/*----------------------------------------------------------------------------*/
static VOID
HifPdmaConfig (
IN void *HifInfoSrc,
IN void *Param
)
{
GL_HIF_INFO_T *HifInfo = (GL_HIF_INFO_T *)HifInfoSrc;
MTK_WCN_HIF_DMA_CONF *Conf = (MTK_WCN_HIF_DMA_CONF *)Param;
UINT_32 RegVal;
/* Assign fixed value */
Conf->Burst = HIF_PDMA_BURST_4_4; /* vs. HIF_BURST_4DW */
Conf->Fix_en = FALSE;
/* AP_P_DMA_G_DMA_2_CON */
PDMA_DBG(("PDMA> Conf->Dir = %d\n", Conf->Dir));
/* AP_DMA_HIF_0_CON */
RegVal = HIF_DMAR_READL(HifInfo, AP_DMA_HIF_0_CON);
RegVal &= ~(ADH_CR_BURST_LEN | ADH_CR_FIX_EN | ADH_CR_DIR);
RegVal |= (((Conf->Burst<<ADH_CR_BURST_LEN_OFFSET)&ADH_CR_BURST_LEN) | \
(Conf->Fix_en<<ADH_CR_FIX_EN_OFFSET) | \
(Conf->Dir));
HIF_DMAR_WRITEL(HifInfo, AP_DMA_HIF_0_CON, RegVal);
PDMA_DBG(("PDMA> AP_DMA_HIF_0_CON = 0x%08x\n", RegVal));
/* AP_DMA_HIF_0_SRC_ADDR */
HIF_DMAR_WRITEL(HifInfo, AP_DMA_HIF_0_SRC_ADDR, Conf->Src);
PDMA_DBG(("PDMA> AP_DMA_HIF_0_SRC_ADDR = 0x%08x\n", Conf->Src));
/* AP_DMA_HIF_0_DST_ADDR */
HIF_DMAR_WRITEL(HifInfo, AP_DMA_HIF_0_DST_ADDR, Conf->Dst);
PDMA_DBG(("PDMA> AP_DMA_HIF_0_DST_ADDR = 0x%08x\n", Conf->Dst));
/* AP_DMA_HIF_0_LEN */
HIF_DMAR_WRITEL(HifInfo, AP_DMA_HIF_0_LEN, (Conf->Count & ADH_CR_LEN));
PDMA_DBG(("PDMA> AP_DMA_HIF_0_LEN = %u\n", (Conf->Count & ADH_CR_LEN)));
}/* End of HifPdmaConfig */
/*----------------------------------------------------------------------------*/
VOID
HifPdmaInit (
GL_HIF_INFO_T *HifInfo
)
{
/* IO remap PDMA register memory */
HifInfo->DmaRegBaseAddr = ioremap(AP_DMA_HIF_BASE, AP_DMA_HIF_0_LENGTH);
/* assign PDMA operators */
HifInfo->DmaOps = &HifPdmaOps;
/* enable PDMA mode */
HifInfo->fgDmaEnable = TRUE;
PDMA_DBG(("PDMA> HifPdmaInit ok!\n"));
}
/*----------------------------------------------------------------------------*/
static VOID
HifPdmaStart(
IN void *HifInfoSrc
)
{
GL_HIF_INFO_T *HifInfo = (GL_HIF_INFO_T *)HifInfoSrc;
UINT_32 RegVal;
/* Enable interrupt */
RegVal = HIF_DMAR_READL(HifInfo, AP_DMA_HIF_0_INT_EN);
HIF_DMAR_WRITEL(HifInfo, AP_DMA_HIF_0_INT_EN, (RegVal | ADH_CR_INTEN_FLAG_0));
/* Start DMA */
RegVal = HIF_DMAR_READL(HifInfo, AP_DMA_HIF_0_EN);
HIF_DMAR_WRITEL(HifInfo, AP_DMA_HIF_0_EN, (RegVal | ADH_CR_EN));
PDMA_DBG(("PDMA> HifPdmaStart...\n"));
} /* End of HifPdmaStart */
/*----------------------------------------------------------------------------*/
VOID
HifPdmaInit (
GL_HIF_INFO_T *HifInfo
)
{
extern phys_addr_t gConEmiPhyBase;
/* IO remap PDMA register memory */
HifInfo->DmaRegBaseAddr = ioremap(AP_DMA_HIF_BASE, AP_DMA_HIF_0_LENGTH);
/* assign PDMA operators */
HifInfo->DmaOps = &HifPdmaOps;
/* enable PDMA mode */
HifInfo->fgDmaEnable = TRUE;
#if 1 // MPU Setting
// WIFI using TOP 512KB
printk("[wlan] MPU region 12, 0x%08x - 0x%08x\n", (UINT_32)gConEmiPhyBase, (UINT_32)(gConEmiPhyBase + 512*1024));
#if defined(CONFIG_ARCH_MT6735) || defined(CONFIG_ARCH_MT6753)
/* for denali 1 & denali 3 */
emi_mpu_set_region_protection(gConEmiPhyBase,
gConEmiPhyBase + 512*1024 - 1,
12,
SET_ACCESS_PERMISSON(FORBIDDEN,FORBIDDEN,FORBIDDEN,FORBIDDEN,FORBIDDEN,NO_PROTECTION,FORBIDDEN,FORBIDDEN));
//#else
// emi_mpu_set_region_protection(gConEmiPhyBase,
// gConEmiPhyBase + 512*1024 - 1,
// 6,
// SET_ACCESS_PERMISSON(FORBIDDEN,NO_PROTECTION,FORBIDDEN,FORBIDDEN));
#endif
#endif
#if !defined(CONFIG_MTK_LEGACY)
g_clk_wifi_pdma = HifInfo->clk_wifi_dma;
#endif
PDMA_DBG(("PDMA> HifPdmaInit ok!\n"));
}
