RT_STATUS phy_RF6052_Config_ParaFile( struct net_device* dev ) { struct r8192_priv *priv = rtllib_priv(dev); u32 u4RegValue = 0; u8 eRFPath; RT_STATUS rtStatus = RT_STATUS_SUCCESS; BB_REGISTER_DEFINITION_T *pPhyReg; for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++) { pPhyReg = &priv->PHYRegDef[eRFPath]; /*----Store original RFENV control type----*/ switch(eRFPath) { case RF90_PATH_A: case RF90_PATH_C: u4RegValue = PHY_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV); break; case RF90_PATH_B : case RF90_PATH_D: u4RegValue = PHY_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16); break; } /*----Set RF_ENV enable----*/ PHY_SetBBReg(dev, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1); udelay(1); /*----Set RF_ENV output high----*/ PHY_SetBBReg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0x1); udelay(1); /* Set bit number of Address and Data for RF register */ PHY_SetBBReg(dev, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); udelay(1); PHY_SetBBReg(dev, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); udelay(1); /*----Initialize RF fom connfiguration file----*/ switch(eRFPath) { case RF90_PATH_A: #if RTL8190_Download_Firmware_From_Header rtStatus= (PHY_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath) == true)?RT_STATUS_SUCCESS:RT_STATUS_FAILURE; #else rtStatus = (PHY_ConfigRFWithParaFile(dev, szRadioAFile, (RF90_RADIO_PATH_E)eRFPath) == true)?RT_STATUS_SUCCESS:RT_STATUS_FAILURE; #endif break; case RF90_PATH_B: #if RTL8190_Download_Firmware_From_Header rtStatus= (PHY_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath) == true)?RT_STATUS_SUCCESS:RT_STATUS_FAILURE; #else rtStatus = (PHY_ConfigRFWithParaFile(dev, szRadioBFile, (RF90_RADIO_PATH_E)eRFPath) == true)?RT_STATUS_SUCCESS:RT_STATUS_FAILURE; #endif break; case RF90_PATH_C: break; case RF90_PATH_D: break; } /*----Restore RFENV control type----*/; switch(eRFPath) { case RF90_PATH_A: case RF90_PATH_C: PHY_SetBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue); break; case RF90_PATH_B : case RF90_PATH_D: PHY_SetBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue); break; } if(rtStatus != RT_STATUS_SUCCESS){ RT_TRACE(COMP_INIT, "phy_RF6052_Config_ParaFile():Radio[%d] Fail!!", eRFPath); goto phy_RF6052_Config_ParaFile_Fail; } } RT_TRACE(COMP_INIT, "<---phy_RF6052_Config_ParaFile()\n"); return rtStatus; phy_RF6052_Config_ParaFile_Fail: return rtStatus; }
int phy_RF6052_Config_ParaFile( IN PADAPTER Adapter ) { u32 u4RegValue; u8 eRFPath; BB_REGISTER_DEFINITION_T *pPhyReg; int rtStatus = _SUCCESS; HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); static char sz88CRadioAFile[] = RTL8188C_PHY_RADIO_A; static char sz88CRadioBFile[] = RTL8188C_PHY_RADIO_B; static char sz92CRadioAFile[] = RTL8192C_PHY_RADIO_A; static char sz92CRadioBFile[] = RTL8192C_PHY_RADIO_B; static char sz88CTestRadioAFile[] = RTL8188C_PHY_RADIO_A; static char sz88CTestRadioBFile[] = RTL8188C_PHY_RADIO_B; static char sz92CTestRadioAFile[] = RTL8192C_PHY_RADIO_A; static char sz92CTestRadioBFile[] = RTL8192C_PHY_RADIO_B; static char sz92DRadioAFile[] = RTL8192D_PHY_RADIO_A; static char sz92DRadioBFile[] = RTL8192D_PHY_RADIO_B; static char sz92DTestRadioAFile[] = RTL8192D_PHY_RADIO_A; static char sz92DTestRadioBFile[] = RTL8192D_PHY_RADIO_B; u8 *pszRadioAFile, *pszRadioBFile; u8 u1bTmp; BOOLEAN bMac1NeedInitRadioAFirst = _FALSE; BOOLEAN bNeedPowerDownRadioA = _FALSE; // 92D RF config zhiyuan 2010/04/07 // Single phy mode: use radio_a radio_b config path_A path_B seperately by MAC0, and MAC1 needn't configure RF; // Dual PHY mode:MAC0 use radio_a config 1st phy path_A, MAC1 use radio_b config 2nd PHY path_A. if(IS_HARDWARE_TYPE_8192D(pHalData)){ if(IS_NORMAL_CHIP(pHalData->VersionID)) { pszRadioAFile = sz92DRadioAFile; pszRadioBFile = sz92DRadioBFile; if(pHalData->interfaceIndex==1) { if(pHalData->MacPhyMode92D==DUALMAC_DUALPHY) pszRadioAFile = sz92DRadioBFile; else return rtStatus; } } else { pszRadioAFile = sz92DTestRadioAFile; pszRadioBFile = sz92DTestRadioBFile; if(pHalData->interfaceIndex==1) { // // when 92D test chip dual mac dual phy mode, if enable MAC1 first, before init RF radio B, // also init RF radio A, and then let radio A go to power down mode. // Note: normal chip need do this or not will be considerred later. // if(pHalData->MacPhyMode92D==DUALMAC_DUALPHY) { u1bTmp = read8(Adapter, REG_MAC0); if (!(u1bTmp&MAC0_ON)) { // MAC0 not enabled, also init radio A before init radio B. // Enable BB and RF #if (DEV_BUS_TYPE == PCI_INTERFACE) //PlatformEFIOWrite1Byte(Adapter, REG_SYS_FUNC_EN, 0xE0); #if 0 MpWritePCIDwordDBI8192C(Adapter, (REG_SYS_FUNC_EN - 2), MpReadPCIDwordDBI8192C(Adapter, (REG_SYS_FUNC_EN - 2), BIT3)&0xFFFCFFFF, BIT3); #endif //u2bTmp = PlatformEFIORead2Byte(Adapter, REG_SYS_FUNC_EN); //PlatformEFIOWrite2Byte(Adapter, REG_SYS_FUNC_EN, u2bTmp|BIT13|BIT0|BIT1); MpWritePCIDwordDBI8192C(Adapter, (REG_SYS_FUNC_EN - 2), MpReadPCIDwordDBI8192C(Adapter, (REG_SYS_FUNC_EN - 2), BIT3)|BIT29|BIT16|BIT17, BIT3); #elif (DEV_BUS_TYPE == USB_INTERFACE) pHalData->bDuringMac1InitRadioA = _TRUE; write16(Adapter, REG_SYS_FUNC_EN, read16(Adapter, REG_SYS_FUNC_EN)&0xFFFC); write16(Adapter, REG_SYS_FUNC_EN, read16(Adapter, REG_SYS_FUNC_EN)|BIT13|BIT0|BIT1); pHalData->bDuringMac1InitRadioA = _FALSE; #endif pHalData->NumTotalRFPath = 2; bMac1NeedInitRadioAFirst = _TRUE; } else { // MAC0 enabled, only init radia B. pszRadioAFile = sz92DTestRadioBFile; } } else { return rtStatus; } } } } else{ if(IS_92C_SERIAL( pHalData->VersionID))// 88c's IPA is different from 92c's { if(IS_NORMAL_CHIP(pHalData->VersionID)) { pszRadioAFile = sz92CRadioAFile; pszRadioBFile = sz92CRadioBFile; } else { pszRadioAFile = sz92CTestRadioAFile; pszRadioBFile = sz92CTestRadioBFile; } } else { if(IS_NORMAL_CHIP(pHalData->VersionID)) { pszRadioAFile = sz88CRadioAFile; pszRadioBFile = sz88CRadioBFile; } else { pszRadioAFile = sz88CTestRadioAFile; pszRadioBFile = sz88CTestRadioBFile; } } } //3//----------------------------------------------------------------- //3// <2> Initialize RF //3//----------------------------------------------------------------- //for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++) for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++) { if (IS_HARDWARE_TYPE_8192D(pHalData) && bMac1NeedInitRadioAFirst) { if (eRFPath == RF90_PATH_A) { pHalData->bDuringMac1InitRadioA = _TRUE; bNeedPowerDownRadioA = _TRUE; } if (eRFPath == RF90_PATH_B) { pHalData->bDuringMac1InitRadioA = _FALSE; bMac1NeedInitRadioAFirst = _FALSE; eRFPath = RF90_PATH_A; pszRadioAFile = sz92DTestRadioBFile; pHalData->NumTotalRFPath = 1; } } pPhyReg = &pHalData->PHYRegDef[eRFPath]; /*----Store original RFENV control type----*/ switch(eRFPath) { case RF90_PATH_A: case RF90_PATH_C: u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV); break; case RF90_PATH_B : case RF90_PATH_D: u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16); break; } /*----Set RF_ENV enable----*/ PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1); udelay_os(1);//PlatformStallExecution(1); /*----Set RF_ENV output high----*/ PHY_SetBBReg(Adapter, pPhyReg->rfintfo, bRFSI_RFENV, 0x1); udelay_os(1);//PlatformStallExecution(1); /* Set bit number of Address and Data for RF register */ PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); // Set 1 to 4 bits for 8255 udelay_os(1);//PlatformStallExecution(1); PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); // Set 0 to 12 bits for 8255 udelay_os(1);//PlatformStallExecution(1); /*----Initialize RF fom connfiguration file----*/ switch(eRFPath) { case RF90_PATH_A: #ifdef CONFIG_EMBEDDED_FWIMG rtStatus= PHY_ConfigRFWithHeaderFile(Adapter,(RF90_RADIO_PATH_E)eRFPath); #else rtStatus = PHY_ConfigRFWithParaFile(Adapter, pszRadioAFile, (RF90_RADIO_PATH_E)eRFPath); #endif break; case RF90_PATH_B: #ifdef CONFIG_EMBEDDED_FWIMG rtStatus= PHY_ConfigRFWithHeaderFile(Adapter,(RF90_RADIO_PATH_E)eRFPath); #else rtStatus = PHY_ConfigRFWithParaFile(Adapter, pszRadioBFile, (RF90_RADIO_PATH_E)eRFPath); #endif break; case RF90_PATH_C: break; case RF90_PATH_D: break; } /*----Restore RFENV control type----*/; switch(eRFPath) { case RF90_PATH_A: case RF90_PATH_C: PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue); break; case RF90_PATH_B : case RF90_PATH_D: PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue); break; } if(rtStatus != _SUCCESS){ //RT_TRACE(COMP_FPGA, DBG_LOUD, ("phy_RF6052_Config_ParaFile():Radio[%d] Fail!!", eRFPath)); goto phy_RF6052_Config_ParaFile_Fail; } } if (IS_HARDWARE_TYPE_8192D(pHalData) && bNeedPowerDownRadioA) { // check MAC0 enable or not again now, if enabled, not power down radio A. u1bTmp = read8(Adapter, REG_MAC0); if (!(u1bTmp&MAC0_ON)) { // power down RF radio A according to YuNan's advice. #if (DEV_BUS_TYPE == PCI_INTERFACE) MpWritePCIDwordDBI8192C(Adapter, rFPGA0_XA_LSSIParameter, 0x00000000, BIT3); #elif (DEV_BUS_TYPE == USB_INTERFACE) pHalData->bDuringMac1InitRadioA = _TRUE; write32(Adapter, rFPGA0_XA_LSSIParameter, 0x00000000); pHalData->bDuringMac1InitRadioA = _FALSE; #endif } bNeedPowerDownRadioA = _FALSE; } //RT_TRACE(COMP_INIT, DBG_LOUD, ("<---phy_RF6052_Config_ParaFile()\n")); return rtStatus; phy_RF6052_Config_ParaFile_Fail: return rtStatus; }
int phy_RF6052_Config_ParaFile( IN PADAPTER Adapter ) { u32 u4RegValue; u8 eRFPath; BB_REGISTER_DEFINITION_T *pPhyReg; int rtStatus = _SUCCESS; HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); static u8 sz88CRadioAFile[] = RTL8188C_PHY_RADIO_A; static u8 sz88CRadioBFile[] = RTL8188C_PHY_RADIO_B; #if DEV_BUS_TYPE==DEV_BUS_USB_INTERFACE static u8 sz88CRadioAFile_mCard[] = RTL8188C_PHY_RADIO_A_mCard; static u8 sz88CRadioBFile_mCard[] = RTL8188C_PHY_RADIO_B_mCard; static u8 sz88CRadioAFile_HP[] = RTL8188C_PHY_RADIO_A_HP; #endif static u8 sz92CCRadioAFile[] = RTL8192C_PHY_RADIO_A; static u8 sz92CRadioBFile[] = RTL8192C_PHY_RADIO_B; u8 *pszRadioAFile, *pszRadioBFile; if(IS_92C_SERIAL( pHalData->VersionID))// 88c's IPA is different from 92c's { pszRadioAFile = (u8*)&sz92CCRadioAFile; pszRadioBFile = (u8*)&sz92CRadioBFile; } else{ #if DEV_BUS_TYPE==DEV_BUS_USB_INTERFACE if( BOARD_MINICARD == pHalData->BoardType) { pszRadioAFile = sz88CRadioAFile_mCard; pszRadioBFile = sz88CRadioBFile_mCard; } else if( BOARD_USB_High_PA == pHalData->BoardType) { pszRadioAFile = sz88CRadioAFile_HP; } else #endif { pszRadioAFile = (u8*)&sz88CRadioAFile; pszRadioBFile = (u8*)&sz88CRadioBFile; } } //3//----------------------------------------------------------------- //3// <2> Initialize RF //3//----------------------------------------------------------------- //for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++) for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++) { pPhyReg = &pHalData->PHYRegDef[eRFPath]; /*----Store original RFENV control type----*/ switch(eRFPath) { case RF90_PATH_A: case RF90_PATH_C: u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV); break; case RF90_PATH_B : case RF90_PATH_D: u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16); break; } /*----Set RF_ENV enable----*/ PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1); rtw_udelay_os(1);//PlatformStallExecution(1); /*----Set RF_ENV output high----*/ PHY_SetBBReg(Adapter, pPhyReg->rfintfo, bRFSI_RFENV, 0x1); rtw_udelay_os(1);//PlatformStallExecution(1); /* Set bit number of Address and Data for RF register */ PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); // Set 1 to 4 bits for 8255 rtw_udelay_os(1);//PlatformStallExecution(1); PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); // Set 0 to 12 bits for 8255 rtw_udelay_os(1);//PlatformStallExecution(1); /*----Initialize RF fom connfiguration file----*/ switch(eRFPath) { case RF90_PATH_A: #ifdef CONFIG_EMBEDDED_FWIMG rtStatus= PHY_ConfigRFWithHeaderFile(Adapter,(RF90_RADIO_PATH_E)eRFPath); #else rtStatus = PHY_ConfigRFWithParaFile(Adapter, pszRadioAFile, (RF90_RADIO_PATH_E)eRFPath); #endif break; case RF90_PATH_B: #ifdef CONFIG_EMBEDDED_FWIMG rtStatus= PHY_ConfigRFWithHeaderFile(Adapter,(RF90_RADIO_PATH_E)eRFPath); #else rtStatus = PHY_ConfigRFWithParaFile(Adapter, pszRadioBFile, (RF90_RADIO_PATH_E)eRFPath); #endif break; case RF90_PATH_C: break; case RF90_PATH_D: break; } /*----Restore RFENV control type----*/; switch(eRFPath) { case RF90_PATH_A: case RF90_PATH_C: PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue); break; case RF90_PATH_B : case RF90_PATH_D: PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue); break; } if(rtStatus != _SUCCESS){ //RT_TRACE(COMP_FPGA, DBG_LOUD, ("phy_RF6052_Config_ParaFile():Radio[%d] Fail!!", eRFPath)); goto phy_RF6052_Config_ParaFile_Fail; } } //RT_TRACE(COMP_INIT, DBG_LOUD, ("<---phy_RF6052_Config_ParaFile()\n")); return rtStatus; phy_RF6052_Config_ParaFile_Fail: return rtStatus; }