PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2", "pfc-sh73a0", "fsia_data_out", "fsia"), /* I2C3 */ PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.3", "pfc-sh73a0", "i2c3_1", "i2c3"), /* LCD */ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh73a0", "lcd_data24", "lcd"), PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh73a0", "lcd_sync", "lcd"), /* MMCIF */ PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0", "mmc0_data8_0", "mmc0"), PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0", "mmc0_ctrl_0", "mmc0"), PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mmcif.0", "pfc-sh73a0", "PORT279", pin_pullup_conf), PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0", "mmc0_data8_0", pin_pullup_conf), /* SCIFA4 */ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0", "scifa4_data", "scifa4"), PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0", "scifa4_ctrl", "scifa4"), /* SDHI0 */ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0", "sdhi0_data4", "sdhi0"), PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0", "sdhi0_ctrl", "sdhi0"), PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0", "sdhi0_cd", "sdhi0"), PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0", "keysc_out5", "keysc"), PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0", "keysc_out6_0", "keysc"), PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0", "keysc_out7_0", "keysc"), PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0", "keysc_out8_0", "keysc"), PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0", "keysc_in8", pin_pullup_conf), /* MMCIF */ PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0", "mmc0_data8_0", "mmc0"), PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0", "mmc0_ctrl_0", "mmc0"), PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mmcif.0", "pfc-sh73a0", "PORT279", pin_pullup_conf), PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0", "mmc0_data8_0", pin_pullup_conf), /* SCIFA2 (UART2) */ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0", "scifa2_data_0", "scifa2"), PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0", "scifa2_ctrl_0", "scifa2"), /* SCIFA4 (UART1) */ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0", "scifa4_data", "scifa4"), PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0", "scifa4_ctrl", "scifa4"), /* SCIFB (BT) */ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.8", "pfc-sh73a0", "scifb_data_0", "scifb"),
static unsigned long pin_cfgs_ode[] = { PAD_CTL_ODE, }; static unsigned long pin_cfgs_dse_low[] = { PAD_CTL_DSE_LOW, }; static const struct pinctrl_map armadillo_box_ws1_pinctrl_map[] = { /* uart3 */ PIN_MAP_MUX_GROUP_DEFAULT("imx21-uart.2", "imx25-pinctrl.0", "cspi1_mosi__uart3_rxd_mux", "uart3"), PIN_MAP_MUX_GROUP_DEFAULT("imx21-uart.2", "imx25-pinctrl.0", "cspi1_miso__uart3_txd_mux", "uart3"), PIN_MAP_CONFIGS_PIN_DEFAULT("imx21-uart.2", "imx25-pinctrl.0", "MX25_PAD_CSPI1_MOSI", pin_cfgs_100kup), PIN_MAP_CONFIGS_PIN_DEFAULT("imx21-uart.2", "imx25-pinctrl.0", "MX25_PAD_CSPI1_MISO", pin_cfgs_none), /* FEC */ PIN_MAP_MUX_GROUP_DEFAULT("imx25-fec.0", "imx25-pinctrl.0", "fec_mdc__fec_mdc", "fec"), PIN_MAP_MUX_GROUP_DEFAULT("imx25-fec.0", "imx25-pinctrl.0", "fec_mdio__fec_mdio", "fec"), PIN_MAP_MUX_GROUP_DEFAULT("imx25-fec.0", "imx25-pinctrl.0", "fec_tdata0__fec_tdata0", "fec"), PIN_MAP_MUX_GROUP_DEFAULT("imx25-fec.0", "imx25-pinctrl.0", "fec_tdata1__fec_tdata1", "fec"), PIN_MAP_MUX_GROUP_DEFAULT("imx25-fec.0", "imx25-pinctrl.0", "fec_tx_en__fec_tx_en", "fec"), PIN_MAP_MUX_GROUP_DEFAULT("imx25-fec.0", "imx25-pinctrl.0",
static unsigned long __maybe_unused pin_cfgs_dse_low[] = { PAD_CTL_DSE_LOW, }; static unsigned long __maybe_unused pin_cfgs_pke[] = { PAD_CTL_PKE, }; static const struct pinctrl_map armadillo4x0_con9_con14_pinctrl_map[] = { /* uart3 */ #if defined(CONFIG_ARMADILLO4X0_UART3_CON9) PIN_MAP_MUX_GROUP_DEFAULT("imx21-uart.2", "imx25-pinctrl.0", "cspi1_mosi__uart3_rxd_mux", "uart3"), PIN_MAP_MUX_GROUP_DEFAULT("imx21-uart.2", "imx25-pinctrl.0", "cspi1_miso__uart3_txd_mux", "uart3"), PIN_MAP_CONFIGS_PIN_DEFAULT("imx21-uart.2", "imx25-pinctrl.0", "MX25_PAD_CSPI1_MOSI", pin_cfgs_100kup), PIN_MAP_CONFIGS_PIN_DEFAULT("imx21-uart.2", "imx25-pinctrl.0", "MX25_PAD_CSPI1_MISO", pin_cfgs_none), #endif #if defined(CONFIG_ARMADILLO4X0_UART3_HW_FLOW_CON9) PIN_MAP_MUX_GROUP_DEFAULT("imx21-uart.2", "imx25-pinctrl.0", "cspi1_ss1__uart3_rts", "uart3"), PIN_MAP_MUX_GROUP_DEFAULT("imx21-uart.2", "imx25-pinctrl.0", "cspi1_sclk__uart3_cts", "uart3"), PIN_MAP_CONFIGS_PIN_DEFAULT("imx21-uart.2", "imx25-pinctrl.0", "MX25_PAD_CSPI1_SS1", pin_cfgs_100kup), PIN_MAP_CONFIGS_PIN_DEFAULT("imx21-uart.2", "imx25-pinctrl.0", "MX25_PAD_CSPI1_SCLK", pin_cfgs_none), #endif /* uart5 */