/**
* \brief Disable all clocks.
*/
extern void PMC_DisableAllClocks(void)
{
uint32_t read_reg;
PMC->PMC_SCDR = PMC_SCDR_PCK0 | PMC_SCDR_PCK1 | PMC_SCDR_PCK2; /* disable PCK */
_PMC_SwitchMck2MainClock();
PMC->CKGR_PLLR = PMC->CKGR_PLLR & ~CKGR_PLLR_MUL_Msk; /* disable PLL A */
_PMC_SwitchMck2SlowClock();
read_reg = PMC->CKGR_MOR;
read_reg = (read_reg & ~CKGR_MOR_MOSCRCEN) | CKGR_MOR_KEY(0x37u); /* disable RC OSC */
PMC->CKGR_MOR = read_reg;
PMC_DisableAllPeripherals(); /* disable all peripheral clocks */
}
/**
* \brief Disable all clocks.
*/
void PMC_DisableAllClocks(void)
{
uint32_t read_reg;
PMC->PMC_SCDR = PMC_SCDR_PCK0 | PMC_SCDR_PCK1 | PMC_SCDR_PCK2 | PMC_SCDR_PCK3 |
PMC_SCDR_PCK4 | PMC_SCDR_PCK5 | PMC_SCDR_PCK6; /* disable PCK */
_PMC_SwitchMck2MainClock();
PMC->CKGR_PLLAR = PMC->CKGR_PLLAR & ~CKGR_PLLAR_MULA_Msk; /* disable PLL A */
_PMC_SwitchMck2SlowClock();
read_reg = PMC->CKGR_MOR;
read_reg = (read_reg & ~CKGR_MOR_MOSCRCEN) | CKGR_MOR_KEY_PASSWD;
/* disable RC OSC */
PMC->CKGR_MOR = read_reg;
PMC_DisableAllPeripherals(); /* disable all peripheral clocks */
}
