/**
* \brief Configures a TWI peripheral to operate in master mode, at the given
* frequency (in Hz). The duty cycle of the TWI clock is set to 50%.
* \param pTwi Pointer to an Twi instance.
* \param twck Desired TWI clock frequency.
* \param mck Master clock frequency.
*/
void TWI_ConfigureMaster( Twi* pTwi, uint32_t dwTwCk, uint32_t dwMCk )
{
uint32_t dwCkDiv = 0 ;
uint32_t dwClDiv ;
uint32_t dwOk = 0 ;
uint32_t id = ID_TWI0;
uint32_t maxClock;
TRACE_DEBUG( "TWI_ConfigureMaster()\n\r" ) ;
assert( pTwi ) ;
/* SVEN: TWI Slave Mode Enabled */
pTwi->TWI_CR = TWI_CR_SVEN ;
/* Reset the TWI */
pTwi->TWI_CR = TWI_CR_SWRST ;
pTwi->TWI_RHR ;
/* TWI Slave Mode Disabled, TWI Master Mode Disabled. */
pTwi->TWI_CR = TWI_CR_SVDIS ;
pTwi->TWI_CR = TWI_CR_MSDIS ;
/* Set master mode */
pTwi->TWI_CR = TWI_CR_MSEN ;
if ((uint32_t)pTwi == (uint32_t)TWI0) id = ID_TWI0;
else if ((uint32_t)pTwi == (uint32_t)TWI1) id = ID_TWI1;
else if ((uint32_t)pTwi == (uint32_t)TWI2) id = ID_TWI2;
maxClock = PMC_SetPeriMaxClock(id, dwMCk);
/* Configure clock */
while ( !dwOk )
{
dwClDiv = ((maxClock / (2 * dwTwCk)) - 8) / (1<<dwCkDiv) ;
if ( dwClDiv <= 255 )
{
dwOk = 1 ;
}
else
{
dwCkDiv++ ;
}
}
assert( dwCkDiv < 8 ) ;
TRACE_DEBUG( "Using CKDIV = %u and CLDIV/CHDIV = %u\n\r", dwCkDiv, dwClDiv ) ;
pTwi->TWI_CWGR = 0 ;
pTwi->TWI_CWGR = (dwCkDiv << 16) | (dwClDiv << 8) | dwClDiv ;
}
/**
* \brief Configures a SSC peripheral.If the divided clock is not used, the master
* clock frequency can be set to 0.
* \note The emitter and transmitter are disabled by this function.
* \param ssc Pointer to an SSC instance.
* \param bitRate bit rate.
* \param masterClock master clock.
*/
void SSC_Configure(Ssc *ssc, uint32_t bitRate, uint32_t masterClock)
{
uint32_t id;
uint32_t maxClock;
id = (ssc == SSC0 )? ID_SSC0 : ID_SSC1;
maxClock = PMC_SetPeriMaxClock(id, masterClock);
/* Reset, disable receiver & transmitter */
ssc->SSC_CR = SSC_CR_RXDIS | SSC_CR_TXDIS | SSC_CR_SWRST;
/* Configure clock frequency */
if (bitRate != 0) {
ssc->SSC_CMR = maxClock / (2 * bitRate);
} else {
ssc->SSC_CMR = 0;
}
/* Enable SSC peripheral clock */
//PMC_EnablePeripheral(id);
}
