/** * Configure a BAM pipe for satellite MTI use * */ void bam_pipe_satellite_mti(void *base, u32 pipe, u32 irq_gen_addr, u32 ee) { bam_write_reg(base, P_IRQ_EN(pipe), 0); bam_write_reg(base, P_IRQ_DEST_ADDR(pipe), irq_gen_addr); bam_write_reg_field(base, IRQ_SIC_SEL, (1 << pipe), 1); bam_write_reg_field(base, IRQ_SRCS_MSK, (1 << pipe), 1); }
/** * Configure a BAM pipe for satellite MTI use * */ void bam_pipe_satellite_mti(void *base, u32 pipe, u32 irq_gen_addr, u32 ee) { bam_write_reg(base, P_IRQ_EN(pipe), 0); #ifndef CONFIG_SPS_SUPPORT_NDP_BAM bam_write_reg(base, P_IRQ_DEST_ADDR(pipe), irq_gen_addr); bam_write_reg_field(base, IRQ_SIC_SEL, (1 << pipe), 1); #endif bam_write_reg_field(base, IRQ_SRCS_MSK, (1 << pipe), 1); }
void bam_pipe_set_mti(void *base, u32 pipe, enum bam_enable irq_en, u32 src_mask, u32 irq_gen_addr) { #ifndef CONFIG_SPS_SUPPORT_NDP_BAM bam_write_reg(base, P_IRQ_DEST_ADDR(pipe), irq_gen_addr); #endif if (!irq_en) src_mask = 0; bam_write_reg(base, P_IRQ_EN(pipe), src_mask); }
/** * Configure MTI for a BAM pipe * */ void bam_pipe_set_mti(void *base, u32 pipe, enum bam_enable irq_en, u32 src_mask, u32 irq_gen_addr) { /* * MTI use is only supported on BAMs when global config is controlled * by a remote processor. * Consequently, the global configuration register to enable SIC (MTI) * support cannot be accessed. * The remote processor must be relied upon to enable the SIC and the * interrupt. Since the remote processor enable both SIC and interrupt, * the interrupt enable mask must be set to zero for polling mode. */ #ifndef CONFIG_SPS_SUPPORT_NDP_BAM bam_write_reg(base, P_IRQ_DEST_ADDR(pipe), irq_gen_addr); #endif if (!irq_en) src_mask = 0; bam_write_reg(base, P_IRQ_EN(pipe), src_mask); }