/** * Reset inactivity timer for a BAM pipe * */ void bam_pipe_timer_reset(void *base, u32 pipe) { /* reset */ bam_write_reg_field(base, P_TIMER_CTRL(pipe), P_TIMER_RST, 0); /* active */ bam_write_reg_field(base, P_TIMER_CTRL(pipe), P_TIMER_RST, 1); }
/** * Configure inactivity timer count for a BAM pipe * */ void bam_pipe_timer_config(void *base, u32 pipe, enum bam_pipe_timer_mode mode, u32 timeout_count) { bam_write_reg_field(base, P_TIMER_CTRL(pipe), P_TIMER_MODE, mode); bam_write_reg_field(base, P_TIMER_CTRL(pipe), P_TIMER_TRSHLD, timeout_count); }
void bam_pipe_timer_reset(void *base, u32 pipe) { bam_write_reg_field(base, P_TIMER_CTRL(pipe), P_TIMER_RST, 0); bam_write_reg_field(base, P_TIMER_CTRL(pipe), P_TIMER_RST, 1); }
/** * Reset inactivity timer for a BAM pipe * */ void bam_pipe_timer_reset(void *base, u32 pipe) { u32 for_all_pipes = 0; #ifdef CONFIG_SPS_SUPPORT_NDP_BAM for_all_pipes = bam_read_reg_field(base, REVISION, BAM_NUM_INACTIV_TMRS); #endif if (for_all_pipes) { #ifdef CONFIG_SPS_SUPPORT_NDP_BAM /* reset */ bam_write_reg_field(base, TIMER_CTRL, TIMER_RST, 0); /* active */ bam_write_reg_field(base, TIMER_CTRL, TIMER_RST, 1); #endif } else { /* reset */ bam_write_reg_field(base, P_TIMER_CTRL(pipe), P_TIMER_RST, 0); /* active */ bam_write_reg_field(base, P_TIMER_CTRL(pipe), P_TIMER_RST, 1); } }
/** * Configure inactivity timer count for a BAM pipe * */ void bam_pipe_timer_config(void *base, u32 pipe, enum bam_pipe_timer_mode mode, u32 timeout_count) { u32 for_all_pipes = 0; #ifdef CONFIG_SPS_SUPPORT_NDP_BAM for_all_pipes = bam_read_reg_field(base, REVISION, BAM_NUM_INACTIV_TMRS); #endif if (for_all_pipes) { #ifdef CONFIG_SPS_SUPPORT_NDP_BAM bam_write_reg_field(base, TIMER_CTRL, TIMER_MODE, mode); bam_write_reg_field(base, TIMER_CTRL, TIMER_TRSHLD, timeout_count); #endif } else { bam_write_reg_field(base, P_TIMER_CTRL(pipe), P_TIMER_MODE, mode); bam_write_reg_field(base, P_TIMER_CTRL(pipe), P_TIMER_TRSHLD, timeout_count); } }