/**
Invalidates the entire instruction cache in cache coherency domain of the
calling CPU.
**/
VOID
EFIAPI
InvalidateInstructionCache (
VOID
)
{
PalCall (PAL_CACHE_FLUSH, PAL_CACHE_FLUSH_INSTRUCTION_ALL, PAL_CACHE_FLUSH_INVALIDATE_LINES | PAL_CACHE_FLUSH_NO_INTERRUPT, 0);
}
/**
Writes back and invalidates the entire data cache in cache coherency domain
of the calling CPU.
Writes back and invalidates the entire data cache in cache coherency domain
of the calling CPU. This function guarantees that all dirty cache lines are
written back to system memory, and also invalidates all the data cache lines
in the cache coherency domain of the calling CPU.
**/
VOID
EFIAPI
WriteBackInvalidateDataCache (
VOID
)
{
PalCall (PAL_CACHE_FLUSH, PAL_CACHE_FLUSH_DATA_ALL, PAL_CACHE_FLUSH_INVALIDATE_LINES | PAL_CACHE_FLUSH_NO_INTERRUPT, 0);
}
/**
Places the CPU in a sleep state until an interrupt is received.
Places the CPU in a sleep state until an interrupt is received. If interrupts
are disabled prior to calling this function, then the CPU will be placed in a
sleep state indefinitely.
**/
VOID
EFIAPI
CpuSleep (
VOID
)
{
UINT64 Tpr;
//
// It is the TPR register that controls if external interrupt would bring processor in LIGHT HALT low-power state
// back to normal state. PAL_HALT_LIGHT does not depend on PSR setting.
// So here if interrupts are disabled (via PSR.i), TRP.mmi needs to be set to prevent processor being interrupted by external interrupts.
// If interrupts are enabled, then just use current TRP setting.
//
if (GetInterruptState ()) {
//
// If interrupts are enabled, then call PAL_HALT_LIGHT with the current TPR setting.
//
PalCall (PAL_HALT_LIGHT, 0, 0, 0);
} else {
//
// If interrupts are disabled on entry, then mask all interrupts in TPR before calling PAL_HALT_LIGHT.
//
//
// Save TPR
//
Tpr = AsmReadTpr();
//
// Set TPR.mmi to mask all external interrupts
//
AsmWriteTpr (BIT16 | Tpr);
PalCall (PAL_HALT_LIGHT, 0, 0, 0);
//
// Restore TPR
//
AsmWriteTpr (Tpr);
}
}
**/
UINT64
EFIAPI
GetPerformanceCounterProperties (
OUT UINT64 *StartValue, OPTIONAL
OUT UINT64 *EndValue OPTIONAL
)
{
PAL_CALL_RETURN PalRet;
UINT64 BaseFrequence;
//
// Get processor base frequency
//
PalRet = PalCall (PAL_FREQ_BASE, 0, 0, 0);
ASSERT (PalRet.Status == 0);
BaseFrequence = PalRet.r9;
//
// Get processor frequency ratio
//
PalRet = PalCall (PAL_FREQ_RATIOS, 0, 0, 0);
ASSERT (PalRet.Status == 0);
//
// Start value of counter is 0
//
if (StartValue != NULL) {
*StartValue = 0;
}
