VOID STATIC PcieAlibUpdatePciePortDataCallback ( IN PCIe_ENGINE_CONFIG *Engine, IN OUT VOID *Buffer, IN PCIe_PLATFORM_CONFIG *Pcie ) { _ALIB_PORT_DATA *PortData; PortData = &((ALIB_DATA *) Buffer)->PortData[Engine->Type.Port.PcieBridgeId].PortData; if (PcieConfigIsEngineAllocated (Engine) && (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled || PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS))) { // // Various speed capability // PortData->PciePortMaxSpeed = (UINT8) PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_MAX, Engine); PortData->PciePortCurSpeed = (UINT8) PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_BOOT, Engine); PortData->PciePortDcSpeed = PcieGen1; PortData->PciePortAcSpeed = PortData->PciePortMaxSpeed; if (Pcie->PsppPolicy == PsppBalanceLow) { PortData->PciePortAcSpeed = PcieGen1; } if (PcieConfigIsSbPcieEngine (Engine)) { PortData->PcieSbPort = 0x1; PortData->PciePortAcSpeed = PortData->PciePortMaxSpeed; } if (Engine->Type.Port.PortData.MiscControls.LinkSafeMode != 0) { PortData->PcieLinkSafeMode = 0x1; PortData->PcieLocalOverrideSpeed = Engine->Type.Port.PortData.MiscControls.LinkSafeMode; } // // various port capability // PortData->StartPhyLane = (UINT8) Engine->EngineData.StartLane; PortData->EndPhyLane = (UINT8) Engine->EngineData.EndLane; PortData->StartCoreLane = (UINT8) Engine->Type.Port.StartCoreLane; PortData->EndCoreLane = (UINT8) Engine->Type.Port.EndCoreLane; PortData->PortId = Engine->Type.Port.PortId; PortData->LinkHotplug = Engine->Type.Port.PortData.LinkHotplug; PortData->PciDev = (UINT8) Engine->Type.Port.Address.Address.Device; PortData->PciFun = (UINT8) Engine->Type.Port.Address.Address.Function; } else { PortData->PciePortMaxSpeed = PcieGen1; PortData->PciePortCurSpeed = PcieGen1; PortData->PciePortDcSpeed = PcieGen1; PortData->PciePortAcSpeed = PcieGen1; PortData->PcieLocalOverrideSpeed = PcieGen1; } }
VOID STATIC PcieUtilGlobalGenCapabilityCallback ( IN PCIe_ENGINE_CONFIG *Engine, IN OUT VOID *Buffer, IN PCIe_PLATFORM_CONFIG *Pcie ) { PCIE_GLOBAL_GEN_CAP_WORKSPACE *GlobalGenCapability; PCIE_LINK_SPEED_CAP LinkSpeedCapability; PCIE_HOTPLUG_TYPE HotPlugType; UINT32 Flags; Flags = PCIE_GLOBAL_GEN_CAP_ALL_PORTS; GlobalGenCapability = (PCIE_GLOBAL_GEN_CAP_WORKSPACE*) Buffer; LinkSpeedCapability = PcieGen1; if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) { Flags |= PCIE_GLOBAL_GEN_CAP_TRAINED_PORTS; } HotPlugType = Engine->Type.Port.PortData.LinkHotplug; if ((HotPlugType == HotplugBasic) || (HotPlugType == HotplugServer) || (HotPlugType == HotplugEnhanced)) { Flags |= PCIE_GLOBAL_GEN_CAP_HOTPLUG_PORTS; } if ((GlobalGenCapability->Flags & Flags) != 0) { ASSERT ((GlobalGenCapability->Flags & (PCIE_PORT_GEN_CAP_MAX | PCIE_PORT_GEN_CAP_BOOT)) != 0); LinkSpeedCapability = PcieFmGetLinkSpeedCap (GlobalGenCapability->Flags, Engine, Pcie); if (GlobalGenCapability->LinkSpeedCapability < LinkSpeedCapability) { GlobalGenCapability->LinkSpeedCapability = LinkSpeedCapability; } } }
VOID STATIC PciePortPostS3InitCallback ( IN PCIe_ENGINE_CONFIG *Engine, IN OUT VOID *Buffer, IN PCIe_PLATFORM_CONFIG *Pcie ) { PCIE_LINK_SPEED_CAP LinkSpeedCapability; ASSERT (Engine->EngineData.EngineType == PciePortEngine); LinkSpeedCapability = PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_BOOT, Engine, Pcie); PcieSetLinkSpeedCap (LinkSpeedCapability, Engine, Pcie); if (Engine->Type.Port.PortData.MiscControls.LinkSafeMode == PcieGen1) { PcieLinkSafeMode (Engine, Pcie); } if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) { PcieForceCompliance (Engine, Pcie); } if (!Engine->Type.Port.IsSB) { if ((PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS) || ((Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) && (Engine->Type.Port.PortData.LinkHotplug != HotplugInboard)) || (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1))) { PcieTrainingSetPortState (Engine, LinkStateResetExit, FALSE, Pcie); } else { PcieTrainingSetPortState (Engine, LinkStateDeviceNotPresent, FALSE, Pcie); } PcieConfigUpdatePortStatus (Engine, 0, INIT_STATUS_PCIE_TRAINING_SUCCESS); } else { PcieTrainingSetPortState (Engine, LinkStateTrainingSuccess, FALSE, Pcie); } }
VOID STATIC PciePortPostInitCallback ( IN PCIe_ENGINE_CONFIG *Engine, IN OUT VOID *Buffer, IN PCIe_PLATFORM_CONFIG *Pcie ) { PCIE_LINK_SPEED_CAP LinkSpeedCapability; ASSERT (Engine->EngineData.EngineType == PciePortEngine); if (Engine->Type.Port.PortData.MiscControls.LinkSafeMode == PcieGen1) { PcieLinkSafeMode (Engine, Pcie); } LinkSpeedCapability = PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_BOOT, Engine, Pcie); PcieSetLinkSpeedCap (LinkSpeedCapability, Engine, Pcie); // Retrain only present port to Gen2 if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS) && (LinkSpeedCapability > PcieGen1) && !Engine->Type.Port.IsSB) { PcieTrainingSetPortState (Engine, LinkStateRetrain, FALSE, Pcie); PcieConfigUpdatePortStatus (Engine, 0, INIT_STATUS_PCIE_TRAINING_SUCCESS); } // Train ports forced to compliance if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) { PcieForceCompliance (Engine, Pcie); PcieTrainingSetPortState (Engine, LinkStateResetExit, FALSE, Pcie); } }
VOID STATIC PciePostS3PortInitCallbackML ( IN PCIe_ENGINE_CONFIG *Engine, IN OUT VOID *Buffer, IN PCIe_PLATFORM_CONFIG *Pcie ) { PCIE_LINK_SPEED_CAP LinkSpeedCapability; PCIE_LINK_TRAINING_STATE State; ASSERT (Engine->EngineData.EngineType == PciePortEngine); LinkSpeedCapability = PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_BOOT, Engine); PcieSetLinkSpeedCapV4 (LinkSpeedCapability, Engine, Pcie); if (Engine->Type.Port.PortData.MiscControls.LinkSafeMode == PcieGen1) { PcieLinkSafeMode (Engine, Pcie); } if (!PcieConfigIsSbPcieEngine (Engine)) { // // General Port // State = LinkStateDeviceNotPresent; if (Engine->Type.Port.PortData.LinkHotplug == HotplugDisabled || Engine->Type.Port.PortData.LinkHotplug == HotplugInboard) { // // Non hotplug device: we only check status from previous boot // if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) { State = LinkStateResetExit; } } else { UINT32 PcieScratch; // // Get endpoint staus from scratch // PcieScratch = PciePortRegisterRead (Engine, DxFxxE4_x01_ADDRESS, Pcie); // // Hotplug device: we check ep status if reported // if ((PcieScratch & 0x1) == 0) { State = LinkStateResetExit; } } // // For compliance we always leave link in enabled state // if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode) { State = LinkStateResetExit; } PcieConfigUpdatePortStatus (Engine, 0, INIT_STATUS_PCIE_TRAINING_SUCCESS); } else { // // SB port // State = LinkStateTrainingSuccess; } PcieTrainingSetPortStateV2 (Engine, State, FALSE, Pcie); }
VOID STATIC PcieAlibSetPortInfoCallback ( IN PCIe_ENGINE_CONFIG *Engine, IN OUT VOID *Buffer, IN PCIe_PLATFORM_CONFIG *Pcie ) { ALIB_PORT_INFO_PACKAGE *PortInfoPackage; UINT8 PortIndex; PortInfoPackage = (ALIB_PORT_INFO_PACKAGE*) Buffer; PortIndex = (UINT8) Engine->Type.Port.Address.Address.Device - 2; PortInfoPackage->PortInfo[PortIndex].StartPhyLane = (UINT8) Engine->EngineData.StartLane; PortInfoPackage->PortInfo[PortIndex].EndPhyLane = (UINT8) Engine->EngineData.EndLane; PortInfoPackage->PortInfo[PortIndex].StartCoreLane = (UINT8) Engine->Type.Port.StartCoreLane; PortInfoPackage->PortInfo[PortIndex].EndCoreLane = (UINT8) Engine->Type.Port.EndCoreLane; PortInfoPackage->PortInfo[PortIndex].PortId = Engine->Type.Port.PortId; // PortInfoPackage->PortInfo[PortIndex].WrapperId = 0x0130 | (PcieEngineGetParentWrapper (Engine)->WrapId); PortInfoPackage->PortInfo[PortIndex].WrapperId = 0x0130u | (PcieEngineGetParentWrapper (Engine)->WrapId); PortInfoPackage->PortInfo[PortIndex].LinkHotplug = Engine->Type.Port.PortData.LinkHotplug; PortInfoPackage->PortInfo[PortIndex].MaxSpeedCap = (UINT8) PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_MAX, Engine, Pcie); }
VOID STATIC PcieAlibSetPortMaxSpeedCallback ( IN PCIe_ENGINE_CONFIG *Engine, IN OUT VOID *Buffer, IN PCIe_PLATFORM_CONFIG *Pcie ) { UINT8 *PsppMaxPortSpeedPackage; PsppMaxPortSpeedPackage = (UINT8*) Buffer; if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled || PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) { PsppMaxPortSpeedPackage[(Engine->Type.Port.Address.Address.Device - 2) * 2 + 1] = (UINT8) PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_MAX, Engine, Pcie); } }