/** * Relinquish control to DDI for specific lanes * * * @param[in] Wrapper Pointer to wrapper configuration descriptor * @param[in] Pcie Pointer to global PCIe configuration */ VOID PcieSetDdiOwnPhyV4 ( IN PCIe_WRAPPER_CONFIG *Wrapper, IN PCIe_PLATFORM_CONFIG *Pcie ) { UINT32 LaneBitmap; UINT8 Slice; if (PcieLibIsDdiWrapper (Wrapper)) { IDS_HDT_CONSOLE (GNB_TRACE, "PcieSetDdiOwnPhyV4 Enter\n"); LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_DDI_PHY_NATIVE, 0, Wrapper); for (Slice = 0; Slice < 4; Slice++) { if ((LaneBitmap & (1 << (Slice * 4))) != 0) { PcieRegisterRMW ( Wrapper, WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8040_ADDRESS + Slice), D0F0xE4_WRAP_8040_OwnSlice_MASK, 1 << D0F0xE4_WRAP_8040_OwnSlice_OFFSET, FALSE, Pcie ); } } IDS_HDT_CONSOLE (GNB_TRACE, "PcieSetDdiOwnPhyV4 Exit\n"); } }
/** * Relinquish control to DDI for specific lanes * * * @param[in] Wrapper Pointer to wrapper configuration descriptor * @param[in] Pcie Pointer to global PCIe configuration */ VOID PcieSetDdiOwnPhy ( IN PCIe_WRAPPER_CONFIG *Wrapper, IN PCIe_PLATFORM_CONFIG *Pcie ) { UINT32 LaneBitmap; if (PcieLibIsDdiWrapper (Wrapper)) { IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmSetDdiOwnPhy Enter\n"); LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_DDI_ALLOCATED, 0, Wrapper, Pcie); IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmSetDdiOwnPhy Exit\n"); } }
/** * Relinquish control to DDI for specific lanes * * * @param[in] Wrapper Pointer to wrapper configuration descriptor * @param[in] Pcie Pointer to global PCIe configuration */ VOID PcieSetDdiOwnPhy ( IN PCIe_WRAPPER_CONFIG *Wrapper, IN PCIe_PLATFORM_CONFIG *Pcie ) { D0F0xE4_WRAP_8040_STRUCT D0F0xE4_WRAP_8040; UINT32 LaneBitmap; if (PcieLibIsDdiWrapper (Wrapper)) { IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmSetDdiOwnPhy Enter\n"); LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_DDI_PHY_NATIVE, 0, Wrapper); D0F0xE4_WRAP_8040.Value = PcieRegisterRead ( Wrapper, WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8040_ADDRESS), Pcie ); if ((LaneBitmap & BIT0) != 0) { D0F0xE4_WRAP_8040.Field.OwnPhyA = 0x1; } if ((LaneBitmap & BIT4) != 0) { D0F0xE4_WRAP_8040.Field.OwnPhyB = 0x1; } if ((LaneBitmap & BIT8) != 0) { D0F0xE4_WRAP_8040.Field.OwnPhyC = 0x1; } if ((LaneBitmap & BIT12) != 0) { D0F0xE4_WRAP_8040.Field.OwnPhyD = 0x1; } PcieRegisterWrite ( Wrapper, WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8040_ADDRESS), D0F0xE4_WRAP_8040.Value, FALSE, Pcie ); IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmSetDdiOwnPhy Exit\n"); } }
/** * Configure engine list to support lane allocation according to configuration ID. * * PCIE port * * * 1 Check if lane from user port descriptor (PCIe_PORT_DESCRIPTOR) belongs to wrapper (PCIe_WRAPPER_CONFIG) * 2 Check if link width from user descriptor less or equal to link width of engine (PCIe_ENGINE_CONFIG) * 3 Check if link width is correct. Correct link width for PCIe port x1, x2, x4, x8, x16, correct link width for DDI x4, x8 * 4 Check if user port device number (PCIe_PORT_DESCRIPTOR) match engine port device number (PCIe_ENGINE_CONFIG) * 5 Check if lane can be muxed * * * DDI Link * * 1 Check if lane from user port descriptor (PCIe_DDI_DESCRIPTOR) belongs to wrapper (PCIe_WRAPPER_CONFIG) * 2 Check lane from (PCIe_DDI_DESCRIPTOR) match exactly phy lane (PCIe_ENGINE_CONFIG) * * * * @param[in] ComplexDescriptor Pointer to used define complex descriptor * @param[in,out] Wrapper Pointer to wrapper config descriptor * @param[in] Pcie Pointer to global PCIe configuration * @retval AGESA_SUCCESS Topology successfully mapped * @retval AGESA_ERROR Topology can not be mapped */ AGESA_STATUS PcieMapTopologyOnWrapper ( IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor, IN OUT PCIe_WRAPPER_CONFIG *Wrapper, IN PCIe_PLATFORM_CONFIG *Pcie ) { AGESA_STATUS AgesaStatus; AGESA_STATUS Status; PCIe_ENGINE_CONFIG *EngineList; UINT32 WrapperPhyLaneBitMap; IDS_HDT_CONSOLE (GNB_TRACE, "PcieMapTopologyOnWrapper Enter\n"); AgesaStatus = AGESA_SUCCESS; if (PcieLibIsPcieWrapper (Wrapper)) { Status = PcieEnginesToWrapper (PciePortEngine, ComplexDescriptor, Wrapper); AGESA_STATUS_UPDATE (Status, AgesaStatus); if (Status == AGESA_ERROR) { // If we can not map topology on wrapper we can not enable any engines. PutEventLog ( AGESA_ERROR, GNB_EVENT_INVALID_PCIE_TOPOLOGY_CONFIGURATION, Wrapper->WrapId, Wrapper->StartPhyLane, Wrapper->EndPhyLane, 0, GnbLibGetHeader (Pcie) ); PcieConfigDisableAllEngines (PciePortEngine, Wrapper); } } if (PcieLibIsDdiWrapper (Wrapper)) { Status = PcieEnginesToWrapper (PcieDdiEngine, ComplexDescriptor, Wrapper); AGESA_STATUS_UPDATE (Status, AgesaStatus); if (Status == AGESA_ERROR) { // If we can not map topology on wrapper we can not enable any engines. PutEventLog ( AGESA_ERROR, GNB_EVENT_INVALID_DDI_TOPOLOGY_CONFIGURATION, Wrapper->WrapId, Wrapper->StartPhyLane, Wrapper->EndPhyLane, 0, GnbLibGetHeader (Pcie) ); PcieConfigDisableAllEngines (PcieDdiEngine, Wrapper); } } // Copy engine data PcieMapInitializeEngineData (ComplexDescriptor, Wrapper, Pcie); EngineList = PcieConfigGetChildEngine (Wrapper); // Verify if we oversubscribe lanes and PHY link width WrapperPhyLaneBitMap = 0; while (EngineList != NULL) { UINT32 EnginePhyLaneBitMap; if (PcieLibIsEngineAllocated (EngineList)) { EnginePhyLaneBitMap = PcieConfigGetEnginePhyLaneBitMap (EngineList); if ((WrapperPhyLaneBitMap & EnginePhyLaneBitMap) != 0) { IDS_HDT_CONSOLE (PCIE_MISC, " ERROR! Lanes double subscribe lanes [Engine Lanes %d..%d]\n", EngineList->EngineData.StartLane, EngineList->EngineData.EndLane ); PutEventLog ( AGESA_ERROR, GNB_EVENT_INVALID_LANES_CONFIGURATION, EngineList->EngineData.StartLane, EngineList->EngineData.EndLane, 0, 0, GnbLibGetHeader (Pcie) ); PcieConfigDisableEngine (EngineList); Status = AGESA_ERROR; AGESA_STATUS_UPDATE (Status, AgesaStatus); } else { WrapperPhyLaneBitMap |= EnginePhyLaneBitMap; } } EngineList = PcieLibGetNextDescriptor (EngineList); } IDS_HDT_CONSOLE (GNB_TRACE, "PcieMapTopologyOnWrapper Exit [%d]\n", AgesaStatus); return AgesaStatus; }