/*----------------------------------------------------------------------------------------*/
AGESA_STATUS
PcieCommClkCfgInterface (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS AgesaStatus;
PCIe_PLATFORM_CONFIG *Pcie;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieCommClkCfgInterface Enter\n");
AgesaStatus = PcieLocateConfigurationData (StdHeader, &Pcie);
if (AgesaStatus == AGESA_SUCCESS) {
PcieConfigRunProcForAllEngines (
DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
PcieCommClkCfgPortInitCallback,
NULL,
Pcie
);
}
IDS_HDT_CONSOLE (GNB_TRACE, "PcieCommClkCfgInterface Exit [0x%x]\n", AgesaStatus);
return AgesaStatus;
}
/**
* PCIe Post Init
*
*
*
* @param[in] StdHeader Standard configuration header
* @retval AGESA_STATUS
*/
AGESA_STATUS
PciePostInterfaceML (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS AgesaStatus;
AGESA_STATUS Status;
PCIe_PLATFORM_CONFIG *Pcie;
GNB_BUILD_OPTIONS_ML *GnbBuildOptionData;
IDS_HDT_CONSOLE (GNB_TRACE, "PciePostInterfaceML Enter\n");
AgesaStatus = AGESA_SUCCESS;
Status = PcieLocateConfigurationData (StdHeader, &Pcie);
IDS_OPTION_HOOK (IDS_BEFORE_GEN2_INIT, Pcie, StdHeader);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
GnbBuildOptionData = GnbLocateHeapBuffer (AMD_GNB_BUILD_OPTIONS_HANDLE, StdHeader);
ASSERT (GnbBuildOptionData != NULL);
if ((Status == AGESA_SUCCESS) &&
(GnbBuildOptionData->CfgUseSMUServices == TRUE)) {
PciePortsVisibilityControlV5 (UnhidePorts, Pcie);
Status = PciePostInitML (Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
ASSERT (Status == AGESA_SUCCESS);
Status = PciePostPortInitML (Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
ASSERT (Status == AGESA_SUCCESS);
Status = PcieTrainingV2 (Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
ASSERT (Status == AGESA_SUCCESS);
IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_PCIE_PHY_CONFIG, Pcie, StdHeader);
GnbSmuBiosTableGetPcieInfoML (StdHeader, Pcie);
PciePortsVisibilityControlV5 (HidePorts, Pcie);
}
IDS_HDT_CONSOLE (GNB_TRACE, "PciePostInterfaceML Exit [0x%x]\n", AgesaStatus);
return AgesaStatus;
}
AGESA_STATUS
GnbNbIoapicInterface (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AMD_MID_PARAMS *MidParamsPtr;
AGESA_STATUS Status;
PCIe_PLATFORM_CONFIG *Pcie;
UINT64 GnbNbIoapicAddress;
IDS_HDT_CONSOLE (GNB_TRACE, "GnbNbIoapicInterface Enter\n");
Status = PcieLocateConfigurationData (StdHeader, &Pcie);
if (Status == AGESA_SUCCESS) {
MidParamsPtr = (AMD_MID_PARAMS *) StdHeader;
GnbNbIoapicAddress = MidParamsPtr->GnbMidConfiguration.GnbIoapicAddress;
// For each ENGINE, configure the group, swizzle, and pin per APIC_DEVICE_INFO
PcieConfigRunProcForAllEngines (DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, IoapicInitCallbackV5, NULL, Pcie);
// For each GNB, configure the IOAPIC Enable, ID Size, and SB Feature Enable
Status = PcieConfigRunProcForAllDescriptors (DESCRIPTOR_SILICON, 0, DESCRIPTOR_TERMINATE_TOPOLOGY, IoapicEnableCallbackV5, &GnbNbIoapicAddress, Pcie);
}
IDS_HDT_CONSOLE (GNB_TRACE, "GnbNbIoapicInterface Exit\n");
return Status;
}
STATIC AGESA_STATUS
GnbIommuMidInit (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS Status;
PCIe_PLATFORM_CONFIG *Pcie;
IDS_HDT_CONSOLE (GNB_TRACE, "GnbIommuMidInit Enter\n");
Status = PcieLocateConfigurationData (StdHeader, &Pcie);
if (Status == AGESA_SUCCESS) {
PcieConfigRunProcForAllEngines (
DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
GnbIommuMidInitOnPortCallback,
NULL,
Pcie
);
}
GnbIommuMidInitCheckGfxPciePorts (Pcie);
IDS_HDT_CONSOLE (GNB_TRACE, "GnbIommuMidInit Exit [0x%x]\n", Status);
return Status;
}
AGESA_STATUS
PcieAlibBuildAcpiTable (
IN AMD_CONFIG_PARAMS *StdHeader,
OUT VOID **AlibSsdtPtr
)
{
AGESA_STATUS Status;
UINT32 AmlObjName;
PCIe_PLATFORM_CONFIG *Pcie;
PP_FUSE_ARRAY *PpFuseArray;
VOID *AlibSsdtBuffer;
VOID *AmlObjPtr;
UINT8 SclkVidArray[4];
UINT8 BootUpVid;
UINT8 BootUpVidIndex;
UINT8 Gen1VidIndex;
UINTN Index;
UINTN AlibSsdtlength;
Status = AGESA_SUCCESS;
AlibSsdtlength = ((ACPI_TABLE_HEADER*) &AlibSsdt[0])->TableLength;
if (*AlibSsdtPtr == NULL) {
AlibSsdtBuffer = GnbAllocateHeapBuffer (
AMD_ACPI_ALIB_BUFFER_HANDLE,
AlibSsdtlength,
StdHeader
);
ASSERT (AlibSsdtBuffer != NULL);
if (AlibSsdtBuffer == NULL) {
return AGESA_ERROR;
}
*AlibSsdtPtr = AlibSsdtBuffer;
} else {
AlibSsdtBuffer = *AlibSsdtPtr;
}
// Copy template to buffer
LibAmdMemCopy (AlibSsdtBuffer, &AlibSsdt[0], AlibSsdtlength, StdHeader);
// Set PCI MMIO configuration
// AmlObjName = '10DA';
AmlObjName = Int32FromChar ('A', 'D', '0', '1');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
if (AmlObjPtr != NULL) {
UINT64 MsrReg;
LibAmdMsrRead (MSR_MMIO_Cfg_Base, &MsrReg, StdHeader);
if ((MsrReg & BIT0) != 0 && (MsrReg & 0xFFFFFFFF00000000) == 0) {
*(UINT32*)((UINT8*)AmlObjPtr + 5) = (UINT32)(MsrReg & 0xFFFFF00000);
} else {
Status = AGESA_ERROR;
}
} else {
Status = AGESA_ERROR;
}
// Set voltage configuration
PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader);
if (PpFuseArray != NULL) {
// AmlObjName = '30DA';
AmlObjName = Int32FromChar ('A', 'D', '0', '3');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {
*(UINT8*)((UINT8*)AmlObjPtr + 5) = PpFuseArray->PcieGen2Vid;
} else {
Status = AGESA_ERROR;
}
} else {
Status = AGESA_ERROR;
}
GnbLibPciRead (
MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3x15C_ADDRESS),
AccessWidth32,
&SclkVidArray[0],
StdHeader
);
Gen1VidIndex = 0;
BootUpVidIndex = 0;
BootUpVid = 0xff;
for (Index = 0; Index < 4; Index++) {
if (SclkVidArray[Index] > SclkVidArray[Gen1VidIndex]) {
Gen1VidIndex = (UINT8) Index;
}
if (SclkVidArray[Index] != 0 && SclkVidArray[Index] < BootUpVid) {
BootUpVid = SclkVidArray[Index];
BootUpVidIndex = (UINT8) Index;
}
}
// AmlObjName = '40DA';
AmlObjName = Int32FromChar ('A', 'D', '0', '4');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {
*(UINT8*)((UINT8*)AmlObjPtr + 5) = Gen1VidIndex;
} else {
Status = AGESA_ERROR;
}
// AmlObjName = '50DA';
AmlObjName = Int32FromChar ('A', 'D', '0', '5');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {
*(UINT8*)((UINT8*)AmlObjPtr + 5) = BootUpVidIndex;
} else {
Status = AGESA_ERROR;
}
// Set PCIe configuration
if (PcieLocateConfigurationData (StdHeader, &Pcie) == AGESA_SUCCESS) {
// AmlObjName = '20DA';
AmlObjName = Int32FromChar ('A', 'D', '0', '2');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {
*(UINT8*)((UINT8*)AmlObjPtr + 5) = Pcie->PsppPolicy;
} else {
Status = AGESA_ERROR;
}
// AmlObjName = '60DA';
AmlObjName = Int32FromChar ('A', 'D', '0', '6');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {
PcieConfigRunProcForAllEngines (
DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
PcieAlibSetPortMaxSpeedCallback,
(UINT8*)((UINT8*)AmlObjPtr + 7),
Pcie
);
} else {
Status = AGESA_ERROR;
}
// AmlObjName = '80DA';
AmlObjName = Int32FromChar ('A', 'D', '0', '8');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {
PcieConfigRunProcForAllEngines (
DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
PcieAlibSetPortOverrideSpeedCallback,
(UINT8*)((UINT8*)AmlObjPtr + 7),
Pcie
);
} else {
Status = AGESA_ERROR;
}
// AmlObjName = '70DA';
AmlObjName = Int32FromChar ('A', 'D', '0', '7');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {
PcieConfigRunProcForAllEngines (
DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
PcieAlibSetPortInfoCallback,
(UINT8*)((UINT8*)AmlObjPtr + 4),
Pcie
);
} else {
Status = AGESA_ERROR;
}
} else {
ASSERT (FALSE);
Status = AGESA_ERROR;
}
if (Status == AGESA_SUCCESS) {
Status = PcieFmAlibBuildAcpiTable (AlibSsdtBuffer, StdHeader);
}
if (Status != AGESA_SUCCESS) {
//Shrink table length to size of the header
((ACPI_TABLE_HEADER*) AlibSsdtBuffer)->TableLength = sizeof (ACPI_TABLE_HEADER);
}
ChecksumAcpiTable ((ACPI_TABLE_HEADER*) AlibSsdtBuffer, StdHeader);
return Status;
}
/**
* Build integrated info table
*
*
*
* @param[in] Gfx Gfx configuration info
* @param[in] SystemInfoTableV3 ATOM_FUSION_SYSTEM_INFO_V3 pointer
* @param[in] PpF1Array
* @retval AGESA_STATUS
*/
AGESA_STATUS
GfxIntInfoTableInitV3 (
IN GFX_PLATFORM_CONFIG *Gfx,
IN ATOM_FUSION_SYSTEM_INFO_V3 *SystemInfoTableV3,
IN PP_F1_ARRAY_V2 *PpF1Array
)
{
AGESA_STATUS Status;
AGESA_STATUS AgesaStatus;
PCIe_PLATFORM_CONFIG *Pcie;
ATOM_PPLIB_POWERPLAYTABLE4 *PpTable;
UINT8 Channel;
AgesaStatus = AGESA_SUCCESS;
IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableInitV3 Enter\n");
if (PpF1Array != NULL) {
Channel = 0;
if ((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_ON_DCT1) != 0) {
Channel = 1;
} else if ((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_ON_DCT2) != 0) {
Channel = 2;
} else if ((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_ON_DCT3) != 0) {
Channel = 3;
}
SystemInfoTableV3->sIntegratedSysInfo.sHeader.usStructureSize = sizeof (ATOM_INTEGRATED_SYSTEM_INFO_V1_8);
ASSERT (SystemInfoTableV3->sIntegratedSysInfo.sHeader.usStructureSize == 512);
SystemInfoTableV3->sIntegratedSysInfo.sHeader.ucTableFormatRevision = 1;
SystemInfoTableV3->sIntegratedSysInfo.sHeader.ucTableContentRevision = 8;
SystemInfoTableV3->sIntegratedSysInfo.ulBootUpEngineClock = 200 * 100; //Set default engine clock to 200MhZ
SystemInfoTableV3->sIntegratedSysInfo.field2 = (PpF1Array->PP_FUSE_ARRAY_V2_fld21 + 0x10) * 10000;
SystemInfoTableV3->sIntegratedSysInfo.ulBootUpUMAClock = Gfx->UmaInfo.MemClock * 100;
SystemInfoTableV3->sIntegratedSysInfo.usRequestedPWMFreqInHz = Gfx->LcdBackLightControl;
SystemInfoTableV3->sIntegratedSysInfo.ucUMAChannelNumber = ((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_INTERLEAVE) == 0) ? 1 : 2;
SystemInfoTableV3->sIntegratedSysInfo.ucMemoryType = Gfx->UmaInfo.MemType;
SystemInfoTableV3->sIntegratedSysInfo.usBootUpNBVoltage = GnbLocateHighestVidIndexV5 (GnbLibGetHeader (Gfx));
SystemInfoTableV3->sIntegratedSysInfo.usPanelRefreshRateRange = Gfx->DynamicRefreshRate;
SystemInfoTableV3->sIntegratedSysInfo.usLvdsSSPercentage = Gfx->LvdsSpreadSpectrum;
//Locate PCIe configuration data to get definitions of display connectors
SystemInfoTableV3->sIntegratedSysInfo.sExtDispConnInfo.sHeader.usStructureSize = sizeof (ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO);
SystemInfoTableV3->sIntegratedSysInfo.sExtDispConnInfo.sHeader.ucTableFormatRevision = 1;
SystemInfoTableV3->sIntegratedSysInfo.sExtDispConnInfo.sHeader.ucTableContentRevision = 1;
SystemInfoTableV3->sIntegratedSysInfo.sExtDispConnInfo.uc3DStereoPinId = Gfx->Gnb3dStereoPinIndex;
SystemInfoTableV3->sIntegratedSysInfo.sExtDispConnInfo.ucRemoteDisplayConfig = Gfx->GnbRemoteDisplaySupport;
SystemInfoTableV3->sIntegratedSysInfo.sExtDispConnInfo.ucFixDPVoltageSwing = (UINT8) Gfx->DpFixedVoltSwingType;
SystemInfoTableV3->sIntegratedSysInfo.usExtDispConnInfoOffset = offsetof (ATOM_INTEGRATED_SYSTEM_INFO_V1_8, sExtDispConnInfo);
SystemInfoTableV3->sIntegratedSysInfo.usPCIEClkSSPercentage = Gfx->PcieRefClkSpreadSpectrum;
SystemInfoTableV3->sIntegratedSysInfo.ucLvdsMisc = Gfx->LvdsMiscControl.Value;
IDS_HDT_CONSOLE (GNB_TRACE, "Lvds Misc control : %x\n", Gfx->LvdsMiscControl.Value);
if (Gfx->LvdsMiscControl.Field.LvdsVoltOverwriteEn) {
SystemInfoTableV3->sIntegratedSysInfo.ucLVDSVoltAdjust = Gfx->LVDSVoltAdjust;
IDS_HDT_CONSOLE (GNB_TRACE, "LVDSVoltAdjust : %x\n", Gfx->LVDSVoltAdjust);
}
SystemInfoTableV3->sIntegratedSysInfo.ulVBIOSMisc = Gfx->DisplayMiscControl.Value;
IDS_HDT_CONSOLE (GNB_TRACE, "Display Misc control : %x\n", Gfx->DisplayMiscControl.Value);
// LVDS
SystemInfoTableV3->sIntegratedSysInfo.ucLVDSPwrOnSeqDIGONtoDE_in4Ms = Gfx->LvdsPowerOnSeqDigonToDe;
SystemInfoTableV3->sIntegratedSysInfo.ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms = Gfx->LvdsPowerOnSeqDeToVaryBl;
SystemInfoTableV3->sIntegratedSysInfo.ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms = Gfx->LvdsPowerOnSeqVaryBlToDe;
SystemInfoTableV3->sIntegratedSysInfo.ucLVDSPwrOffSeqDEtoDIGON_in4Ms = Gfx->LvdsPowerOnSeqDeToDigon;
SystemInfoTableV3->sIntegratedSysInfo.ucLVDSOffToOnDelay_in4Ms = Gfx->LvdsPowerOnSeqOnToOffDelay;
SystemInfoTableV3->sIntegratedSysInfo.ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms = Gfx->LvdsPowerOnSeqVaryBlToBlon;
SystemInfoTableV3->sIntegratedSysInfo.ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms = Gfx->LvdsPowerOnSeqBlonToVaryBl;
SystemInfoTableV3->sIntegratedSysInfo.ulLCDBitDepthControlVal = Gfx->LcdBitDepthControlValue;
SystemInfoTableV3->sIntegratedSysInfo.usMaxLVDSPclkFreqInSingleLink = Gfx->LvdsMaxPixelClockFreq;
SystemInfoTableV3->sIntegratedSysInfo.ucMinAllowedBL_Level = Gfx->MinAllowedBLLevel;
Status = PcieLocateConfigurationData (GnbLibGetHeader (Gfx), &Pcie);
ASSERT (Status == AGESA_SUCCESS);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
if (Status == AGESA_SUCCESS) {
Status = GfxIntegratedEnumerateAllConnectors (
&SystemInfoTableV3->sIntegratedSysInfo.sExtDispConnInfo.sPath[0],
Pcie,
Gfx
);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
}
SystemInfoTableV3->sIntegratedSysInfo.sExtDispConnInfo.uceDPToLVDSRxId = eDP_TO_LVDS_RX_DISABLE;
PcieConfigRunProcForAllEngines (
DESCRIPTOR_ALLOCATED | DESCRIPTOR_VIRTUAL | DESCRIPTOR_DDI_ENGINE,
GfxIntegrateducEDPToLVDSRxIdCallback,
&SystemInfoTableV3->sIntegratedSysInfo.sExtDispConnInfo.uceDPToLVDSRxId,
Pcie
);
// Build PP table
PpTable = (ATOM_PPLIB_POWERPLAYTABLE4*) &SystemInfoTableV3->ulPowerplayTable;
// Build PP table
///@todo
//Status = GfxPowerPlayBuildTable (PpTable, Gfx);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
// Assign usFormatID to 0x000B to represent V3
///@todo
PpTable->usFormatID = 0xB;
// Build Display clock info
GfxIntegratedInfoTable289_fun (PpF1Array, &SystemInfoTableV3->sIntegratedSysInfo, Gfx);
GfxIntegratedInfoTable318_fun (PpF1Array, &SystemInfoTableV3->sIntegratedSysInfo, Gfx);
///@todo review if these parameters needed
// Fill in Nb P-state MemclkFreq Data
GfxFillNbPstateMemclkFreqV3 (&SystemInfoTableV3->sIntegratedSysInfo, PpF1Array, Gfx);
// Fill in HTC Data
if (PpF1Array->HtcEn == 1) {
SystemInfoTableV3->sIntegratedSysInfo.ucHtcTmpLmt = (UCHAR) (PpF1Array->HtcTmpLmt / 2 + 52);
SystemInfoTableV3->sIntegratedSysInfo.ATOM_INTEGRATED_SYSTEM_INFO_V1_8_fld11 = (UCHAR) (PpF1Array->PP_FUSE_ARRAY_V2_fld20 / 2);
} else {
SystemInfoTableV3->sIntegratedSysInfo.ucHtcTmpLmt = 0;
SystemInfoTableV3->sIntegratedSysInfo.ATOM_INTEGRATED_SYSTEM_INFO_V1_8_fld11 = 0;
}
// Fill in NB P states VID & NCLK info
GfxFillNbPStateVidV3 (PpF1Array, &SystemInfoTableV3->sIntegratedSysInfo, Gfx);
// Family specific data update - store default values to be updated by family specific code
//GfxFmIntegratedInfoTableInit (&SystemInfoV1Table.sIntegratedSysInfo, Gfx);
SystemInfoTableV3->sIntegratedSysInfo.ulDDR_DLL_PowerUpTime = 4940;
SystemInfoTableV3->sIntegratedSysInfo.ulDDR_PLL_PowerUpTime = 2000;
if (PpF1Array->MemPhyPllPdMode[Channel] != 0) {
SystemInfoTableV3->sIntegratedSysInfo.ulSystemConfig |= BIT2;
}
if (PpF1Array->DisDllShutdownSR[Channel] == 0) {
SystemInfoTableV3->sIntegratedSysInfo.ulSystemConfig |= BIT1;
}
if (GnbBuildOptions.CfgPciePowerGatingFlags != (PCIE_POWERGATING_SKIP_CORE | PCIE_POWERGATING_SKIP_PHY)) {
SystemInfoTableV3->sIntegratedSysInfo.ulSystemConfig |= BIT0;
}
SystemInfoTableV3->sIntegratedSysInfo.ulGPUCapInfo = GPUCAPINFO_TMDS_HDMI_USE_CASCADE_PLL_MODE | GPUCAPINFO_DP_USE_SINGLE_PLL_MODE;
IDS_HDT_CONSOLE (GNB_TRACE, "ulSystemConfig : %x\n", SystemInfoTableV3->sIntegratedSysInfo.ulSystemConfig);
} else {
Status = AGESA_ERROR;
AGESA_STATUS_UPDATE (Status, AgesaStatus);
}
IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableInitV3 Exit [0x%x]\n", Status);
return Status;
}
/**
* Build integrated info table
*
*
*
* @param[in] Gfx Gfx configuration info
* @retval AGESA_STATUS
*/
AGESA_STATUS
STATIC
GfxIntInfoTableInitTN (
IN GFX_PLATFORM_CONFIG *Gfx
)
{
AGESA_STATUS Status;
AGESA_STATUS AgesaStatus;
ATOM_FUSION_SYSTEM_INFO_V2 SystemInfoTableV2;
PP_FUSE_ARRAY *PpFuseArray;
PCIe_PLATFORM_CONFIG *Pcie;
ATOM_PPLIB_POWERPLAYTABLE3 *PpTable;
UINT8 Channel;
AgesaStatus = AGESA_SUCCESS;
IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableInitTN Enter\n");
LibAmdMemFill (&SystemInfoTableV2, 0x00, sizeof (ATOM_FUSION_SYSTEM_INFO_V2), GnbLibGetHeader (Gfx));
SystemInfoTableV2.sIntegratedSysInfo.sHeader.usStructureSize = sizeof (ATOM_INTEGRATED_SYSTEM_INFO_V1_7);
ASSERT (SystemInfoTableV2.sIntegratedSysInfo.sHeader.usStructureSize == 512);
SystemInfoTableV2.sIntegratedSysInfo.sHeader.ucTableFormatRevision = 1;
SystemInfoTableV2.sIntegratedSysInfo.sHeader.ucTableContentRevision = 7;
SystemInfoTableV2.sIntegratedSysInfo.ulDentistVCOFreq = GfxLibGetSytemPllCofTN (GnbLibGetHeader (Gfx)) * 100;
SystemInfoTableV2.sIntegratedSysInfo.ulBootUpUMAClock = Gfx->UmaInfo.MemClock * 100;
SystemInfoTableV2.sIntegratedSysInfo.usRequestedPWMFreqInHz = Gfx->LcdBackLightControl;
SystemInfoTableV2.sIntegratedSysInfo.ucUMAChannelNumber = ((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_INTERLEAVE) == 0) ? 1 : 2;
SystemInfoTableV2.sIntegratedSysInfo.ucMemoryType = 3; //DDR3
SystemInfoTableV2.sIntegratedSysInfo.ulBootUpEngineClock = 200 * 100; //Set default engine clock to 200MhZ
SystemInfoTableV2.sIntegratedSysInfo.usBootUpNBVoltage = GnbLocateHighestVidIndex (GnbLibGetHeader (Gfx));
SystemInfoTableV2.sIntegratedSysInfo.ulMinEngineClock = 200 * 100;
SystemInfoTableV2.sIntegratedSysInfo.usPanelRefreshRateRange = Gfx->DynamicRefreshRate;
SystemInfoTableV2.sIntegratedSysInfo.usLvdsSSPercentage = Gfx->LvdsSpreadSpectrum;
//Locate PCIe configuration data to get definitions of display connectors
SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.sHeader.usStructureSize = sizeof (ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO);
SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.sHeader.ucTableFormatRevision = 1;
SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.sHeader.ucTableContentRevision = 1;
SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.uc3DStereoPinId = Gfx->Gnb3dStereoPinIndex;
SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.ucRemoteDisplayConfig = Gfx->GnbRemoteDisplaySupport;
SystemInfoTableV2.sIntegratedSysInfo.usExtDispConnInfoOffset = offsetof (ATOM_INTEGRATED_SYSTEM_INFO_V1_7, sExtDispConnInfo);
SystemInfoTableV2.sIntegratedSysInfo.ulSB_MMIO_Base_Addr = SbGetSbMmioBaseAddress (GnbLibGetHeader (Gfx));
SystemInfoTableV2.sIntegratedSysInfo.usPCIEClkSSPercentage = Gfx->PcieRefClkSpreadSpectrum;
SystemInfoTableV2.sIntegratedSysInfo.ucLvdsMisc = Gfx->LvdsMiscControl.Value;
IDS_HDT_CONSOLE (GNB_TRACE, "Lvds Misc control : %x\n", Gfx->LvdsMiscControl.Value);
if (Gfx->LvdsMiscControl.Field.TravisLvdsVoltOverwriteEn) {
SystemInfoTableV2.sIntegratedSysInfo.gnbgfxline429 = Gfx->gfxplmcfg0 ;
IDS_HDT_CONSOLE (GNB_TRACE, "TravisLVDSVoltAdjust : %x\n", Gfx->gfxplmcfg0 );
}
SystemInfoTableV2.sIntegratedSysInfo.ulOtherDisplayMisc = Gfx->DisplayMiscControl.Value;
IDS_HDT_CONSOLE (GNB_TRACE, "Display Misc control : %x\n", Gfx->DisplayMiscControl.Value);
// LVDS
SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOnSeqDIGONtoDE_in4Ms = Gfx->LvdsPowerOnSeqDigonToDe;
SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms = Gfx->LvdsPowerOnSeqDeToVaryBl;
SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms = Gfx->LvdsPowerOnSeqVaryBlToDe;
SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOffSeqDEtoDIGON_in4Ms = Gfx->LvdsPowerOnSeqDeToDigon;
SystemInfoTableV2.sIntegratedSysInfo.ucLVDSOffToOnDelay_in4Ms = Gfx->LvdsPowerOnSeqOnToOffDelay;
SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms = Gfx->LvdsPowerOnSeqVaryBlToBlon;
SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms = Gfx->LvdsPowerOnSeqBlonToVaryBl;
SystemInfoTableV2.sIntegratedSysInfo.ulLCDBitDepthControlVal = Gfx->LcdBitDepthControlValue;
SystemInfoTableV2.sIntegratedSysInfo.usMaxLVDSPclkFreqInSingleLink = Gfx->LvdsMaxPixelClockFreq;
Status = PcieLocateConfigurationData (GnbLibGetHeader (Gfx), &Pcie);
ASSERT (Status == AGESA_SUCCESS);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
if (Status == AGESA_SUCCESS) {
Status = GfxIntegratedEnumerateAllConnectors (
&SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.sPath[0],
Pcie,
Gfx
);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
}
SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.uceDPToLVDSRxId = eDP_TO_LVDS_RX_DISABLE;
PcieConfigRunProcForAllEngines (
DESCRIPTOR_ALLOCATED | DESCRIPTOR_VIRTUAL | DESCRIPTOR_DDI_ENGINE,
GfxIntegrateducEDPToLVDSRxIdCallback,
&SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.uceDPToLVDSRxId,
Pcie
);
// Build PP table
PpTable = (ATOM_PPLIB_POWERPLAYTABLE3*) &SystemInfoTableV2.ulPowerplayTable;
// Build PP table
Status = GfxPowerPlayBuildTable (PpTable, Gfx);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
// Assign usFormatID to 0x000B to represent Trinity
PpTable->usFormatID = 0xB;
// Build info from fuses
PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, GnbLibGetHeader (Gfx));
ASSERT (PpFuseArray != NULL);
if (PpFuseArray != NULL) {
// Build Display clock info
GfxIntInfoTableInitDispclkTable (PpFuseArray, &SystemInfoTableV2.sIntegratedSysInfo, Gfx);
// Build Sclk info table
GfxIntInfoTableInitSclkTable (PpFuseArray, &SystemInfoTableV2.sIntegratedSysInfo, Gfx);
} else {
Status = AGESA_ERROR;
AGESA_STATUS_UPDATE (Status, AgesaStatus);
}
//@todo review if thouse parameters needed
// Fill in Nb P-state MemclkFreq Data
GfxFillNbPstateMemclkFreqTN (&SystemInfoTableV2.sIntegratedSysInfo, Gfx);
// Fill in HTC Data
GfxFillHtcDataTN (&SystemInfoTableV2.sIntegratedSysInfo, Gfx);
// Fill in NB P states VID
GfxFillNbPStateVidTN (&SystemInfoTableV2.sIntegratedSysInfo, Gfx);
// Fill in NCLK info
//GfxFillNclkInfo (&SystemInfoV1Table.sIntegratedSysInfo, Gfx);
// Fill in the M3 arbitration control tables
//GfxFillM3ArbritrationControl (&SystemInfoV1Table.sIntegratedSysInfo, Gfx);
// Family specific data update
// Determine ulGMCRestoreResetTime
Status = GfxCalculateRestoreResetTimeTN (&SystemInfoTableV2.sIntegratedSysInfo, Gfx, PpFuseArray);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
//GfxFmIntegratedInfoTableInit (&SystemInfoV1Table.sIntegratedSysInfo, Gfx);
SystemInfoTableV2.sIntegratedSysInfo.ulDDR_DLL_PowerUpTime = 4940;
SystemInfoTableV2.sIntegratedSysInfo.ulDDR_PLL_PowerUpTime = 2000;
if ((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_ON_DCT0) != 0) {
Channel = 0;
} else {
Channel = 1;
}
if (GfxLibGetMemPhyPllPdModeTN (Channel, GnbLibGetHeader (Gfx)) != 0) {
SystemInfoTableV2.sIntegratedSysInfo.ulSystemConfig |= BIT2;
}
if (GfxLibGetDisDllShutdownSRTN (Channel, GnbLibGetHeader (Gfx)) == 0) {
SystemInfoTableV2.sIntegratedSysInfo.ulSystemConfig |= BIT1;
}
if (GnbBuildOptions.CfgPciePowerGatingFlags != (PCIE_POWERGATING_SKIP_CORE | PCIE_POWERGATING_SKIP_PHY)) {
SystemInfoTableV2.sIntegratedSysInfo.ulSystemConfig |= BIT0;
}
SystemInfoTableV2.sIntegratedSysInfo.ulGPUCapInfo = GPUCAPINFO_TMDS_HDMI_USE_CASCADE_PLL_MODE | GPUCAPINFO_DP_USE_SINGLE_PLL_MODE;
IDS_HDT_CONSOLE (GNB_TRACE, "ulSystemConfig : %x\n", SystemInfoTableV2.sIntegratedSysInfo.ulSystemConfig);
IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_INTEGRATED_TABLE_CONFIG, &SystemInfoTableV2.sIntegratedSysInfo, GnbLibGetHeader (Gfx));
//Copy integrated info table to Frame Buffer. (Do not use LibAmdMemCopy, routine not guaranteed access to above 4G memory in 32 bit mode.)
GfxIntInfoTabablePostToFb (&SystemInfoTableV2, Gfx);
IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableInit Exit [0x%x]\n", Status);
return Status;
}
AgesaStatus = AGESA_SUCCESS;
EarlyParamsPtr = (AMD_EARLY_PARAMS *) StdHeader;
/* FIXME: Intentionally discard qualifier const of
* GnbConfig.PcieComplexList here.
*/
PcieComplexList = PcieConfigProcessUserConfig (
(PCIe_COMPLEX_DESCRIPTOR *)EarlyParamsPtr->GnbConfig.PcieComplexList,
StdHeader);
GNB_DEBUG_CODE (
if (PcieComplexList != NULL) {
PcieUserConfigConfigDump (PcieComplexList);
}
);
Status = PcieLocateConfigurationData (StdHeader, &Pcie);
ASSERT (Status == AGESA_SUCCESS);
if (Status == AGESA_SUCCESS) {
Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetChild (DESCRIPTOR_COMPLEX, &Pcie->Header);
NumberOfComplexes = PcieInputParserGetNumberOfComplexes (PcieComplexList);
while (Complex != NULL) {
for (Index = 0; Index < NumberOfComplexes; Index++) {
ComplexDescriptor = PcieInputParserGetComplexDescriptor (PcieComplexList, Index);
if (ComplexDescriptor->SocketId == Complex->SocketId) {
Status = PcieMapTopologyOnComplex (ComplexDescriptor, Complex, Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
}
}
Complex = PcieLibGetNextDescriptor (Complex);
}
}
AGESA_STATUS
GnbCableSafeEntry (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS Status;
PCIe_PLATFORM_CONFIG *Pcie;
PCIe_ENGINE_CONFIG *DdiEngineList [MaxHdp];
UINT8 HdpIndex;
UINT8 CurrentIndex;
GNB_CABLE_SAFE_DATA CableSafeData;
BOOLEAN ForceCableSafeOff;
IDS_HDT_CONSOLE (GNB_TRACE, "GnbCableSafeEntry Enter\n");
Status = AGESA_SUCCESS;
ForceCableSafeOff = GnbBuildOptions.CfgForceCableSafeOff;
IDS_OPTION_HOOK (IDS_GNB_FORCE_CABLESAFE, &ForceCableSafeOff, StdHeader);
if (GnbCableSafeIsSupported (StdHeader)) {
if (PcieLocateConfigurationData (StdHeader, &Pcie) == AGESA_SUCCESS) {
for (HdpIndex = 0; HdpIndex < MaxHdp; HdpIndex++) {
DdiEngineList[HdpIndex] = NULL;
}
LibAmdMemFill (&CableSafeData, 0, sizeof (CableSafeData), StdHeader);
if (!ForceCableSafeOff) {
PcieConfigRunProcForAllEngines (
DESCRIPTOR_ALLOCATED | DESCRIPTOR_DDI_ENGINE,
GnbCableSafeGetConnectorInfoArrayCallback,
DdiEngineList,
Pcie
);
CurrentIndex = 0;
for (HdpIndex = 0; HdpIndex < MaxHdp; HdpIndex++) {
if (DdiEngineList [HdpIndex] != NULL) {
CableSafeData.Data[HdpIndexTranslationTable[CurrentIndex]] = HdpIndex + 1;
CableSafeData.Data[AuxIndexTranslationTable[CurrentIndex]] = AuxDataTranslationTable [(DdiEngineList [HdpIndex])->Type.Ddi.DdiData.AuxIndex];
IDS_HDT_CONSOLE (NB_MISC, " Index [%d] HDP 0x%02x AUX 0x%02x\n", CurrentIndex, HdpIndex, (DdiEngineList [HdpIndex])->Type.Ddi.DdiData.AuxIndex);
CurrentIndex++;
}
}
} else {
GMMx6124_STRUCT GMMx6124;
GMMx6124.Value = 0x3F;
NbSmuSrbmRegisterWrite (SMU_GMM_TO_FCR (GMMx6124_ADDRESS), &GMMx6124.Value, TRUE, GnbLibGetHeader (Pcie));
GnbLibPciRMW (
MAKE_SBDFO (0, 0, 0x18, 6, D18F6x80_ADDRESS),
AccessWidth32,
0xffffffff,
(7 << D18F6x80_CableSafeDisAux_3_1_OFFSET) | (7 << D18F6x80_CableSafeDisAux_6_4_OFFSET),
GnbLibGetHeader (Pcie)
);
}
CableSafeData.Config.Enable = 0x1;
CableSafeData.Config.DebounceFilter = 0;
CableSafeData.Config.SoftPeriod = 0x4;
CableSafeData.Config.Unit = 0x1;
CableSafeData.Config.Period = 0xf424;
NbSmuRcuRegisterWrite (
SMUx0B_x85D0_ADDRESS,
(UINT32*) &CableSafeData,
sizeof (CableSafeData) / sizeof (UINT32),
TRUE,
StdHeader
);
NbSmuServiceRequest (0x05, TRUE, StdHeader);
} else {
Status = AGESA_ERROR;
}
}
IDS_HDT_CONSOLE (GNB_TRACE, "GnbCableSafeEntry Exit [Status = 0x%04x]\n", Status);
return Status;
}
/**
* Build integrated info table
*
*
*
* @param[in] Gfx Gfx configuration info
* @retval AGESA_STATUS
*/
AGESA_STATUS
GfxIntegratedInfoTableInit (
IN GFX_PLATFORM_CONFIG *Gfx
)
{
AGESA_STATUS Status;
AGESA_STATUS AgesaStatus;
ATOM_FUSION_SYSTEM_INFO_V1 SystemInfoV1Table;
PP_FUSE_ARRAY *PpFuseArray;
PCIe_PLATFORM_CONFIG *Pcie;
UINT32 IntegratedInfoAddress;
ATOM_PPLIB_POWERPLAYTABLE3 *PpTable;
UINT8 Channel;
AgesaStatus = AGESA_SUCCESS;
IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableInit Enter\n");
LibAmdMemFill (&SystemInfoV1Table, 0x00, sizeof (ATOM_FUSION_SYSTEM_INFO_V1), GnbLibGetHeader (Gfx));
SystemInfoV1Table.sIntegratedSysInfo.sHeader.usStructureSize = sizeof (ATOM_INTEGRATED_SYSTEM_INFO_V6);
ASSERT (SystemInfoV1Table.sIntegratedSysInfo.sHeader.usStructureSize == 512);
SystemInfoV1Table.sIntegratedSysInfo.sHeader.ucTableFormatRevision = 1;
SystemInfoV1Table.sIntegratedSysInfo.sHeader.ucTableContentRevision = 6;
SystemInfoV1Table.sIntegratedSysInfo.ulDentistVCOFreq = GfxLibGetMainPllFreq (GnbLibGetHeader (Gfx)) * 100;
SystemInfoV1Table.sIntegratedSysInfo.ulBootUpUMAClock = Gfx->UmaInfo.MemClock * 100;
SystemInfoV1Table.sIntegratedSysInfo.usRequestedPWMFreqInHz = Gfx->LcdBackLightControl;
SystemInfoV1Table.sIntegratedSysInfo.ucUMAChannelNumber = ((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_INTERLEAVE) == 0) ? 1 : 2;
SystemInfoV1Table.sIntegratedSysInfo.ucMemoryType = 3; //DDR3
SystemInfoV1Table.sIntegratedSysInfo.ulBootUpEngineClock = 200 * 100; //Set default engine clock to 200MhZ
SystemInfoV1Table.sIntegratedSysInfo.usBootUpNBVoltage = GfxLibMaxVidIndex (GnbLibGetHeader (Gfx));
SystemInfoV1Table.sIntegratedSysInfo.ulMinEngineClock = GfxLibGetMinSclk (GnbLibGetHeader (Gfx));
SystemInfoV1Table.sIntegratedSysInfo.usPanelRefreshRateRange = Gfx->DynamicRefreshRate;
SystemInfoV1Table.sIntegratedSysInfo.usLvdsSSPercentage = Gfx->LvdsSpreadSpectrum;
SystemInfoV1Table.sIntegratedSysInfo.usLvdsSSpreadRateIn10Hz = Gfx->LvdsSpreadSpectrumRate;
SystemInfoV1Table.sIntegratedSysInfo.usPCIEClkSSPercentage = Gfx->PcieRefClkSpreadSpectrum;
// SystemInfoV1Table.sIntegratedSysInfo.ucLvdsMisc = Gfx->LvdsMiscControl.Value;
//Locate PCIe configuration data to get definitions of display connectors
SystemInfoV1Table.sIntegratedSysInfo.sExtDispConnInfo.sHeader.usStructureSize = sizeof (ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO);
SystemInfoV1Table.sIntegratedSysInfo.sExtDispConnInfo.sHeader.ucTableFormatRevision = 1;
SystemInfoV1Table.sIntegratedSysInfo.sExtDispConnInfo.sHeader.ucTableContentRevision = 1;
SystemInfoV1Table.sIntegratedSysInfo.sExtDispConnInfo.uc3DStereoPinId = Gfx->Gnb3dStereoPinIndex;
ASSERT ((Gfx->UmaInfo.UmaAttributes & (UMA_ATTRIBUTE_ON_DCT0 | UMA_ATTRIBUTE_ON_DCT1)) != 0);
if ((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_ON_DCT0) != 0) {
Channel = 0;
} else {
Channel = 1;
}
if (GfxLibGetCsrPhySrPllPdMode (Channel, GnbLibGetHeader (Gfx)) != 0) {
SystemInfoV1Table.sIntegratedSysInfo.ulSystemConfig |= BIT2;
}
if (GfxLibGetDisDllShutdownSR (Channel, GnbLibGetHeader (Gfx)) == 0) {
SystemInfoV1Table.sIntegratedSysInfo.ulSystemConfig |= BIT1;
}
Status = PcieLocateConfigurationData (GnbLibGetHeader (Gfx), &Pcie);
ASSERT (Status == AGESA_SUCCESS);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
if (Status == AGESA_SUCCESS) {
Status = GfxIntegratedEnumerateAllConnectors (
&SystemInfoV1Table.sIntegratedSysInfo.sExtDispConnInfo.sPath[0],
Pcie,
Gfx
);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
}
SystemInfoV1Table.sIntegratedSysInfo.usExtDispConnInfoOffset = offsetof (ATOM_INTEGRATED_SYSTEM_INFO_V6, sExtDispConnInfo);
// Build PP table
PpTable = (ATOM_PPLIB_POWERPLAYTABLE3*) &SystemInfoV1Table.ulPowerplayTable;
// Build PP table
Status = GfxPowerPlayBuildTable (PpTable, Gfx);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
// Build info from fuses
PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, GnbLibGetHeader (Gfx));
ASSERT (PpFuseArray != NULL);
if (PpFuseArray != NULL) {
// Build Display clock info
GfxIntegratedInfoInitDispclkTable (PpFuseArray, &SystemInfoV1Table.sIntegratedSysInfo, Gfx);
// Build Sclk info table
GfxIntegratedInfoInitSclkTable (PpFuseArray, &SystemInfoV1Table.sIntegratedSysInfo, Gfx);
} else {
Status = AGESA_ERROR;
AGESA_STATUS_UPDATE (Status, AgesaStatus);
}
// Fill in HTC Data
GfxFillHtcData (&SystemInfoV1Table.sIntegratedSysInfo, Gfx);
// Fill in NB P states VID
GfxFillNbPStateVid (&SystemInfoV1Table.sIntegratedSysInfo, Gfx);
// Fill in NCLK info
GfxFillNclkInfo (&SystemInfoV1Table.sIntegratedSysInfo, Gfx);
// Fill in the M3 arbitration control tables
GfxFillM3ArbritrationControl (&SystemInfoV1Table.sIntegratedSysInfo, Gfx);
// Fill South bridge MMIO Base address
GfxFillSbMmioBaseAddress (&SystemInfoV1Table.sIntegratedSysInfo, Gfx);
// Family specific data update
GfxFmIntegratedInfoTableInit (&SystemInfoV1Table.sIntegratedSysInfo, Gfx);
IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_INTEGRATED_TABLE_CONFIG, &SystemInfoV1Table.sIntegratedSysInfo, GnbLibGetHeader (Gfx));
//Copy integrated info table to Frame Buffer. (Do not use LibAmdMemCopy, routine not guaranteed access to above 4G memory in 32 bit mode.)
IntegratedInfoAddress = (UINT32) (Gfx->UmaInfo.UmaSize - sizeof (ATOM_FUSION_SYSTEM_INFO_V1));
GfxLibCopyMemToFb ((VOID *) (&SystemInfoV1Table), IntegratedInfoAddress, sizeof (ATOM_FUSION_SYSTEM_INFO_V1), Gfx);
IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableInit Exit [0x%x]\n", Status);
return Status;
}
STATIC AGESA_STATUS
GnbLclkDpmInitTN (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS Status;
PCIe_PLATFORM_CONFIG *Pcie;
PP_FUSE_ARRAY *PpFuseArray;
PCI_ADDR GnbPciAddress;
UINT32 Index;
UINT8 LclkDpmMode;
D0F0xBC_x1F200_STRUCT D0F0xBC_x1F200[NUM_DPM_STATES];
D0F0xBC_x1F208_STRUCT D0F0xBC_x1F208[NUM_DPM_STATES];
D0F0xBC_x1F210_STRUCT D0F0xBC_x1F210[NUM_DPM_STATES];
D0F0xBC_x1F300_STRUCT D0F0xBC_x1F300;
ex1003_STRUCT ex1003 [NUM_DPM_STATES];
DOUBLE PcieCacLut;
ex1072_STRUCT ex1072 ;
D0F0xBC_x1FE00_STRUCT D0F0xBC_x1FE00;
D0F0xBC_x1F30C_STRUCT D0F0xBC_x1F30C;
D18F3x64_STRUCT D18F3x64;
IDS_HDT_CONSOLE (GNB_TRACE, "GnbLclkDpmInitTN Enter\n");
Status = AGESA_SUCCESS;
LclkDpmMode = GnbBuildOptions.LclkDpmEn ? LclkDpmRcActivity : LclkDpmDisabled;
IDS_OPTION_HOOK (IDS_GNB_LCLK_DPM_EN, &LclkDpmMode, StdHeader);
if (LclkDpmMode == LclkDpmRcActivity) {
PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader);
if (PpFuseArray != NULL) {
Status = PcieLocateConfigurationData (StdHeader, &Pcie);
if (Status == AGESA_SUCCESS) {
GnbPciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0);
//Clear DPM_EN bit in LCLK_DPM_CNTL register
//Call BIOS service SMC_MSG_CONFIG_LCLK_DPM to disable LCLK DPM
GnbRegisterReadTN (D0F0xBC_x1F300_TYPE, D0F0xBC_x1F300_ADDRESS, &D0F0xBC_x1F300.Value, 0, StdHeader);
D0F0xBC_x1F300.Field.LclkDpmEn = 0x0;
GnbRegisterWriteTN (D0F0xBC_x1F300_TYPE, D0F0xBC_x1F300_ADDRESS, &D0F0xBC_x1F300.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader);
GnbSmuServiceRequestV4 (
GnbPciAddress,
SMC_MSG_CONFIG_LCLK_DPM,
GNB_REG_ACC_FLAG_S3SAVE,
StdHeader
);
//Initialize LCLK states
LibAmdMemFill (D0F0xBC_x1F200, 0x00, sizeof (D0F0xBC_x1F200), StdHeader);
LibAmdMemFill (D0F0xBC_x1F208, 0x00, sizeof (D0F0xBC_x1F208), StdHeader);
LibAmdMemFill (ex1003, 0x00, sizeof (D0F0xBC_x1F208), StdHeader);
D0F0xBC_x1F200[0].Field.LclkDivider = PpFuseArray->LclkDpmDid[0];
D0F0xBC_x1F200[0].Field.VID = PpFuseArray->SclkVid[PpFuseArray->LclkDpmVid[0]];
D0F0xBC_x1F200[0].Field.LowVoltageReqThreshold = 0xa;
D0F0xBC_x1F210[0].Field.ActivityThreshold = 0xf;
D0F0xBC_x1F200[5].Field.LclkDivider = PpFuseArray->LclkDpmDid[1];
D0F0xBC_x1F200[5].Field.VID = PpFuseArray->SclkVid[PpFuseArray->LclkDpmVid[1]];
D0F0xBC_x1F200[5].Field.LowVoltageReqThreshold = 0xa;
D0F0xBC_x1F210[5].Field.ActivityThreshold = 0x32;
D0F0xBC_x1F200[5].Field.StateValid = 0x1;
D0F0xBC_x1F200[6].Field.LclkDivider = PpFuseArray->LclkDpmDid[2];
D0F0xBC_x1F200[6].Field.VID = PpFuseArray->SclkVid[PpFuseArray->LclkDpmVid[2]];
D0F0xBC_x1F200[6].Field.LowVoltageReqThreshold = 0xa;
D0F0xBC_x1F210[6].Field.ActivityThreshold = 0x32;
D0F0xBC_x1F200[6].Field.StateValid = 0x1;
GnbRegisterReadTN (TYPE_D0F0xBC , 0x1f920 , &ex1072.Value, 0, StdHeader);
PcieCacLut = 0.0000057028 * (1 << ex1072.Field.ex1072_0 );
IDS_HDT_CONSOLE (GNB_TRACE, "LCLK DPM1 10khz %x (%d)\n", GfxFmCalculateClock (PpFuseArray->LclkDpmDid[1], StdHeader), GfxFmCalculateClock (PpFuseArray->LclkDpmDid[1], StdHeader));
D0F0xBC_x1FE00.Field.Data = (UINT32) GnbFpLibDoubleToInt32 (PcieCacLut * GfxFmCalculateClock (PpFuseArray->LclkDpmDid[1], StdHeader));
GnbRegisterWriteTN (D0F0xBC_x1FE00_TYPE, D0F0xBC_x1FE00_ADDRESS, &D0F0xBC_x1FE00.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader);
PcieCacLut = 0.00000540239329 * (1 << ex1072.Field.ex1072_0 );
ex1003[6].Field.ex1003_0 = (UINT32) GnbFpLibDoubleToInt32 (PcieCacLut * GfxFmCalculateClock (PpFuseArray->LclkDpmDid[2], StdHeader));
IDS_HDT_CONSOLE (GNB_TRACE, "LCLK DPM2 10khz %x (%d)\n", GfxFmCalculateClock (PpFuseArray->LclkDpmDid[2], StdHeader), GfxFmCalculateClock (PpFuseArray->LclkDpmDid[2], StdHeader));
for (Index = 0; Index < NUM_DPM_STATES; ++Index) {
GnbRegisterWriteTN (
D0F0xBC_x1F200_TYPE,
D0F0xBC_x1F200_ADDRESS + Index * 0x20,
&D0F0xBC_x1F200[Index].Value,
GNB_REG_ACC_FLAG_S3SAVE,
StdHeader
);
GnbRegisterWriteTN (
D0F0xBC_x1F208_TYPE,
D0F0xBC_x1F208_ADDRESS + Index * 0x20,
&D0F0xBC_x1F208[Index].Value,
GNB_REG_ACC_FLAG_S3SAVE,
StdHeader
);
GnbRegisterWriteTN (
D0F0xBC_x1F210_TYPE,
D0F0xBC_x1F210_ADDRESS + Index * 0x20,
&D0F0xBC_x1F210[Index].Value,
GNB_REG_ACC_FLAG_S3SAVE,
StdHeader
);
GnbRegisterWriteTN (
TYPE_D0F0xBC ,
0x1f940 + Index * 4,
&ex1003[Index].Value,
GNB_REG_ACC_FLAG_S3SAVE,
StdHeader
);
}
//Enable LCLK DPM Voltage Scaling
GnbRegisterReadTN (D0F0xBC_x1F300_TYPE, D0F0xBC_x1F300_ADDRESS, &D0F0xBC_x1F300.Value, 0, StdHeader);
D0F0xBC_x1F300.Field.VoltageChgEn = 0x1;
D0F0xBC_x1F300.Field.LclkDpmEn = 0x1;
D0F0xBC_x1F300.Field.LclkDpmBootState = 0x5;
GnbRegisterWriteTN (D0F0xBC_x1F300_TYPE, D0F0xBC_x1F300_ADDRESS, &D0F0xBC_x1F300.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader);
//Programming Lclk Thermal Throttling Threshold
GnbRegisterReadTN (D18F3x64_TYPE, D18F3x64_ADDRESS, &D18F3x64.Value, 0, StdHeader);
GnbRegisterReadTN (D0F0xBC_x1F30C_TYPE, D0F0xBC_x1F30C_ADDRESS, &D0F0xBC_x1F30C.Value, 0, StdHeader);
D0F0xBC_x1F30C.Field.LowThreshold = (UINT16) (((D18F3x64.Field.HtcTmpLmt / 2 + 52) - 1 + 49) * 8);
D0F0xBC_x1F30C.Field.HighThreshold = (UINT16) (((D18F3x64.Field.HtcTmpLmt / 2 + 52) + 49) * 8);
GnbRegisterWriteTN (D0F0xBC_x1F30C_TYPE, D0F0xBC_x1F30C_ADDRESS, &D0F0xBC_x1F30C.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader);
GnbSmuServiceRequestV4 (
GnbPciAddress,
SMC_MSG_CONFIG_LCLK_DPM,
GNB_REG_ACC_FLAG_S3SAVE,
StdHeader
);
}
} else {
Status = AGESA_ERROR;
}
}
IDS_HDT_CONSOLE (GNB_TRACE, "GnbLclkDpmInitTN Exit [0x%x]\n", Status);
return Status;
}
