VOID Phydm_AdaptivityInit( IN PVOID pDM_VOID ) { PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; #if(DM_ODM_SUPPORT_TYPE == ODM_WIN) PADAPTER pAdapter = pDM_Odm->Adapter; PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo); pDM_Odm->Carrier_Sense_enable = (BOOLEAN)pMgntInfo->RegEnableCarrierSense; pDM_Odm->DynamicLinkAdaptivity = (BOOLEAN)pMgntInfo->RegDmLinkAdaptivity; #elif(DM_ODM_SUPPORT_TYPE == ODM_CE) pDM_Odm->Carrier_Sense_enable = (pDM_Odm->Adapter->registrypriv.adaptivity_mode!=0)?TRUE:FALSE; pDM_Odm->DynamicLinkAdaptivity = (pDM_Odm->Adapter->registrypriv.adaptivity_dml!=0)?TRUE:FALSE; #endif #if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN)) if(pDM_Odm->Carrier_Sense_enable == FALSE) { #if(DM_ODM_SUPPORT_TYPE == ODM_WIN) if( pMgntInfo->RegL2HForAdaptivity != 0 ) pDM_Odm->TH_L2H_ini = pMgntInfo->RegL2HForAdaptivity; else #endif pDM_Odm->TH_L2H_ini = 0xf5; // -7 } else { #if(DM_ODM_SUPPORT_TYPE == ODM_WIN) if( pMgntInfo->RegL2HForAdaptivity != 0 ) pDM_Odm->TH_L2H_ini = pMgntInfo->RegL2HForAdaptivity; else #endif pDM_Odm->TH_L2H_ini = 0xa; } #if(DM_ODM_SUPPORT_TYPE == ODM_WIN) if( pMgntInfo->RegHLDiffForAdaptivity != 0 ) pDM_Odm->TH_EDCCA_HL_diff = pMgntInfo->RegHLDiffForAdaptivity; else #endif pDM_Odm->TH_EDCCA_HL_diff = 7; ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("TH_L2H_ini = 0x%x, TH_EDCCA_HL_diff = 0x%x\n", pDM_Odm->TH_L2H_ini, pDM_Odm->TH_EDCCA_HL_diff)); #elif (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) prtl8192cd_priv priv = pDM_Odm->priv; if(pDM_Odm->Carrier_Sense_enable){ pDM_Odm->TH_L2H_ini = 10; pDM_Odm->TH_EDCCA_HL_diff = 7; } else { pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_backup; //set by mib pDM_Odm->TH_EDCCA_HL_diff = 7; } pDM_Odm->TH_L2H_ini_mode2 = 20; pDM_Odm->TH_EDCCA_HL_diff_mode2 = 8; //pDM_Odm->TH_L2H_ini_backup = pDM_Odm->TH_L2H_ini; pDM_Odm->TH_EDCCA_HL_diff_backup = pDM_Odm->TH_EDCCA_HL_diff ; if(priv->pshare->rf_ft_var.adaptivity_enable == 2) pDM_Odm->DynamicLinkAdaptivity = TRUE; else pDM_Odm->DynamicLinkAdaptivity = FALSE; #endif pDM_Odm->IGI_Base = 0x32; pDM_Odm->IGI_target = 0x1c; pDM_Odm->FABound = 6000; pDM_Odm->H2L_lb= 0; pDM_Odm->L2H_lb= 0; pDM_Odm->Adaptivity_IGI_upper = 0; pDM_Odm->NHMWait = 0; pDM_Odm->bCheck = FALSE; pDM_Odm->bFirstLink = TRUE; pDM_Odm->Adaptivity_enable = FALSE; // use this flag to judge enable or disable Phydm_MACEDCCAState(pDM_Odm, PhyDM_DONT_IGNORE_EDCCA); //Search pwdB lower bound if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11N, bMaskDWord, 0x208); ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT9|BIT8, 0x0); /* set forgetting factor = 0 for all n series IC*/ } else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC, bMaskDWord, 0x209); ODM_SetBBReg(pDM_Odm, rFPGA0_XA_LSSIReadBack, BIT1|BIT0, 0x0); } if (pDM_Odm->SupportICType & ODM_RTL8814A) /* 8814a no need to find pwdB lower bound, maybe */ { ODM_SetBBReg(pDM_Odm, ODM_REG_EDCCA_DOWN_OPT, BIT30|BIT29|BIT28, 0x7); /* interfernce need > 2^x us, and then EDCCA will be 1 */ ODM_SetBBReg(pDM_Odm, ODM_REG_EDCCA_POWER_CAL, BIT5, 1); /* 0: mean, 1:max pwdB */ ODM_SetBBReg(pDM_Odm, ODM_REG_ACBB_EDCCA_ENHANCE, BIT29|BIT28, 0x1); /* 0 : rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out */ } else Phydm_SearchPwdBLowerBound(pDM_Odm); }
VOID Phydm_AdaptivityInit( IN PVOID pDM_VOID ) { PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY); #if(DM_ODM_SUPPORT_TYPE == ODM_WIN) PADAPTER pAdapter = pDM_Odm->Adapter; PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo); pDM_Odm->Carrier_Sense_enable = (BOOLEAN)pMgntInfo->RegEnableCarrierSense; pDM_Odm->DCbackoff = (u1Byte)pMgntInfo->RegDCbackoff; Adaptivity->DynamicLinkAdaptivity = (BOOLEAN)pMgntInfo->RegDmLinkAdaptivity; Adaptivity->APNumTH = (u1Byte)pMgntInfo->RegAPNumTH; #elif(DM_ODM_SUPPORT_TYPE == ODM_CE) pDM_Odm->Carrier_Sense_enable = (pDM_Odm->Adapter->registrypriv.adaptivity_mode != 0) ? TRUE : FALSE; pDM_Odm->DCbackoff = pDM_Odm->Adapter->registrypriv.adaptivity_dc_backoff; Adaptivity->DynamicLinkAdaptivity = (pDM_Odm->Adapter->registrypriv.adaptivity_dml != 0) ? TRUE : FALSE; #endif #if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN)) if (pDM_Odm->Carrier_Sense_enable == FALSE) { #if(DM_ODM_SUPPORT_TYPE == ODM_WIN) if (pMgntInfo->RegL2HForAdaptivity != 0) pDM_Odm->TH_L2H_ini = pMgntInfo->RegL2HForAdaptivity; else #endif { pDM_Odm->TH_L2H_ini = 0xf5; } } else { #if(DM_ODM_SUPPORT_TYPE == ODM_WIN) if (pMgntInfo->RegL2HForAdaptivity != 0) pDM_Odm->TH_L2H_ini = pMgntInfo->RegL2HForAdaptivity; else #endif pDM_Odm->TH_L2H_ini = 0xa; } #if(DM_ODM_SUPPORT_TYPE == ODM_WIN) if (pMgntInfo->RegHLDiffForAdaptivity != 0) pDM_Odm->TH_EDCCA_HL_diff = pMgntInfo->RegHLDiffForAdaptivity; else #endif pDM_Odm->TH_EDCCA_HL_diff = 7; ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("TH_L2H_ini = 0x%x, TH_EDCCA_HL_diff = 0x%x\n", pDM_Odm->TH_L2H_ini, pDM_Odm->TH_EDCCA_HL_diff)); #elif (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) prtl8192cd_priv priv = pDM_Odm->priv; if (pDM_Odm->Carrier_Sense_enable) { pDM_Odm->TH_L2H_ini = 0xa; pDM_Odm->TH_EDCCA_HL_diff = 7; } else { pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_backup; /*set by mib*/ pDM_Odm->TH_EDCCA_HL_diff = 7; } Adaptivity->TH_L2H_ini_mode2 = 20; Adaptivity->TH_EDCCA_HL_diff_mode2 = 8; Adaptivity->TH_EDCCA_HL_diff_backup = pDM_Odm->TH_EDCCA_HL_diff; if (priv->pshare->rf_ft_var.adaptivity_enable == 2) Adaptivity->DynamicLinkAdaptivity = TRUE; else Adaptivity->DynamicLinkAdaptivity = FALSE; #endif pDM_Odm->Adaptivity_IGI_upper = 0; pDM_Odm->Adaptivity_enable = FALSE; /*use this flag to decide enable or disable*/ Adaptivity->IGI_Base = 0x32; Adaptivity->IGI_target = 0x1c; Adaptivity->H2L_lb = 0; Adaptivity->L2H_lb = 0; Adaptivity->NHMWait = 0; Adaptivity->bCheck = FALSE; Adaptivity->bFirstLink = TRUE; Phydm_MACEDCCAState(pDM_Odm, PhyDM_DONT_IGNORE_EDCCA); /*Search pwdB lower bound*/ if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11N, bMaskDWord, 0x208); #if (RTL8195A_SUPPORT == 0) else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC, bMaskDWord, 0x209); #endif #if (RTL8195A_SUPPORT == 1) if (pDM_Odm->SupportICType & ODM_RTL8195A) { ODM_SetBBReg(pDM_Odm, ODM_REG_EDCCA_DOWN_OPT_11N, BIT12 | BIT11 | BIT10, 0x7); /*interfernce need > 2^x us, and then EDCCA will be 1*/ ODM_SetBBReg(pDM_Odm, DOM_REG_EDCCA_DCNF_11N, BIT21 | BIT20, 0x1); /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/ } #else if (pDM_Odm->SupportICType & ODM_RTL8814A) { /*8814a no need to find pwdB lower bound, maybe*/ ODM_SetBBReg(pDM_Odm, ODM_REG_EDCCA_DOWN_OPT, BIT30 | BIT29 | BIT28, 0x7); /*interfernce need > 2^x us, and then EDCCA will be 1*/ ODM_SetBBReg(pDM_Odm, ODM_REG_ACBB_EDCCA_ENHANCE, BIT29 | BIT28, 0x1); /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/ } else Phydm_SearchPwdBLowerBound(pDM_Odm); #endif }