static int qlcnic_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) { struct qlcnic_adapter *adapter = netdev_priv(dev); u32 wol_cfg; if (qlcnic_83xx_check(adapter)) return -EOPNOTSUPP; if (wol->wolopts & ~WAKE_MAGIC) return -EINVAL; wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG_NV); if (!(wol_cfg & (1 << adapter->portnum))) return -EOPNOTSUPP; wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG); if (wol->wolopts & WAKE_MAGIC) wol_cfg |= 1UL << adapter->portnum; else wol_cfg &= ~(1UL << adapter->portnum); QLCWR32(adapter, QLCNIC_WOL_CONFIG, wol_cfg); return 0; }
u32 qlcnic_issue_cmd(struct qlcnic_adapter *adapter, u32 pci_fn, u32 version, u32 arg1, u32 arg2, u32 arg3, u32 cmd) { u32 rsp; u32 signature; u32 rcode = QLCNIC_RCODE_SUCCESS; struct pci_dev *pdev = adapter->pdev; signature = QLCNIC_CDRP_SIGNATURE_MAKE(pci_fn, version); /* Acquire semaphore before accessing CRB */ if (qlcnic_api_lock(adapter)) return QLCNIC_RCODE_TIMEOUT; QLCWR32(adapter, QLCNIC_SIGN_CRB_OFFSET, signature); QLCWR32(adapter, QLCNIC_ARG1_CRB_OFFSET, arg1); QLCWR32(adapter, QLCNIC_ARG2_CRB_OFFSET, arg2); QLCWR32(adapter, QLCNIC_ARG3_CRB_OFFSET, arg3); QLCWR32(adapter, QLCNIC_CDRP_CRB_OFFSET, QLCNIC_CDRP_FORM_CMD(cmd)); rsp = qlcnic_poll_rsp(adapter); if (rsp == QLCNIC_CDRP_RSP_TIMEOUT) { dev_err(&pdev->dev, "card response timeout.\n"); rcode = QLCNIC_RCODE_TIMEOUT; } else if (rsp == QLCNIC_CDRP_RSP_FAIL) { rcode = QLCRD32(adapter, QLCNIC_ARG1_CRB_OFFSET); dev_err(&pdev->dev, "failed card response code:0x%x\n", rcode); } /* Release semaphore */ qlcnic_api_unlock(adapter); return rcode; }
static int qlcnic_set_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *pause) { struct qlcnic_adapter *adapter = netdev_priv(netdev); int port = adapter->ahw->physical_port; __u32 val; if (qlcnic_83xx_check(adapter)) return qlcnic_83xx_set_pauseparam(adapter, pause); /* read mode */ if (adapter->ahw->port_type == QLCNIC_GBE) { if ((port < 0) || (port > QLCNIC_NIU_MAX_GBE_PORTS)) return -EIO; /* set flow control */ val = QLCRD32(adapter, QLCNIC_NIU_GB_MAC_CONFIG_0(port)); if (pause->rx_pause) qlcnic_gb_rx_flowctl(val); else qlcnic_gb_unset_rx_flowctl(val); QLCWR32(adapter, QLCNIC_NIU_GB_MAC_CONFIG_0(port), val); QLCWR32(adapter, QLCNIC_NIU_GB_MAC_CONFIG_0(port), val); /* set autoneg */ val = QLCRD32(adapter, QLCNIC_NIU_GB_PAUSE_CTL); switch (port) { case 0: if (pause->tx_pause) qlcnic_gb_unset_gb0_mask(val); else qlcnic_gb_set_gb0_mask(val); break; case 1: if (pause->tx_pause) qlcnic_gb_unset_gb1_mask(val); else qlcnic_gb_set_gb1_mask(val); break; case 2: if (pause->tx_pause) qlcnic_gb_unset_gb2_mask(val); else qlcnic_gb_set_gb2_mask(val); break; case 3: default: if (pause->tx_pause) qlcnic_gb_unset_gb3_mask(val); else qlcnic_gb_set_gb3_mask(val); break; } QLCWR32(adapter, QLCNIC_NIU_GB_PAUSE_CTL, val); } else if (adapter->ahw->port_type == QLCNIC_XGBE) { if (!pause->rx_pause || pause->autoneg) return -EOPNOTSUPP; if ((port < 0) || (port > QLCNIC_NIU_MAX_XG_PORTS)) return -EIO; val = QLCRD32(adapter, QLCNIC_NIU_XG_PAUSE_CTL); if (port == 0) { if (pause->tx_pause) qlcnic_xg_unset_xg0_mask(val); else qlcnic_xg_set_xg0_mask(val); } else { if (pause->tx_pause) qlcnic_xg_unset_xg1_mask(val); else qlcnic_xg_set_xg1_mask(val); } QLCWR32(adapter, QLCNIC_NIU_XG_PAUSE_CTL, val); } else { dev_err(&netdev->dev, "Unknown board type: %x\n", adapter->ahw->port_type); } return 0; }