static void rcba_config(void)
{
/* Set up virtual channel 0 */
RCBA32(0x0014) = 0x80000001;
RCBA32(0x001c) = 0x03128010;
/* Device 1f interrupt pin register */
RCBA32(0x3100) = 0x00042210;
RCBA32(0x3108) = 0x10004321;
RCBA32(0x3104) = 0x00002100;
/* PCIe Interrupts */
RCBA32(0x310c) = 0x00214321;
/* HD Audio Interrupt */
RCBA32(0x3110) = 0x00000001;
/* dev irq route register */
RCBA16(0x3140) = 0x0132;
RCBA16(0x3142) = 0x0146;
RCBA16(0x3144) = 0x0237;
RCBA16(0x3146) = 0x3201;
RCBA16(0x3148) = 0x0146;
/* Enable IOAPIC */
RCBA8(0x31ff) = 0x03;
RCBA32(0x3418) = 0x003000e2;
RCBA32(0x3418) |= 1;
}
static void rcba_config(void)
{
/* Set up virtual channel 0 */
//RCBA32(0x0014) = 0x80000001;
//RCBA32(0x001c) = 0x03128010;
/* Device 1f interrupt pin register */
RCBA32(0x3100) = 0x00042210;
/* Device 1d interrupt pin register */
RCBA32(0x310c) = 0x00214321;
/* dev irq route register */
RCBA16(0x3140) = 0x0132;
RCBA16(0x3142) = 0x0146;
RCBA16(0x3144) = 0x0237;
RCBA16(0x3146) = 0x3201;
RCBA16(0x3148) = 0x0146;
/* Enable IOAPIC */
RCBA8(0x31ff) = 0x03;
/* Disable unused devices */
//RCBA32(0x3418) = FD_PCIE6|FD_PCIE5|FD_PCIE4|FD_ACMOD|FD_ACAUD|FD_PATA;
// RCBA32(0x3418) |= (1 << 0); // Required.
// FIXME look me up!
RCBA32(0x3418) = 0x003204e1;
/* Enable PCIe Root Port Clock Gate */
// RCBA32(0x341c) = 0x00000001;
}
static void i82801gx_spi_init(void)
{
u16 spicontrol;
spicontrol = RCBA16(SPIBASE + 2);
spicontrol &= ~(1 << 0); // SPI Access Request
RCBA16(SPIBASE + 2) = spicontrol;
}
static void rcba_config(void)
{
u32 reg32;
/*
* GFX INTA -> PIRQA (MSI)
* D28IP_P2IP WLAN INTA -> PIRQB
* D28IP_P3IP ETH0 INTC -> PIRQD
* D29IP_E1P EHCI1 INTA -> PIRQE
* D26IP_E2P EHCI2 INTA -> PIRQE
* D31IP_SIP SATA INTA -> PIRQF (MSI)
* D31IP_SMIP SMBUS INTB -> PIRQG
* D31IP_TTIP THRT INTC -> PIRQH
* D27IP_ZIP HDA INTA -> PIRQG (MSI)
*
* Trackpad DVT PIRQA (16)
* Trackpad DVT PIRQE (20)
*/
/* Device interrupt pin register (board specific) */
RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
(INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
RCBA32(D30IP) = (NOINT << D30IP_PIP);
RCBA32(D29IP) = (INTA << D29IP_E1P);
RCBA32(D28IP) = (NOINT << D28IP_P1IP) | (INTA << D28IP_P2IP) |
(INTC << D28IP_P3IP) | (NOINT << D28IP_P4IP) |
(NOINT << D28IP_P5IP) | (NOINT << D28IP_P6IP) |
(NOINT << D28IP_P7IP) | (NOINT << D28IP_P8IP);
RCBA32(D27IP) = (INTA << D27IP_ZIP);
RCBA32(D26IP) = (INTA << D26IP_E2P);
RCBA32(D25IP) = (NOINT << D25IP_LIP);
RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
/* Device interrupt route registers */
DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC);
DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE);
DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB);
DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH);
DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
/* Enable IOAPIC (generic) */
RCBA16(OIC) = 0x0100;
/* PCH BWG says to read back the IOAPIC enable register */
(void) RCBA16(OIC);
/* Disable unused devices (board specific) */
reg32 = RCBA32(FD);
reg32 |= PCH_DISABLE_ALWAYS;
/* Disable PCI bridge so MRC does not probe this bus */
reg32 |= PCH_DISABLE_P2P;
RCBA32(FD) = reg32;
}
static void early_ich7_init(void)
{
uint8_t reg8;
uint32_t reg32;
// program secondary mlt XXX byte?
pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
// reset rtc power status
reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
reg8 &= ~(1 << 2);
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
// usb transient disconnect
reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
reg8 |= (3 << 0);
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
reg32 |= (1 << 29) | (1 << 17);
pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
reg32 |= (1 << 31) | (1 << 27);
pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
RCBA32(0x0088) = 0x0011d000;
RCBA16(0x01fc) = 0x060f;
RCBA32(0x01f4) = 0x86000040;
RCBA32(0x0214) = 0x10030549;
RCBA32(0x0218) = 0x00020504;
RCBA8(0x0220) = 0xc5;
reg32 = RCBA32(0x3410);
reg32 |= (1 << 6);
RCBA32(0x3410) = reg32;
reg32 = RCBA32(0x3430);
reg32 &= ~(3 << 0);
reg32 |= (1 << 0);
RCBA32(0x3430) = reg32;
RCBA32(0x3418) |= (1 << 0);
RCBA16(0x0200) = 0x2008;
RCBA8(0x2027) = 0x0d;
RCBA16(0x3e08) |= (1 << 7);
RCBA16(0x3e48) |= (1 << 7);
RCBA32(0x3e0e) |= (1 << 7);
RCBA32(0x3e4e) |= (1 << 7);
// next step only on ich7m b0 and later:
reg32 = RCBA32(0x2034);
reg32 &= ~(0x0f << 16);
reg32 |= (5 << 16);
RCBA32(0x2034) = reg32;
}
void mainboard_rcba_config(void)
{
u32 reg32;
/*
* GFX INTA -> PIRQA (MSI)
* D20IP_XHCI XHCI INTA -> PIRQD (MSI)
* D26IP_E2P EHCI #2 INTA -> PIRQF
* D27IP_ZIP HDA INTA -> PIRQA (MSI)
* D28IP_P2IP WLAN INTA -> PIRQD
* D28IP_P3IP Card Reader INTB -> PIRQE
* D28IP_P6IP LAN INTC -> PIRQB
* D29IP_E1P EHCI #1 INTA -> PIRQD
* D31IP_SIP SATA INTA -> PIRQB (MSI)
* D31IP_SMIP SMBUS INTB -> PIRQH
*/
/* Device interrupt pin register (board specific) */
RCBA32(D31IP) = (NOINT << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
(INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
RCBA32(D30IP) = (NOINT << D30IP_PIP);
RCBA32(D29IP) = (INTA << D29IP_E1P);
RCBA32(D28IP) = (NOINT << D28IP_P1IP) | (INTA << D28IP_P2IP) |
(INTB << D28IP_P3IP) | (NOINT << D28IP_P4IP) |
(NOINT << D28IP_P5IP) | (INTC << D28IP_P6IP) |
(NOINT << D28IP_P7IP) | (NOINT << D28IP_P8IP);
RCBA32(D27IP) = (INTA << D27IP_ZIP);
RCBA32(D26IP) = (INTA << D26IP_E2P);
RCBA32(D25IP) = (NOINT << D25IP_LIP);
RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
RCBA32(D20IP) = (INTA << D20IP_XHCIIP);
/* Device interrupt route registers */
DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC);
DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
DIR_ROUTE(D28IR, PIRQD, PIRQE, PIRQB, PIRQC);
DIR_ROUTE(D27IR, PIRQA, PIRQB, PIRQC, PIRQD);
DIR_ROUTE(D26IR, PIRQF, PIRQB, PIRQC, PIRQD);
DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
DIR_ROUTE(D20IR, PIRQD, PIRQE, PIRQF, PIRQG);
/* Enable IOAPIC (generic) */
RCBA16(OIC) = 0x0100;
/* PCH BWG says to read back the IOAPIC enable register */
(void) RCBA16(OIC);
/* Disable unused devices (board specific) */
reg32 = RCBA32(FD);
/* Disable PCI bridge so MRC does not probe this bus */
reg32 |= PCH_DISABLE_P2P;
RCBA32(FD) = reg32;
}
void mainboard_rcba_config(void)
{
u32 reg32;
/*
* GFX INTA -> PIRQA (MSI)
* D28IP_P1IP WLAN INTA -> PIRQB
* D28IP_P2IP ETH0 INTB -> PIRQF
* D28IP_P3IP SDCARD INTC -> PIRQD
* D29IP_E1P EHCI1 INTA -> PIRQD
* D26IP_E2P EHCI2 INTA -> PIRQF
* D31IP_SIP SATA INTA -> PIRQB (MSI)
* D31IP_SMIP SMBUS INTB -> PIRQH
* D31IP_TTIP THRT INTC -> PIRQA
* D27IP_ZIP HDA INTA -> PIRQA (MSI)
*
* Trackpad interrupt is edge triggered and cannot be shared.
* TRACKPAD -> PIRQG
*/
/* Device interrupt pin register (board specific) */
RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
(INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
RCBA32(D29IP) = (INTA << D29IP_E1P);
RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) |
(INTC << D28IP_P3IP);
RCBA32(D27IP) = (INTA << D27IP_ZIP);
RCBA32(D26IP) = (INTA << D26IP_E2P);
RCBA32(D25IP) = (NOINT << D25IP_LIP);
RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
/* Device interrupt route registers */
DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC);
DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE);
DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB);
DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH);
DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
/* Enable IOAPIC (generic) */
RCBA16(OIC) = 0x0100;
/* PCH BWG says to read back the IOAPIC enable register */
(void) RCBA16(OIC);
/* Disable unused devices (board specific) */
reg32 = RCBA32(FD);
/* Disable PCI bridge so MRC does not probe this bus */
reg32 |= PCH_DISABLE_P2P;
RCBA32(FD) = reg32;
}
void intel_pch_finalize_smm(void)
{
if (CONFIG_LOCK_SPI_ON_RESUME_RO || CONFIG_LOCK_SPI_ON_RESUME_NO_ACCESS) {
/* Copy flash regions from FREG0-4 to PR0-4
and enable write protection bit31 */
int i;
u32 lockmask = (1 << 31);
if (CONFIG_LOCK_SPI_ON_RESUME_NO_ACCESS)
lockmask |= (1 << 15);
for (i = 0; i < 20; i += 4)
RCBA32(0x3874 + i) = RCBA32(0x3854 + i) | lockmask;
}
/* Set SPI opcode menu */
RCBA16(0x3894) = SPI_OPPREFIX;
RCBA16(0x3896) = SPI_OPTYPE;
RCBA32(0x3898) = SPI_OPMENU_LOWER;
RCBA32(0x389c) = SPI_OPMENU_UPPER;
/* Lock SPIBAR */
RCBA32_OR(0x3804, (1 << 15));
#if CONFIG_SPI_FLASH_SMM
/* Re-init SPI driver to handle locked BAR */
spi_init();
#endif
/* TCLOCKDN: TC Lockdown */
RCBA32_OR(0x0050, (1 << 31));
/* BIOS Interface Lockdown */
RCBA32_OR(0x3410, (1 << 0));
/* Function Disable SUS Well Lockdown */
RCBA_AND_OR(8, 0x3420, ~0U, (1 << 7));
/* Global SMI Lock */
pci_or_config16(PCH_LPC_DEV, 0xa0, 1 << 4);
/* GEN_PMCON Lock */
pci_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2));
/* R/WO registers */
RCBA32(0x21a4) = RCBA32(0x21a4);
pci_write_config32(PCI_DEV(0, 27, 0), 0x74,
pci_read_config32(PCI_DEV(0, 27, 0), 0x74));
/* Indicate finalize step with post code */
outb(POST_OS_BOOT, 0x80);
}
static void rcba_config(void)
{
u32 reg32;
/*
* GFX INTA -> PIRQA (MSI)
* D28IP_P3IP WLAN INTA -> PIRQB
* D29IP_E1P EHCI1 INTA -> PIRQD
* D26IP_E2P EHCI2 INTA -> PIRQF
* D31IP_SIP SATA INTA -> PIRQF (MSI)
* D31IP_SMIP SMBUS INTB -> PIRQH
* D31IP_TTIP THRT INTC -> PIRQA
* D27IP_ZIP HDA INTA -> PIRQA (MSI)
*
* TRACKPAD -> PIRQE (Edge Triggered)
* TOUCHSCREEN -> PIRQG (Edge Triggered)
*/
/* Device interrupt pin register (board specific) */
RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
(INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
RCBA32(D30IP) = (NOINT << D30IP_PIP);
RCBA32(D29IP) = (INTA << D29IP_E1P);
RCBA32(D28IP) = (INTA << D28IP_P3IP);
RCBA32(D27IP) = (INTA << D27IP_ZIP);
RCBA32(D26IP) = (INTA << D26IP_E2P);
RCBA32(D25IP) = (NOINT << D25IP_LIP);
RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
/* Device interrupt route registers */
DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC);
DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE);
DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB);
DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH);
DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
/* Enable IOAPIC (generic) */
RCBA16(OIC) = 0x0100;
/* PCH BWG says to read back the IOAPIC enable register */
(void) RCBA16(OIC);
/* Disable unused devices (board specific) */
reg32 = RCBA32(FD);
reg32 |= PCH_DISABLE_ALWAYS;
RCBA32(FD) = reg32;
}
static u32 southbrigde_smi_mask_events(u32 smi_sts)
{
/* Clear all disabled bits in SMI_EN but the reserved ones. */
smi_sts &= inl(pmbase + SMI_EN) | 0xf7f99700;
/* Check if SCI is enabled. */
if (inl(pmbase + PM1_CNT) & SCI_EN)
/* Clear PM1, GPE. */
smi_sts &= ~((1 << 8) | (1 << 9));
/* Check if SPI generates SMI. */
if (!(RCBA16(0x3806) & (1 << 15)) &&
!(RCBA16(0x3891) & (1 << 15)))
/* Clear SPI. */
smi_sts &= ~(1 << 26);
return smi_sts;
}
void
southbridge_configure_default_intmap(void)
{
/*
* GFX INTA -> PIRQA (MSI)
* D28IP_P1IP SLOT1 INTA -> PIRQB
* D28IP_P2IP SLOT2 INTB -> PIRQF
* D28IP_P3IP SLOT3 INTC -> PIRQD
* D28IP_P5IP SLOT5 INTC -> PIRQD
* D29IP_E1P EHCI1 INTA -> PIRQD
* D26IP_E2P EHCI2 INTA -> PIRQF
* D31IP_SIP SATA INTA -> PIRQB (MSI)
* D31IP_SMIP SMBUS INTB -> PIRQH
* D31IP_TTIP THRT INTC -> PIRQA
* D27IP_ZIP HDA INTA -> PIRQA (MSI)
*
*/
RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
(INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
RCBA32(D30IP) = (NOINT << D30IP_PIP);
RCBA32(D29IP) = (INTA << D29IP_E1P);
RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) |
(INTC << D28IP_P3IP) | (INTC << D28IP_P5IP);
RCBA32(D27IP) = (INTA << D27IP_ZIP);
RCBA32(D26IP) = (INTA << D26IP_E2P);
RCBA32(D25IP) = (NOINT << D25IP_LIP);
RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
/* Device interrupt route registers */
DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC);
DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE);
DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB);
DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH);
DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
/* Enable IOAPIC (generic) */
RCBA16(OIC) = 0x0100;
/* PCH BWG says to read back the IOAPIC enable register */
(void) RCBA16(OIC);
}
void pch_iobp_write(u32 address, u32 data)
{
u16 status;
if (!iobp_poll())
return;
/* Set the address */
RCBA32(IOBPIRI) = address;
/* WRITE OPCODE */
status = RCBA16(IOBPS);
status &= ~IOBPS_MASK;
status |= IOBPS_WRITE;
RCBA16(IOBPS) = status;
RCBA32(IOBPD) = data;
/* Undocumented magic */
RCBA16(IOBPU) = IOBPU_MAGIC;
/* Set ready bit */
status = RCBA16(IOBPS);
status |= IOBPS_READY;
RCBA16(IOBPS) = status;
if (!iobp_poll())
return;
/* Check for successful transaction */
status = RCBA16(IOBPS);
if (status & IOBPS_TX_MASK)
printk(BIOS_ERR, "IOBP: write 0x%08x failed\n", address);
}
void pch_iobp_exec(u32 addr, u16 op_code, u8 route_id, u32 *data, u8 *resp)
{
if (!data || !resp)
return;
*resp = -1;
if (!iobp_poll())
return;
/* RCBA2330[31:0] = Address */
RCBA32(IOBPIRI) = addr;
/* RCBA2338[15:8] = opcode */
RCBA16(IOBPS) = (RCBA16(IOBPS) & 0x00ff) | op_code;
/* RCBA233A[15:8] = 0xf0 RCBA233A[7:0] = Route ID */
RCBA16(IOBPU) = IOBPU_MAGIC | route_id;
if (op_code == IOBP_PCICFG_WRITE)
RCBA32(IOBPD) = *data;
/* Set RCBA2338[0] to trigger IOBP transaction*/
RCBA16(IOBPS) = RCBA16(IOBPS) | 0x1;
if (!iobp_poll())
return;
*resp = (RCBA16(IOBPS) & IOBPS_TX_MASK) >> 1;
*data = RCBA32(IOBPD);
}
void intel_pch_finalize_smm(void)
{
/* Set SPI opcode menu */
RCBA16(0x3894) = SPI_OPPREFIX;
RCBA16(0x3896) = SPI_OPTYPE;
RCBA32(0x3898) = SPI_OPMENU_LOWER;
RCBA32(0x389c) = SPI_OPMENU_UPPER;
/* Lock SPIBAR */
RCBA32_OR(0x3804, (1 << 15));
#if CONFIG_SPI_FLASH_SMM
/* Re-init SPI driver to handle locked BAR */
spi_init();
#endif
/* TCLOCKDN: TC Lockdown */
RCBA32_OR(0x0050, (1 << 31));
/* BIOS Interface Lockdown */
RCBA32_OR(0x3410, (1 << 0));
/* Function Disable SUS Well Lockdown */
RCBA_AND_OR(8, 0x3420, ~0U, (1 << 7));
/* Global SMI Lock */
pcie_or_config16(PCH_LPC_DEV, 0xa0, 1 << 4);
/* GEN_PMCON Lock */
pcie_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2));
/* R/WO registers */
RCBA32(0x21a4) = RCBA32(0x21a4);
pcie_write_config32(PCI_DEV(0, 27, 0), 0x74,
pcie_read_config32(PCI_DEV(0, 27, 0), 0x74));
/* Indicate finalize step with post code */
outb(POST_OS_BOOT, 0x80);
}
static void rcba_config(void)
{
/* Set up virtual channel 0 */
//RCBA32(0x0014) = 0x80000001;
//RCBA32(0x001c) = 0x03128010;
/* Device 1f interrupt pin register */
RCBA32(0x3100) = 0x00042220;
/* Device 1d interrupt pin register */
RCBA32(0x310c) = 0x00214321;
/* dev irq route register */
RCBA16(0x3140) = 0x0232;
RCBA16(0x3142) = 0x3246;
RCBA16(0x3144) = 0x0237;
RCBA16(0x3146) = 0x3201;
RCBA16(0x3148) = 0x3216;
/* Enable IOAPIC */
RCBA8(0x31ff) = 0x03;
/* Disable unused devices */
RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_PCIE3 | FD_PCIE2 |
FD_INTLAN | FD_ACMOD | FD_HDAUD | FD_PATA;
RCBA32(0x3418) |= (1 << 0); // Required.
/* Enable PCIe Root Port Clock Gate */
// RCBA32(0x341c) = 0x00000001;
/* This should probably go into the ACPI OS Init trap */
/* Set up I/O Trap #0 for 0xfe00 (SMIC) */
RCBA32(0x1e84) = 0x00020001;
RCBA32(0x1e80) = 0x0000fe01;
/* Set up I/O Trap #3 for 0x800-0x80c (Trap) */
RCBA32(0x1e9c) = 0x000200f0;
RCBA32(0x1e98) = 0x000c0801;
}
static void mb_lpc_setup(void)
{
u32 reg32;
/* Set the value for GPIO base address register and enable GPIO. */
pci_write_config32(LPC_DEV, GPIO_BASE, (DEFAULT_GPIOBASE | 1));
pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10);
setup_pch_gpios(&mainboard_gpio_map);
/* Set GPIOs on superio, enable UART */
if (IS_ENABLED(CONFIG_SUPERIO_NUVOTON_NCT6776)) {
nuvoton_pnp_enter_conf_state(SERIAL_DEV_R2);
pnp_set_logical_device(SERIAL_DEV_R2);
pnp_write_config(SERIAL_DEV_R2, 0x1c, 0x80);
pnp_write_config(SERIAL_DEV_R2, 0x27, 0x80);
pnp_write_config(SERIAL_DEV_R2, 0x2a, 0x60);
nuvoton_pnp_exit_conf_state(SERIAL_DEV_R2);
nuvoton_enable_serial(SERIAL_DEV_R2, CONFIG_TTYS0_BASE);
} else {
winbond_enable_serial(SERIAL_DEV_R1, CONFIG_TTYS0_BASE);
}
/* IRQ routing */
RCBA16(D31IR) = 0x0132;
RCBA16(D29IR) = 0x0237;
/* Enable IOAPIC */
RCBA8(OIC) = 0x03;
RCBA8(OIC);
reg32 = RCBA32(GCS);
reg32 |= (1 << 5);
RCBA32(GCS) = reg32;
RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_ACMOD
| FD_ACAUD | 1;
RCBA32(CG) = 0x00000001;
}
static void rcba_config(void)
{
/* V0CTL Virtual Channel 0 Resource Control */
RCBA32(0x0014) = 0x80000001;
/* V1CAP Virtual Channel 1 Resource Capability */
RCBA32(0x001c) = 0x03128010;
/* Device 1f interrupt pin register */
RCBA32(0x3100) = 0x00042210;
RCBA32(0x3108) = 0x10004321;
/* PCIe Interrupts */
RCBA32(0x310c) = 0x00214321;
/* HD Audio Interrupt */
RCBA32(0x3110) = 0x00000001;
/* dev irq route register */
RCBA16(0x3140) = 0x0232;
RCBA16(0x3142) = 0x3246;
RCBA16(0x3144) = 0x0235;
RCBA16(0x3146) = 0x3201;
RCBA16(0x3148) = 0x3216;
/* Enable IOAPIC */
RCBA8(0x31ff) = 0x03;
/* Disable unused devices */
RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_INTLAN | FD_ACMOD | FD_ACAUD;
RCBA32(0x3418) |= (1 << 0); // Required.
/* Set up I/O Trap #0 for 0xfe00 (SMIC) */
// RCBA32(0x1e84) = 0x00020001;
// RCBA32(0x1e80) = 0x0000fe01;
/* Set up I/O Trap #3 for 0x800-0x80c (Trap) */
RCBA32(0x1e9c) = 0x000200f0;
RCBA32(0x1e98) = 0x000c0801;
}
static inline int iobp_poll(void)
{
unsigned int try;
for (try = IOBP_RETRY; try > 0; try--) {
u16 status = RCBA16(IOBPS);
if ((status & IOBPS_READY) == 0)
return 1;
udelay(10);
}
printk(BIOS_ERR, "IOBP: timeout waiting for transaction to complete\n");
return 0;
}
u32 pch_iobp_read(u32 address)
{
u16 status;
if (!iobp_poll())
return 0;
/* Set the address */
RCBA32(IOBPIRI) = address;
/* READ OPCODE */
status = RCBA16(IOBPS);
status &= ~IOBPS_MASK;
status |= IOBPS_READ;
RCBA16(IOBPS) = status;
/* Undocumented magic */
RCBA16(IOBPU) = IOBPU_MAGIC;
/* Set ready bit */
status = RCBA16(IOBPS);
status |= IOBPS_READY;
RCBA16(IOBPS) = status;
if (!iobp_poll())
return 0;
/* Check for successful transaction */
status = RCBA16(IOBPS);
if (status & IOBPS_TX_MASK) {
printk(BIOS_ERR, "IOBP: read 0x%08x failed\n", address);
return 0;
}
/* Read IOBP data */
return RCBA32(IOBPD);
}
static void rcba_config(void)
{
/* Set up virtual channel 0 */
RCBA32(0x0014) = 0x80000001;
RCBA32(0x001c) = 0x03128010;
/* Device 1f interrupt pin register */
RCBA32(0x3100) = 0x00001230;
RCBA32(0x3108) = 0x40004321;
/* PCIe Interrupts */
RCBA32(0x310c) = 0x00004321;
/* HD Audio Interrupt */
RCBA32(0x3110) = 0x00000002;
/* dev irq route register */
RCBA16(0x3140) = 0x1007;
RCBA16(0x3142) = 0x0076;
RCBA16(0x3144) = 0x3210;
RCBA16(0x3146) = 0x7654;
RCBA16(0x3148) = 0x0010;
/* Enable IOAPIC */
RCBA8(0x31ff) = 0x03;
/* Disable unused devices */
RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD;
RCBA32(0x3418) |= (1 << 0); // Required.
/* Set up I/O Trap #0 for 0xfe00 (SMIC) */
RCBA32(0x1e84) = 0x00020001;
RCBA32(0x1e80) = 0x0000fe01;
/* Set up I/O Trap #3 for 0x800-0x80c (Trap) */
RCBA32(0x1e9c) = 0x000200f0;
RCBA32(0x1e98) = 0x000c0801;
}
static void rcba_config(void)
{
/* Set up virtual channel 0 */
//RCBA32(0x0014) = 0x80000001;
//RCBA32(0x001c) = 0x03128010;
/* Device 1f interrupt pin register */
RCBA32(0x3100) = 0x00042210;
/* Device 1d interrupt pin register */
RCBA32(0x310c) = 0x00214321;
/* dev irq route register */
RCBA16(0x3140) = 0x0132;
RCBA16(0x3142) = 0x0146;
RCBA16(0x3144) = 0x0237;
RCBA16(0x3146) = 0x3201;
RCBA16(0x3148) = 0x0146;
/* Enable IOAPIC */
RCBA8(0x31ff) = 0x03;
/* Enable PCIe Root Port Clock Gate */
// RCBA32(0x341c) = 0x00000001;
}
static int early_spi_read_block(u32 offset, u8 size, u8 *buffer)
{
u32 *ptr32 = (u32*)buffer;
u32 i;
/* Clear status bits */
RCBA16(SPIBAR_HSFS) |= SPIBAR_HSFS_AEL | SPIBAR_HSFS_FCERR |
SPIBAR_HSFS_FDONE;
if (RCBA16(SPIBAR_HSFS) & SPIBAR_HSFS_SCIP) {
printk(BIOS_ERR, "SPI ERROR: transaction in progress\n");
return -1;
}
/* Set flash address */
RCBA32(SPIBAR_FADDR) = offset;
/* Setup read transaction */
RCBA16(SPIBAR_HSFC) = SPIBAR_HSFC_BYTE_COUNT(size) |
SPIBAR_HSFC_CYCLE_READ;
/* Start transactinon */
RCBA16(SPIBAR_HSFC) |= SPIBAR_HSFC_GO;
/* Wait for completion */
for (i = 0; i < SPI_RETRY; i++) {
if (RCBA16(SPIBAR_HSFS) & SPIBAR_HSFS_SCIP) {
/* Cycle in progress, wait 1ms */
udelay(SPI_DELAY);
continue;
}
if (RCBA16(SPIBAR_HSFS) & SPIBAR_HSFS_AEL) {
printk(BIOS_ERR, "SPI ERROR: Access Error\n");
return -1;
}
if (RCBA16(SPIBAR_HSFS) & SPIBAR_HSFS_FCERR) {
printk(BIOS_ERR, "SPI ERROR: Flash Cycle Error\n");
return -1;
}
break;
}
if (i >= SPI_RETRY) {
printk(BIOS_ERR, "SPI ERROR: Timeout\n");
return -1;
}
/* Read the data */
for (i = 0; i < size; i+=sizeof(u32)) {
if (size-i >= 4) {
/* reading >= dword */
*ptr32++ = RCBA32(SPIBAR_FDATA(i/sizeof(u32)));
} else {
/* reading < dword */
u8 j, *ptr8 = (u8*)ptr32;
u32 temp = RCBA32(SPIBAR_FDATA(i/sizeof(u32)));
for (j = 0; j < (size-i); j++) {
*ptr8++ = temp & 0xff;
temp >>= 8;
}
}
}
return size;
}
void
southbridge_configure_default_intmap(void)
{
/*
* For the PCH internal PCI functions, provide a reasonable
* default IRQ mapping that utilizes only PIRQ A to D. Higher
* PIRQs are sometimes used for other on-board chips that
* require an edge triggered interrupt which is not shareable.
*/
/*
* We use a linear mapping for the pin numbers. They are not
* physical pins, and thus, have no relation between the dif-
* ferent devices. Only rule we must obey is that a single-
* function device has to use pin A.
*/
RCBA32(D31IP) = (INTD << D31IP_TTIP) | (INTC << D31IP_SIP2) |
(INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
RCBA32(D29IP) = (INTA << D29IP_E1P);
RCBA32(D28IP) = (INTD << D28IP_P8IP) | (INTC << D28IP_P7IP) |
(INTB << D28IP_P6IP) | (INTA << D28IP_P5IP) |
(INTD << D28IP_P4IP) | (INTC << D28IP_P3IP) |
(INTB << D28IP_P2IP) | (INTA << D28IP_P1IP);
RCBA32(D27IP) = (INTA << D27IP_ZIP);
RCBA32(D26IP) = (INTA << D26IP_E2P);
RCBA32(D25IP) = (INTA << D25IP_LIP);
RCBA32(D22IP) = (INTA << D22IP_MEI1IP);
RCBA32(D20IP) = (INTA << D20IP_XHCIIP);
/*
* For the PIRQ allocation the following was taken into
* account:
* o Interrupts of the PCIe root ports are only about
* events at the ports, not downstream devices. So we
* don't expect many interrupts there and ignore them.
* o We don't expect to talk constantly to the ME either
* so ignore that, too. Same for SMBus and the thermal
* device.
* o Second SATA interface is only used in non-AHCI mode
* so unlikely to coexist with modern interfaces (e.g.
* xHCI).
* o An OS that knows USB3 will likely also know how to
* use MSI.
*
* The functions that might matter first:
*
* D31IP_SIP SATA 1 -> PIRQ A (MSI capable in AHCI mode)
* D31IP_SIP2 SATA 2 -> PIRQ B
* D29IP_E1P EHCI 1 -> PIRQ C
* D27IP_ZIP HDA -> PIRQ D (MSI capable)
* D26IP_E2P EHCI 2 -> PIRQ D
* D25IP_LIP GbE -> PIRQ B (MSI capable)
* D20IP_XHCIIP xHCI -> PIRQ B (MSI capable)
*
* D31IP_TTIP Thermal -> PIRQ B
* D31IP_SMIP SMBUS -> PIRQ A
* D28IP_* PCIe RP -> PIRQ A-D (MSI capable)
* D22IP_MEI1IP ME -> PIRQ A (MSI capable)
*
* Note, CPU-integrated functions seem to always use PIRQ A.
*/
#define _none 0
DIR_ROUTE(D31IR, PIRQA, PIRQA, PIRQB, PIRQB);
DIR_ROUTE(D29IR, PIRQC, _none, _none, _none);
DIR_ROUTE(D28IR, PIRQA, PIRQB, PIRQC, PIRQD);
DIR_ROUTE(D27IR, PIRQD, _none, _none, _none);
DIR_ROUTE(D26IR, PIRQD, _none, _none, _none);
DIR_ROUTE(D25IR, PIRQB, _none, _none, _none);
DIR_ROUTE(D22IR, PIRQA, _none, _none, _none);
DIR_ROUTE(D20IR, PIRQB, _none, _none, _none);
#undef _none
/* Enable IOAPIC (generic) */
RCBA16(OIC) = 0x0100;
/* PCH BWG says to read back the IOAPIC enable register */
(void) RCBA16(OIC);
}
static void pineview_setup_bars(void)
{
u8 reg8;
u16 reg16;
u32 reg32;
/* Setting up Southbridge. In the northbridge code. */
printk(BIOS_DEBUG, "Setting up static southbridge registers...");
pci_write_config32(LPC, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
pci_write_config32(LPC, PMBASE, DEFAULT_PMBASE | 1);
pci_write_config8(LPC, 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI */
pci_write_config32(LPC, GPIOBASE, DEFAULT_GPIOBASE | 1);
pci_write_config8(LPC, 0x4c /* GC */ , 0x10); /* Enable GPIOs */
pci_write_config32(LPC, 0x88, 0x007c0291);
pci_write_config32(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
printk(BIOS_DEBUG, " done.\n");
printk(BIOS_DEBUG, "Disabling Watchdog reboot...");
RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */
outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */
printk(BIOS_DEBUG, " done.\n");
/* Enable upper 128bytes of CMOS */
RCBA32(0x3400) = (1 << 2);
printk(BIOS_DEBUG, "Setting up static northbridge registers...");
pci_write_config8(D0F0, 0x8, 0x69);
/* Set up all hardcoded northbridge BARs */
pci_write_config32(D0F0, EPBAR, DEFAULT_EPBAR | 1);
pci_write_config32(D0F0, MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1);
pci_write_config32(D0F0, DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1);
pci_write_config32(D0F0, PMIOBAR, (uintptr_t)0x400 | 1);
reg32 = MCHBAR32(0x30);
MCHBAR32(0x30) = 0x21800;
DMIBAR32(0x2c) = 0x86000040;
pci_write_config8(D0F0, DEVEN, 0x09);
pci_write_config32(PCI_DEV(0, 0x1e, 0), 0x18, 0x00020200);
pci_write_config32(PCI_DEV(0, 0x1e, 0), 0x18, 0x00000000);
reg8 = pci_read_config8(D0F0, 0xe5); // 0x10
reg16 = pci_read_config16(PCI_DEV(0, 0x02, 0), 0x0); // 0x8086
reg16 = pci_read_config16(D0F0, GGC);
pci_write_config16(D0F0, GGC, 0x130);
reg16 = pci_read_config16(D0F0, GGC);
pci_write_config16(D0F0, GGC, 0x130);
MCHBAR8(0xb08) = 0x20;
reg8 = pci_read_config8(D0F0, 0xe6); // 0x11
reg16 = MCHBAR16(0xc8c);
MCHBAR16(0xc8c) = reg16 | 0x0200;
reg8 = MCHBAR8(0xc8c);
MCHBAR8(0xc8c) = reg8;
MCHBAR8(0xc8c) = 0x12;
pci_write_config8(PCI_DEV(0, 0x02, 0), 0x62, 0x02);
pci_write_config16(PCI_DEV(0, 0x02, 0), 0xe8, 0x8000);
MCHBAR32(0x3004) = 0x48000000;
MCHBAR32(0x3008) = 0xfffffe00;
MCHBAR32(0xb08) = 0x06028220;
MCHBAR32(0xff4) = 0xc6db8b5f;
MCHBAR16(0xff8) = 0x024f;
// PLL Voltage controlled oscillator
//MCHBAR8(0xc38) = 0x04;
pci_write_config16(PCI_DEV(0, 0x02, 0), 0xcc, 0x014d);
reg32 = MCHBAR32(0x40);
MCHBAR32(0x40) = 0x0;
reg32 = MCHBAR32(0x40);
MCHBAR32(0x40) = 0x8;
pci_write_config8(LPC, 0x8, 0x1d);
pci_write_config8(LPC, 0x8, 0x0);
RCBA32(0x3410) = 0x00020465;
RCBA32(0x88) = 0x0011d000;
RCBA32(0x1fc) = 0x60f;
RCBA32(0x1f4) = 0x86000040;
RCBA32(0x214) = 0x10030509;
RCBA32(0x218) = 0x00020504;
RCBA32(0x220) = 0xc5;
RCBA32(0x3430) = 0x1;
RCBA32(0x2027) = 0x38f6a70d;
RCBA16(0x3e08) = 0x0080;
RCBA16(0x3e48) = 0x0080;
RCBA32(0x3e0e) = 0x00000080;
RCBA32(0x3e4e) = 0x00000080;
RCBA32(0x2034) = 0xb24577cc;
RCBA32(0x1c) = 0x03128010;
RCBA32(0x2010) = 0x400;
RCBA32(0x3400) = 0x4;
RCBA32(0x2080) = 0x18006007;
RCBA32(0x20a0) = 0x18006007;
RCBA32(0x20c0) = 0x18006007;
RCBA32(0x20e0) = 0x18006007;
pci_write_config32(PCI_DEV(0, 0x1d, 0), 0xca, 0x1);
pci_write_config32(PCI_DEV(0, 0x1d, 1), 0xca, 0x1);
pci_write_config32(PCI_DEV(0, 0x1d, 2), 0xca, 0x1);
pci_write_config32(PCI_DEV(0, 0x1d, 3), 0xca, 0x1);
RCBA32(0x3100) = 0x42210;
RCBA32(0x3108) = 0x10004321;
RCBA32(0x310c) = 0x00214321;
RCBA32(0x3110) = 0x1;
RCBA32(0x3140) = 0x01460132;
RCBA32(0x3142) = 0x02370146;
RCBA32(0x3144) = 0x32010237;
RCBA32(0x3146) = 0x01463201;
RCBA32(0x3148) = 0x146;
/* Set C0000-FFFFF to access RAM on both reads and writes */
pci_write_config8(D0F0, PAM0, 0x30);
pci_write_config8(D0F0, PAM1, 0x33);
pci_write_config8(D0F0, PAM2, 0x33);
pci_write_config8(D0F0, PAM3, 0x33);
pci_write_config8(D0F0, PAM4, 0x33);
pci_write_config8(D0F0, PAM5, 0x33);
pci_write_config8(D0F0, PAM6, 0x33);
pci_write_config32(D0F0, SKPAD, SKPAD_NORMAL_BOOT_MAGIC);
printk(BIOS_DEBUG, " done.\n");
}
static void init_dmi(void)
{
u32 reg32;
u16 reg16;
/* Assume IGD present */
/* Clear error status */
DMIBAR32(0x1c4) = 0xffffffff;
DMIBAR32(0x1d0) = 0xffffffff;
/* VC0: TC0 only */
DMIBAR8(DMIVC0RCTL) = 1;
DMIBAR8(0x4) = 1;
/* VC1: ID1, TC7 */
reg32 = (DMIBAR32(DMIVC1RCTL) & ~(7 << 24)) | (1 << 24);
reg32 = (reg32 & ~0xff) | 1 << 7;
/* VC1: enable */
reg32 |= 1 << 31;
reg32 = (reg32 & ~(0x7 << 17)) | (0x4 << 17);
DMIBAR32(DMIVC1RCTL) = reg32;
/* Set up VCs in southbridge RCBA */
RCBA8(0x3022) &= ~1;
reg32 = (0x5 << 28) | (1 << 6); /* PCIe x4 */
RCBA32(0x2020) = (RCBA32(0x2020) & ~((0xf << 28) | (0x7 << 6))) | reg32;
/* Assign VC1 id 1 */
RCBA32(0x20) = (RCBA32(0x20) & ~(0x7 << 24)) | (1 << 24);
/* Map TC7 to VC1 */
RCBA8(0x20) &= 1;
RCBA8(0x20) |= 1 << 7;
/* Map TC0 to VC0 */
RCBA8(0x14) &= 1;
/* Init DMI VC1 port arbitration table */
RCBA32(0x20) &= 0xfff1ffff;
RCBA32(0x20) |= 1 << 19;
RCBA32(0x30) = 0x0000000f;
RCBA32(0x34) = 0x000f0000;
RCBA32(0x38) = 0;
RCBA32(0x3c) = 0x000000f0;
RCBA32(0x40) = 0x0f000000;
RCBA32(0x44) = 0;
RCBA32(0x48) = 0x0000f000;
RCBA32(0x4c) = 0;
RCBA32(0x50) = 0x0000000f;
RCBA32(0x54) = 0x000f0000;
RCBA32(0x58) = 0;
RCBA32(0x5c) = 0x000000f0;
RCBA32(0x60) = 0x0f000000;
RCBA32(0x64) = 0;
RCBA32(0x68) = 0x0000f000;
RCBA32(0x6c) = 0;
RCBA32(0x20) |= 1 << 16;
/* Enable VC1 */
RCBA32(0x20) |= 1 << 31;
/* Wait for VC1 */
while ((RCBA8(0x26) & (1 << 1)) != 0);
/* Wait for table load */
while ((RCBA8(0x26) & (1 << 0)) != 0);
/* ASPM on DMI link */
RCBA16(0x1a8) &= ~0x3;
reg16 = RCBA16(0x1a8);
RCBA32(0x2010) = (RCBA32(0x2010) & ~(0x3 << 10)) | (1 << 10);
reg32 = RCBA32(0x2010);
/* Set up VC1 max time */
RCBA32(0x1c) = (RCBA32(0x1c) & ~0x7f0000) | 0x120000;
while ((DMIBAR32(0x26) & (1 << 1)) != 0);
printk(BIOS_DEBUG, "Done DMI setup\n");
/* ASPM on DMI */
DMIBAR32(0x200) &= ~(0x3 << 26);
DMIBAR16(0x210) = (DMIBAR16(0x210) & ~(0xff7)) | 0x101;
DMIBAR32(0x88) &= ~0x3;
DMIBAR32(0x88) |= 0x3;
reg16 = DMIBAR16(0x88);
}
static void rcba_config(void)
{
u32 reg32;
/*
* D31IP_TTIP THRT INTC -> PIRQC
* D31IP_SIP2 SATA2 NOINT
* D31IP_SMIP SMBUS INTC -> PIRQC
* D31IP_SIP SATA INTB -> PIRQD (MSI)
* D29IP_E1P EHCI1 INTA -> PIRQH
* D28IP_P8IP Slot? INTD -> PIRQD
* D28IP_P7IP PCIEx1 INTC -> PIRQC
* D28IP_P6IP 1394 INTB -> PIRQB (MSI)
* D28IP_P5IP GbEPHY INTA -> PIRQA
* D28IP_P4IP ETH2 INTD -> PIRQD (MSI)
* D28IP_P3IP ETH1 INTC -> PIRQC (MSI)
* D28IP_P2IP Slot? INTB -> PIRQB
* D28IP_P1IP Slot? INTA -> PIRQA
* D27IP_ZIP HDA INTA -> PIRQG (MSI)
* D26IP_E2P EHCI2 INTA -> PIRQA
* D25IP_LIP ETH0 INTA -> PIRQE (MSI)
* D22IP_KTIP MEI NOINT
* D22IP_IDERIP MEI NOINT
* D22IP_MEI2IP MEI NOINT
* D22IP_MEI1IP MEI NOINT
* D20IP_XHCIIP XHCI INTA -> PIRQA (MSI)
* GFX INTA -> PIRQA (MSI)
* PEGx16 INTA -> PIRQA
* INTB -> PIRQB
* INTC -> PIRQC
* INTD -> PIRQD
*/
/* Device interrupt pin register (board specific) */
RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
(INTC << D31IP_SMIP) | (INTB << D31IP_SIP);
RCBA32(D29IP) = (INTA << D29IP_E1P);
RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) |
(INTC << D28IP_P3IP) | (INTD << D28IP_P4IP) |
(INTA << D28IP_P5IP) | (INTB << D28IP_P6IP) |
(INTC << D28IP_P7IP) | (INTD << D28IP_P8IP);
RCBA32(D27IP) = (INTA << D27IP_ZIP);
RCBA32(D26IP) = (INTA << D26IP_E2P);
RCBA32(D25IP) = (INTA << D25IP_LIP);
RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
RCBA32(D20IP) = (INTA << D20IP_XHCIIP);
/* Device interrupt route registers */
DIR_ROUTE(D31IR, PIRQA, PIRQD, PIRQC, PIRQA);
DIR_ROUTE(D29IR, PIRQH, PIRQD, PIRQA, PIRQC);
DIR_ROUTE(D28IR, PIRQA, PIRQB, PIRQC, PIRQD);
DIR_ROUTE(D27IR, PIRQG, PIRQB, PIRQC, PIRQD);
DIR_ROUTE(D26IR, PIRQA, PIRQF, PIRQC, PIRQD);
DIR_ROUTE(D25IR, PIRQE, PIRQF, PIRQG, PIRQH);
DIR_ROUTE(D22IR, PIRQA, PIRQD, PIRQC, PIRQB);
DIR_ROUTE(D20IR, PIRQA, PIRQB, PIRQC, PIRQD);
/* Enable IOAPIC (generic) */
RCBA16(OIC) = 0x0100;
/* PCH BWG says to read back the IOAPIC enable register */
(void) RCBA16(OIC);
/* Disable unused devices (board specific) */
reg32 = RCBA32(FD);
reg32 |= PCH_DISABLE_ALWAYS;
/* Disable PCI bridge so MRC does not probe this bus */
reg32 |= PCH_DISABLE_P2P;
RCBA32(FD) = reg32;
}
