示例#1
0
static int gpio_store(void)
{
    // store gpio pinmux
    gpio[0] = RD_MEM_32(conf_gpio18);
    gpio[1] = RD_MEM_32(conf_gpio19);
    return 0;
}
示例#2
0
void invalidate(unsigned int address, unsigned int size)
{
	WR_MEM_32(L2_SCACHE_MTSTART, address);
	WR_MEM_32(L2_SCACHE_MTEND, address+size);
	WR_MEM_32(L2_SCACHE_MAINT, INVALIDATE);
	while(RD_MEM_32(L2_SCACHE_MTSTART) != 0);		// wait until L2 maintenance operation is finished
	WR_MEM_32(L1_SCACHE_MTSTART, address);
	WR_MEM_32(L1_SCACHE_MTEND, address+size);
	WR_MEM_32(L1_SCACHE_MAINT, INVALIDATE);
	while(RD_MEM_32(L1_SCACHE_MTSTART) != 0);		// wait until L1 maintenance operation is finished
}
示例#3
0
void clean(unsigned int address, unsigned int size)
{
	WR_MEM_32(L1_SCACHE_OCP, CLEANBUF);
	WR_MEM_32(L1_SCACHE_MTSTART, address);
	WR_MEM_32(L1_SCACHE_MTEND, address+size);
	WR_MEM_32(L1_SCACHE_MAINT, CLEAN);
	while(RD_MEM_32(L1_SCACHE_MTSTART) != 0);		// wait until L1 maintenance operation is finished
	WR_MEM_32(L2_SCACHE_OCP, CLEANBUF);
	WR_MEM_32(L2_SCACHE_MTSTART, address);
	WR_MEM_32(L2_SCACHE_MTEND, address+size);
	WR_MEM_32(L2_SCACHE_MAINT, CLEAN);
	while(RD_MEM_32(L2_SCACHE_MTSTART) != 0);		// wait until L2 maintenance operation is finished
}
示例#4
0
void start_Timer(void)
{
	// enable timer interrupt
	WR_MEM_32(SYS_INTC_EVTMASK0, 0xFFFFFFFF);		// disable event combiner
	WR_MEM_32(SYS_INTC_EVTMASK1, 0xFFFFFFFF);
	WR_MEM_32(SYS_INTC_EVTMASK2, 0xFFFFFFFF);
	WR_MEM_32(SYS_INTC_EVTMASK3, 0xFFFFFFFF);

	WR_MEM_32(SYS_INTC_INTXCLR, 1);					// clear interrupt exception status register
	WR_MEM_32(SYS_INTC_INTDMASK, 0x0000FFF0);		// disable dropped event detection for all interrupts

													// DSP INT[4] is used to handle timer interrupt
	WR_MEM_32(SYS_INTC_INTMUX1, (RD_MEM_32(SYS_INTC_INTMUX1) & 0xFFFFFF00) | SCTM_TIMEVT1_INTR);
	ICR = (1<<4);									// clear any pending INT[4] interrupt
	IER |= (1<<4) | (1<<1);							// enable INT[4] and NMI
	CSR |= 1;										// GIE = 1, global interrupt enable

	// configure and start timer
	WR_MEM_32(SCACHE_SCTM_CTCNTL, RD_MEM_32(SCACHE_SCTM_CTCNTL) | ENBL);	// enable SCTM module
	WR_MEM_32(SCACHE_SCTM_CTCR_WT, RESET);									// reset timer
	WR_MEM_32(SCACHE_SCTM_TINTVLR, DSP_FREQ/1000);							// set interrupt period to 1ms
	WR_MEM_32(SCACHE_SCTM_CTCR_WT, ENBL | INT | RESTART);					// start timer in repeat mode
}