static int
nfs4_xdr_enc_cb_recall(struct rpc_rqst *req, __be32 *p, struct nfs4_cb_recall *args)
{
struct xdr_stream xdr;
struct nfs4_cb_compound_hdr hdr = {
.ident = args->cbr_ident,
.nops = 1,
};
xdr_init_encode(&xdr, &req->rq_snd_buf, p);
encode_cb_compound_hdr(&xdr, &hdr);
return (encode_cb_recall(&xdr, args));
}
static int
decode_cb_compound_hdr(struct xdr_stream *xdr, struct nfs4_cb_compound_hdr *hdr){
__be32 *p;
READ_BUF(8);
READ32(hdr->status);
READ32(hdr->taglen);
READ_BUF(hdr->taglen + 4);
hdr->tag = (char *)p;
p += XDR_QUADLEN(hdr->taglen);
READ32(hdr->nops);
return 0;
}
static int
nfs4_xdr_enc_cb_recall(struct rpc_rqst *req, __be32 *p,
struct nfs4_rpc_args *rpc_args)
{
struct xdr_stream xdr;
struct nfs4_delegation *args = rpc_args->args_op;
struct nfs4_cb_compound_hdr hdr = {
.ident = args->dl_ident,
.minorversion = rpc_args->args_seq.cbs_minorversion,
};
xdr_init_encode(&xdr, &req->rq_snd_buf, p);
encode_cb_compound_hdr(&xdr, &hdr);
encode_cb_sequence(&xdr, &rpc_args->args_seq, &hdr);
encode_cb_recall(&xdr, args, &hdr);
encode_cb_nops(&hdr);
return 0;
}
static int
decode_cb_compound_hdr(struct xdr_stream *xdr, struct nfs4_cb_compound_hdr *hdr){
__be32 *p;
READ_BUF(8);
READ32(hdr->status);
READ32(hdr->taglen);
READ_BUF(hdr->taglen + 4);
hdr->tag = (char *)p;
p += XDR_QUADLEN(hdr->taglen);
READ32(hdr->nops);
return 0;
}
static void _hsmci_reset(SIM_HBA *hba)
{
SIM_MMC_EXT *ext;
hsmci_ext_t *hsmci;
uintptr_t base;
ext = (SIM_MMC_EXT *)hba->ext;
hsmci = (hsmci_ext_t *)ext->handle;
base = hsmci->base;
int dtor = READ32(MCI_DTOR);
int mr = READ32(MCI_MR);
int sdcr = READ32(MCI_SDCR);
/* Reset and disable controller */
WRITE32 (MCI_CR, SWRST|PWSDIS);
delay (100);
WRITE32 (MCI_CR, MCIDIS | PWSDIS | MCIEN);
WRITE32(MCI_DMA, (READ32(MCI_DMA) & (~(DMAEN))));
WRITE32 (MCI_IDR, 0xffffffff);
WRITE32(MCI_DTOR, dtor);
WRITE32(MCI_MR, mr);
WRITE32(MCI_SDCR, sdcr);
}
void
evgEvtClk::setFracSynFreq(epicsFloat64 freq) {
epicsUInt32 controlWord, oldControlWord;
epicsFloat64 error;
controlWord = FracSynthControlWord (freq, MRF_FRAC_SYNTH_REF, 0, &error);
if ((!controlWord) || (error > 100.0)) {
char err[80];
sprintf(err, "Cannot set event clock speed to %f MHz.\n", freq);
std::string strErr(err);
throw std::runtime_error(strErr);
}
oldControlWord=READ32(m_pReg, FracSynthWord);
/* Changing the control word disturbes the phase of the synthesiser
which will cause a glitch. Don't change the control word unless needed.*/
if(controlWord != oldControlWord){
WRITE32(m_pReg, FracSynthWord, controlWord);
epicsUInt32 uSecDivider = (epicsUInt16)freq;
WRITE32(m_pReg, uSecDiv, uSecDivider);
}
m_fracSynFreq = FracSynthAnalyze(READ32(m_pReg, FracSynthWord), 24.0, 0);
}
/*
* The real PIO transfer.
* Note:
* We only use PIO to read SCR and check/switch high speed mode, so only read operation is possible
*/
static int _hsmci_pio_done(SIM_HBA *hba, char *buf, int len, int dir)
{
SIM_MMC_EXT *ext;
hsmci_ext_t *hsmci;
uintptr_t base;
int i;
int timeout = TIMEOUT_LOOPS;
uint32_t *buf32 = (uint32_t *) buf;
ext = (SIM_MMC_EXT *)hba->ext;
hsmci = (hsmci_ext_t *)ext->handle;
base = hsmci->base;
// Make sure the data is ready
while (!(READ32(MCI_SR) & RXRDY) && timeout--);
if (dir == DATA_READ) {
for (i = 0; i < len; i+=4) {
*buf32++ = READ32(MCI_RDR);
delay(5);
}
} else {
slogf (_SLOGC_SIM_MMC, _SLOG_ERROR, "%s: We only support PIO read\n", __func__);
return -1;
}
clearFIFO (hba);
return len;
}
static int
nfs4_xdr_enc_cb_recall(struct rpc_rqst *req, __be32 *p,
struct nfsd4_callback *cb)
{
struct xdr_stream xdr;
struct nfs4_delegation *args = cb->cb_op;
struct nfs4_cb_compound_hdr hdr = {
.ident = cb->cb_clp->cl_cb_ident,
.minorversion = cb->cb_minorversion,
};
xdr_init_encode(&xdr, &req->rq_snd_buf, p);
encode_cb_compound_hdr(&xdr, &hdr);
encode_cb_sequence(&xdr, cb, &hdr);
encode_cb_recall(&xdr, args, &hdr);
encode_cb_nops(&hdr);
return 0;
}
static int
decode_cb_compound_hdr(struct xdr_stream *xdr, struct nfs4_cb_compound_hdr *hdr){
__be32 *p;
u32 taglen;
READ_BUF(8);
READ32(hdr->status);
/* We've got no use for the tag; ignore it: */
READ32(taglen);
READ_BUF(taglen + 4);
p += XDR_QUADLEN(taglen);
READ32(hdr->nops);
return 0;
}
int NormalIMBase::readHeader(const unsigned char *buf)
{
int pos=0;
senderVersion = READ16(buf+pos);
pos+=2;
sender = READ32(buf+pos);
pos+=4;
receiver = READ32(buf+pos);
pos+=4;
memcpy(fileSessionKey, buf+pos, 16);
pos+=16;
type = READ16(buf+pos);
pos+=2;
sequence = READ16(buf+pos);
pos+=2;
sendTime = READ32(buf+pos);
pos+=4;
senderFace = READ16(buf+pos);
pos+=2;
return pos;
}
SeqRunMode
evgSeqRam::getRunMode() const {
if(READ32(m_pReg, SeqControl(m_id)) & EVG_SEQ_RAM_SINGLE)
return Single;
if(READ32(m_pReg, SeqControl(m_id)) & EVG_SEQ_RAM_RECYCLE)
return Auto;
else
return Normal;
}
/*
* @brief Output a character to serial port
*
* @param dev UART device struct
* @param c character to output
*/
unsigned char uart_gnss_poll_out(struct device *dev, unsigned char c)
{
/* wait for transmitter to ready to accept a character */
uint32_t status = READ32(&__UART1->status);
while (status & UART_STATUS_TX_FULL) {
status = READ32(&__UART1->status);
}
WRITE32(&__UART1->data, c);
return c;
}
/**
* @brief Read data from FIFO
*
* @param dev UART device struct
* @param rx_data Pointer to data container
* @param size Container size
*
* @return Number of bytes read
*/
static int uart_gnss_fifo_read(struct device *dev, uint8_t *rx_data,
const int size)
{
uint32_t status = READ32(&__UART1->status);
uint8_t num_rx = 0;
while ((size - num_rx > 0) && ((status & UART_STATUS_RX_EMPTY) == 0)) {
rx_data[num_rx++] = (uint8_t)READ32(&__UART1->data);
status = READ32(&__UART1->status);
}
return num_rx;
}
int create_RTcore_taskConfig( ST_STD_device *pSTDdev)
{
ST_RTcore* pRTcore;
unsigned int nval=0;
int status;
pRTcore = (ST_RTcore *)malloc(sizeof(ST_RTcore));
if( !pRTcore) return WR_ERROR;
pSTDdev->pUser = pRTcore;
pRTcore->fd_event = open("/dev/intLTU.0", O_RDWR|O_NDELAY);
if (pRTcore->fd_event < 0)
{
fprintf(stdout, "intLTU device open error !!!!!!\n");
return WR_ERROR;
}
pRTcore->base0 = (char *)mmap(0, 0x1000, PROT_READ|PROT_WRITE, MAP_SHARED, pRTcore->fd_event, 0);
if( pRTcore->base0 == 0x0) {
perror("mmap() error!");
close( pRTcore->fd_event );
return WR_ERROR;
}
status = ioctl(pRTcore->fd_event, IOCTL_CLTU_INTERRUPT_ENABLE, &nval);
nval = READ32(pRTcore->base0 + 0x0);
printf("0x0: 0x%x\n", (nval));
nval = READ32(pRTcore->base0 + 0x4);
printf("0x4: 0x%x\n", (nval));
nval = READ32(pRTcore->base0 + 0x8);
printf("0x8: 0x%x\n", (nval));
nval = READ32(pRTcore->base0 + 0xc);
printf("0xc: 0x%x\n", (nval));
// pRTcore->cntDAQ = 0;
pRTcore->cntDAQ_loop = 0;
pRTcore->cntAccum = 0;
/* pRTcore->daqStepTime = 0.00001; */
pRTcore->useScanIoRequest = 0;
/* pRTcore->clkStartTime = -15.0; */
return WR_OK;
}
epicsUInt32
EvrCML::countHigh() const
{
epicsUInt32 val = READ32(base, OutputCMLCount(N));
val >>= OutputCMLCount_high_shft;
return val & OutputCMLCount_mask;
}
void i386_device::i486_cmpxchg_rm32_r32() // Opcode 0x0f b1
{
UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
UINT32 dst = LOAD_RM32(modrm);
UINT32 src = LOAD_REG32(modrm);
if( REG32(EAX) == dst ) {
STORE_RM32(modrm, src);
m_ZF = 1;
CYCLES(CYCLES_CMPXCHG_REG_REG_T);
} else {
REG32(EAX) = dst;
m_ZF = 0;
CYCLES(CYCLES_CMPXCHG_REG_REG_F);
}
} else {
UINT32 ea = GetEA(modrm,0);
UINT32 dst = READ32(ea);
UINT32 src = LOAD_REG32(modrm);
if( REG32(EAX) == dst ) {
WRITE32(ea, src);
m_ZF = 1;
CYCLES(CYCLES_CMPXCHG_REG_MEM_T);
} else {
REG32(EAX) = dst;
m_ZF = 0;
CYCLES(CYCLES_CMPXCHG_REG_MEM_F);
}
}
}
epicsUInt32
MRMCML::countLow () const
{
epicsUInt32 val = READ32(base, OutputCMLCount(N));
val >>= OutputCMLCount_low_shft;
return val & OutputCMLCount_mask;
}
static void I486OP(cmpxchg_rm32_r32)(i386_state *cpustate) // Opcode 0x0f b1
{
UINT8 modrm = FETCH(cpustate);
if( modrm >= 0xc0 ) {
UINT32 dst = LOAD_RM32(modrm);
UINT32 src = LOAD_REG32(modrm);
if( REG32(EAX) == dst ) {
STORE_RM32(modrm, src);
cpustate->ZF = 1;
CYCLES(cpustate,CYCLES_CMPXCHG_REG_REG_T);
} else {
REG32(EAX) = dst;
cpustate->ZF = 0;
CYCLES(cpustate,CYCLES_CMPXCHG_REG_REG_F);
}
} else {
UINT32 ea = GetEA(cpustate,modrm);
UINT32 dst = READ32(cpustate,ea);
UINT32 src = LOAD_REG32(modrm);
if( REG32(EAX) == dst ) {
WRITE32(cpustate,ea, src);
cpustate->ZF = 1;
CYCLES(cpustate,CYCLES_CMPXCHG_REG_MEM_T);
} else {
REG32(EAX) = dst;
cpustate->ZF = 0;
CYCLES(cpustate,CYCLES_CMPXCHG_REG_MEM_F);
}
}
}
static int _hsmci_wait_stat (SIM_HBA *hba, mmc_cmd_t *cmd)
{
SIM_MMC_EXT *ext;
hsmci_ext_t *hsmci;
uintptr_t base;
uint32_t mask = CMDRDY;
ext = (SIM_MMC_EXT *)hba->ext;
hsmci = (hsmci_ext_t *)ext->handle;
base = hsmci->base;
if (cmd->eflags & MMC_CMD_DATA) {
mask |= NOTBUSY | XFRDONE;
}
int timeout = TIMEOUT_LOOPS/100;
while (((READ32(MCI_SR) & mask) != mask) && timeout--)
nanospin_ns(100);
if (timeout <= 0) {
slogf (_SLOGC_SIM_MMC, _SLOG_ERROR, "MMC: timeout on waiting for MCI_SR: 0x%x for CMD%d, mask: 0x%x", READ32(MCI_SR), cmd->opcode, mask);
return MMC_FAILURE;
}
return MMC_SUCCESS;
}
void SignatureChangedPacket::parseData( const unsigned char * buf, const int /*len*/ )
{
int pos=0;
qq = READ32(buf); pos+=4; // your buddy qq number
time = READ32(buf+pos); pos+=4; // the time he/she changed his/her signature
unsigned char tmp = buf[pos++]; // the length of signature
char *str = new char[tmp+1];
memcpy(str, buf+pos, tmp); // we get the new signature
str[tmp] = 0x00;
signature.assign(str);
delete []str;
}
MRMCML::MRMCML(const std::string& n, unsigned char i,EVRMRM& o, outkind k, formFactor f)
:CML(n)
,mult(f==formFactor_CPCIFULL ? 40 : 20) // CML word length
,wordlen(f==formFactor_CPCIFULL ? 2 : 1)// # of 32-bit dwords used to store 1 CML word
// 40 bits fit in 2 dwords, 20 bits fit in 1
,base(o.base)
,N(i)
,owner(o)
,shadowEnable(0)
,shadowWaveformlength(0)
,kind(k)
{
epicsUInt32 val=READ32(base, OutputCMLEna(N));
val&=~OutputCMLEna_type_mask;
switch(kind) {
case typeCML: break;
case typeTG203: val|=OutputCMLEna_type_203; break;
case typeTG300: val|=OutputCMLEna_type_300; break;
default:
throw std::invalid_argument("Invalid CML kind");
}
for(size_t i=0; i<NELEMENTS(shadowPattern); i++) {
epicsUInt32 L = wordlen * (lenPatternMax((pattern)i)/mult);
shadowPattern[i] = new epicsUInt32[L];
std::fill(shadowPattern[i], shadowPattern[i]+L, 0);
}
shadowEnable=val;
}
epicsUInt32 checkVersion(volatile epicsUInt8 *base, unsigned int required) {
#ifndef __linux__
epicsUInt32 junk;
if(devReadProbe(sizeof(junk), (volatile void*)(base+U32_FWVersion), (void*)&junk)) {
throw std::runtime_error("Failed to read from MRM registers (but could read CSR registers)\n");
}
#endif
epicsUInt32 type, ver;
epicsUInt32 v = READ32(base, FWVersion);
epicsPrintf("FPGA version: %08x\n", v);
type = v >> FWVersion_type_shift;
if(type != 0x2){
errlogPrintf("Found type %x which does not correspond to EVG type 0x2.\n", type);
return 0;
}
ver = v & FWVersion_ver_mask;
if(ver < required) {
errlogPrintf("Firmware version >= %x is required got %x\n", required,ver);
return 0;
}
return ver;
}
bool
evgMxc::getTrigEvtMap(epicsUInt16 trigEvt) const {
if(trigEvt > 7)
throw std::runtime_error("EVG Mxc Trig Event ID too large. Max: 7");
epicsUInt32 mask = 1 << (trigEvt+MuxControl_TrigMap_SHIFT);
return READ32(m_pReg, MuxControl(m_id))&mask;
}
/*
* Our current back channel implmentation supports a single backchannel
* with a single slot.
*/
static int
decode_cb_sequence(struct xdr_stream *xdr, struct nfsd4_callback *cb,
struct rpc_rqst *rqstp)
{
struct nfsd4_session *ses = cb->cb_clp->cl_cb_session;
struct nfs4_sessionid id;
int status;
u32 dummy;
__be32 *p;
if (cb->cb_minorversion == 0)
return 0;
status = decode_cb_op_hdr(xdr, OP_CB_SEQUENCE);
if (status)
return status;
/*
* If the server returns different values for sessionID, slotID or
* sequence number, the server is looney tunes.
*/
status = -ESERVERFAULT;
READ_BUF(NFS4_MAX_SESSIONID_LEN + 16);
memcpy(id.data, p, NFS4_MAX_SESSIONID_LEN);
p += XDR_QUADLEN(NFS4_MAX_SESSIONID_LEN);
if (memcmp(id.data, ses->se_sessionid.data, NFS4_MAX_SESSIONID_LEN)) {
dprintk("%s Invalid session id\n", __func__);
goto out;
}
READ32(dummy);
if (dummy != ses->se_cb_seq_nr) {
dprintk("%s Invalid sequence number\n", __func__);
goto out;
}
READ32(dummy); /* slotid must be 0 */
if (dummy != 0) {
dprintk("%s Invalid slotid\n", __func__);
goto out;
}
/* FIXME: process highest slotid and target highest slotid */
status = 0;
out:
return status;
}
void
evgMrm::isr(void* arg) {
evgMrm *evg = (evgMrm*)(arg);
epicsUInt32 flags = READ32(evg->m_pReg, IrqFlag);
epicsUInt32 enable = READ32(evg->m_pReg, IrqEnable);
epicsUInt32 active = flags & enable;
if(!active)
return;
if(active & EVG_IRQ_STOP_RAM(0)) {
if(evg->irqStop0_queued==0) {
callbackRequest(&evg->irqStop0_cb);
evg->irqStop0_queued=1;
} else if(evg->irqStop0_queued==1) {
WRITE32(evg->getRegAddr(), IrqEnable, enable & ~EVG_IRQ_STOP_RAM(0));
evg->irqStop0_queued=2;
}
}
if(active & EVG_IRQ_STOP_RAM(1)) {
if(evg->irqStop1_queued==0) {
callbackRequest(&evg->irqStop1_cb);
evg->irqStop1_queued=1;
} else if(evg->irqStop1_queued==1) {
WRITE32(evg->getRegAddr(), IrqEnable, enable & ~EVG_IRQ_STOP_RAM(1));
evg->irqStop1_queued=2;
}
}
if(active & EVG_IRQ_EXT_INP) {
if(evg->irqExtInp_queued==0) {
callbackRequest(&evg->irqExtInp_cb);
evg->irqExtInp_queued=1;
} else if(evg->irqExtInp_queued==1) {
WRITE32(evg->getRegAddr(), IrqEnable, enable & ~EVG_IRQ_EXT_INP);
evg->irqExtInp_queued=2;
}
}
WRITE32(evg->m_pReg, IrqFlag, flags); // Clear the interrupt causes
READ32(evg->m_pReg, IrqFlag); // Make sure the clear completes before returning
return;
}
std::vector<epicsUInt64>
evgSeqRam::getTimestamp() {
std::vector<epicsUInt64> timestamp(2048, 0);
for(unsigned int i = 0; i < timestamp.size(); i++)
timestamp[i] = READ32(m_pReg, SeqRamTS(m_id,i));
return timestamp;
}
epicsUInt32
EvrInput::backEvt() const
{
epicsUInt32 val;
val = READ32(base, InputMapFP(idx) );
val &= InputMapFP_back_mask;
val >>= InputMapFP_back_shft;
return val;
}
epicsUInt16
EvrInput::dbus() const
{
epicsUInt32 val;
val = READ32(base, InputMapFP(idx) );
val &= InputMapFP_dbus_mask;
val >>= InputMapFP_dbus_shft;
return val;
}
double
MRMCML::fineDelay() const
{
// The GTX output fine delay is an external chip
// and not related to the clock frequency.
// So just scale it to [0, 1) and use ESLO for the
// actual calibration
return READ32(base, GTXDelay(N))/1024.0;
}
void
evgEvtClk::setSource (epicsUInt16 source) {
epicsUInt8 clkReg, regMap = 0;
epicsUInt32 version;
version = READ32(m_pReg, FWVersion);
version &= FWVersion_ver_mask;
if ((RFClockReference) source >= RFClockReference_PXIe100 && version < EVG_FCT_MIN_FIRMWARE ) {
throw std::out_of_range("RF clock source you selected does not exist in this firmware version.");
}
else if ((RFClockReference) source >= RFClockReference_ExtDownrate && version < EVG_MIN_FIRMWARE_REDUCECLK ) {
throw std::out_of_range("RF clock source you selected does not exist in this firmware version.");
}
switch ((RFClockReference) source) {
case RFClockReference_Internal:
regMap = EVG_CLK_SRC_INTERNAL;
break;
case RFClockReference_External:
regMap = EVG_CLK_SRC_EXTERNAL;
break;
case RFClockReference_PXIe100:
regMap = EVG_CLK_SRC_PXIE100;
break;
case RFClockReference_PXIe10:
regMap = EVG_CLK_SRC_PXIE10;
break;
case RFClockReference_Recovered:
regMap = EVG_CLK_SRC_RECOVERED;
break;
case RFClockReference_ExtDownrate:
regMap = EVG_CLK_SRC_EXTDOWNRATE;
break;
case RFClockReference_RecoverHalved:
regMap = EVG_CLK_SRC_RECOVERHALVED;
break;
default:
throw std::out_of_range("RF clock source you selected does not exist.");
break;
}
clkReg = READ8(m_pReg, ClockSource); // read register content
clkReg &= ~EVG_CLK_SRC_SEL; // clear old clock source
clkReg |= regMap; // set new clock source
WRITE8(m_pReg, ClockSource, clkReg); // write the new value to the register
}
void
MRMCML::setCountLow (epicsUInt32 v)
{
v = std::max(kind==typeTG300?40u:20u, std::min(v, 65535u));
epicsUInt32 val = READ32(base, OutputCMLCount(N));
val &= ~(OutputCMLCount_mask << OutputCMLCount_low_shft);
val |= v << OutputCMLCount_low_shft;
WRITE32(base, OutputCMLCount(N), val);
}
unsigned arm_dasm(char *buffer, unsigned int pc)
{
#ifdef MAME_DEBUG
arm_disasm( buffer, pc, cpu_read32(pc&ADDRESS_MASK) );
return 4;
#else
sprintf(buffer, "$%08x", READ32(pc));
return 4;
#endif
}
void clearFIFO (SIM_HBA *hba)
{
SIM_MMC_EXT *ext;
hsmci_ext_t *hsmci;
uintptr_t base;
int i;
int mcisr, mcififo;
ext = (SIM_MMC_EXT *)hba->ext;
hsmci = (hsmci_ext_t *)ext->handle;
base = hsmci->base;
/* Keep read the FIFO until the FIFO is empty */
for (i=0;i<256;i++) {
mcisr = READ32(MCI_SR);
mcififo = READ32(MCI_FIFO);
if (mcisr & FIFOEMPTY) break;
}
}
