static int mercury_cfg_read(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 *data)
{
struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));
u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start;
u32 tok = LBA_CFG_TOK(local_bus, devfn);
void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
if ((pos > 255) || (devfn > 255))
return -EINVAL;
LBA_CFG_TR4_ADDR_SETUP(d, tok | pos);
switch(size) {
case 1:
*data = READ_REG8(data_reg + (pos & 3));
break;
case 2:
*data = READ_REG16(data_reg + (pos & 2));
break;
case 4:
*data = READ_REG32(data_reg); break;
break;
}
DBG_CFG("mercury_cfg_read(%x+%2x) -> 0x%x\n", tok, pos, *data);
return 0;
}
static unsigned int
lba_rd_cfg(struct lba_device *d, u32 tok, u8 reg, u32 size)
{
u32 data = ~0U;
int error = 0;
u32 arb_mask = 0; /* used by LBA_CFG_SETUP/RESTORE */
u32 error_config = 0; /* used by LBA_CFG_SETUP/RESTORE */
u32 status_control = 0; /* used by LBA_CFG_SETUP/RESTORE */
LBA_CFG_SETUP(d, tok);
LBA_CFG_PROBE(d, tok);
LBA_CFG_MASTER_ABORT_CHECK(d, d->hba.base_addr, tok, error);
if (!error) {
void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
LBA_CFG_ADDR_SETUP(d, tok | reg);
switch (size) {
case 1: data = (u32) READ_REG8(data_reg + (reg & 3)); break;
case 2: data = (u32) READ_REG16(data_reg+ (reg & 2)); break;
case 4: data = READ_REG32(data_reg); break;
}
}
LBA_CFG_RESTORE(d, d->hba.base_addr);
return(data);
}
static int hc_isp_suspend(struct device * dev, u32 state, u32 level)
{
switch(level)
{
case SUSPEND_POWER_DOWN:
WRITE_REG16 (pm_hci, 0, HcDMAConfiguration);
WRITE_REG16 (pm_hci, 0, HcuPInterruptEnable);
WRITE_REG16(pm_hci, READ_REG16(pm_hci, HcHardwareConfiguration) &
~InterruptPinEnable, HcHardwareConfiguration);
hc_release_hci(pm_hci);
break;
}
return 0;
}
// Read the FIFO for the endpoint indexed by Endpoint, into the buffer pointed
// at by Buffer, whose size is *Size bytes.
//
// If *Size is less than the number of bytes in the FIFO, return EFI_BUFFER_TOO_SMALL
//
// Update *Size with the number of bytes of data in the FIFO.
STATIC
EFI_STATUS
ReadEndpointBuffer (
IN UINT8 Endpoint,
IN OUT UINTN *Size,
IN OUT VOID *Buffer
)
{
UINT16 NumBytesAvailable;
UINT32 Val32;
UINTN Index;
UINTN NumBytesRead;
SelectEndpoint (Endpoint);
NumBytesAvailable = READ_REG16 (ISP1761_BUFFER_LENGTH);
if (NumBytesAvailable > *Size) {
*Size = NumBytesAvailable;
return EFI_BUFFER_TOO_SMALL;
}
*Size = NumBytesAvailable;
/* -- NB! --
The datasheet says the Data Port is 16 bits but it actually appears to
be 32 bits.
*/
// Read 32-bit chunks
for (Index = 0; Index < NumBytesAvailable / 4; Index++) {
((UINT32 *) Buffer)[Index] = READ_REG32 (ISP1761_DATA_PORT);
}
// Read remaining bytes
// Round NumBytesAvailable down to nearest power of 4
NumBytesRead = NumBytesAvailable & (~0x3);
if (NumBytesRead != NumBytesAvailable) {
Val32 = READ_REG32 (ISP1761_DATA_PORT);
// Copy each required byte of 32-bit word into buffer
for (Index = 0; Index < NumBytesAvailable % 4; Index++) {
((UINT8 *) Buffer)[NumBytesRead + Index] = Val32 >> (Index * 8);
}
}
static int elroy_cfg_read(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 *data)
{
struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));
u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start;
u32 tok = LBA_CFG_TOK(local_bus, devfn);
void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
if ((pos > 255) || (devfn > 255))
return -EINVAL;
/* FIXME: B2K/C3600 workaround is always use old method... */
/* if (!LBA_SKIP_PROBE(d)) */ {
/* original - Generate config cycle on broken elroy
with risk we will miss PCI bus errors. */
*data = lba_rd_cfg(d, tok, pos, size);
DBG_CFG("%s(%x+%2x) -> 0x%x (a)\n", __func__, tok, pos, *data);
return 0;
}
if (LBA_SKIP_PROBE(d) && !lba_device_present(bus->busn_res.start, devfn, d)) {
DBG_CFG("%s(%x+%2x) -> -1 (b)\n", __func__, tok, pos);
/* either don't want to look or know device isn't present. */
*data = ~0U;
return(0);
}
/* Basic Algorithm
** Should only get here on fully working LBA rev.
** This is how simple the code should have been.
*/
LBA_CFG_ADDR_SETUP(d, tok | pos);
switch(size) {
case 1: *data = READ_REG8 (data_reg + (pos & 3)); break;
case 2: *data = READ_REG16(data_reg + (pos & 2)); break;
case 4: *data = READ_REG32(data_reg); break;
}
DBG_CFG("%s(%x+%2x) -> 0x%x (c)\n", __func__, tok, pos, *data);
return 0;
}
static void hc_isp116x_intregdump(hci_t * hci)
{
printk("HcInterruptStatus=%x HcInterruptEnable=%x\n", READ_REG32 (hci, HcInterruptStatus), READ_REG32 (hci, HcInterruptEnable));
printk("HcuPInterrupt=%x HcuPInterruptEnable=%x\n", READ_REG16 (hci, HcuPInterrupt), READ_REG16 (hci, HcuPInterruptEnable));
printk("HcHardwareConfiguration=%x\n", READ_REG16 (hci,HcHardwareConfiguration));
}
