/*!
*
* @param mmio
*
* @return void
*/
static void disable_vga_plb (unsigned char *mmio)
{
unsigned long temp;
unsigned char sr01;
EMGD_TRACE_ENTER;
/* Disable VGA plane if it is enabled. */
temp = EMGD_READ32(EMGD_MMIO(mmio) + VGACNTRL);
if ((temp & BIT31) == 0) {
/* Read SR01 */
READ_VGA(mmio, SR_PORT, 0x01, sr01);
/* Turn on SR01 bit 5 */
WRITE_VGA(mmio, SR_PORT, 0x01, sr01|BIT(5));
/* Wait for 30us */
OS_SLEEP(30);
temp |= BIT31; /* set bit 31 to disable */
temp &= ~BIT30; /* clear bit 30 to get VGA display in normal size */
EMGD_WRITE32(temp, EMGD_MMIO(mmio) + VGACNTRL);
}
/*
* When turing off the VGA plane the palette sometimes gets stuck.
* if we do a couple reads to the palette it will unstuck.
*/
if((1L<<31) & EMGD_READ32( EMGD_MMIO(mmio) + PIPEA_CONF )) {
EMGD_DEBUG("VGA Palette workaround");
EMGD_READ32(EMGD_MMIO(mmio) + DPALETTE_A);
EMGD_READ32(EMGD_MMIO(mmio) + DPALETTE_A);
}
if((1L<<31) & EMGD_READ32( EMGD_MMIO(mmio) + PIPEB_CONF )) {
EMGD_DEBUG("VGA Palette workaround");
EMGD_READ32(EMGD_MMIO(mmio) + DPALETTE_B);
EMGD_READ32(EMGD_MMIO(mmio) + DPALETTE_B);
}
EMGD_TRACE_EXIT;
}
/*!
* Saves the current VGA register state of the video chipset into the
* given state buffer.
*
* This function first saves the 4 plane latches, and then it saves
* the SR, GR, AR, CR registers.
*
* @param context the current device context
* @param vga_buffer this is where the VGA register state is saved
* @param ar_regs AR registers to save
* @param cr_regs CR registers to save
* @param sr_regs SR registers to save
* @param gr_regs GR registers to save
*
* @return 0
*/
static int reg_save_vga_plb(
igd_context_t *context,
vga_state_plb_t *vga_buffer,
unsigned char *ar_regs,
unsigned char *cr_regs,
unsigned char *sr_regs,
unsigned char *gr_regs)
{
unsigned char *mmio;
int i;
mmio = context->device_context.virt_mmadr;
/* First, save a few registers that will be modified to read the latches.
* We need to use GR04 to go through all the latches. Therefore, we must
* first save GR04 before continuing. However, GR04 will only behave the
* way we want it to if we are not in Odd/Even mode and not in Chain 4
* mode. Therefore, we have to make sure GR05 (GFX mode reg),
* and SR04 (Mem Mode reg) are set properly.
* According to B-spec, we are not supposed to program GR06 via MMIO.
*/
READ_VGA(mmio, GR_PORT, GR04, vga_buffer->gr[0x04]);
READ_VGA(mmio, SR_PORT, SR04, vga_buffer->sr[0x04]); /* Memory Mode */
READ_VGA(mmio, GR_PORT, GR05, vga_buffer->gr[0x05]); /* GFX Mode Reg */
READ_VGA(mmio, GR_PORT, GR06, vga_buffer->gr[0x06]); /* Misc Reg */
WRITE_VGA(mmio, SR_PORT, SR04, 0x06);
WRITE_VGA(mmio, GR_PORT, GR05, 0x00);
WRITE_VGA(mmio, GR_PORT, GR06, 0x05);
/* Save Memory Latch Data latches */
for (i=0; i<PLANE_LATCH_COUNT; i++) {
WRITE_VGA(mmio, GR_PORT, GR04, (unsigned char)i);
READ_VGA(mmio, CR_PORT, CR22, vga_buffer->plane_latches[i]);
}
/* Restore the modified regs */
WRITE_VGA(mmio, GR_PORT, GR06, vga_buffer->gr[0x06]);
WRITE_VGA(mmio, GR_PORT, GR05, vga_buffer->gr[0x05]);
WRITE_VGA(mmio, GR_PORT, GR04, vga_buffer->gr[0x04]);
WRITE_VGA(mmio, SR_PORT, SR04, vga_buffer->sr[0x04]);
/* Save Feature Controller register. */
vga_buffer->fcr = EMGD_READ8(mmio + FEATURE_CONT_REG_READ);
/* Save Miscellaneous Output Register. */
vga_buffer->msr = EMGD_READ8(mmio + MSR_READ_PORT);
/* Save index registers. */
vga_buffer->sr_index = EMGD_READ8(mmio + SR_PORT);
vga_buffer->cr_index = EMGD_READ8(mmio + CR_PORT);
vga_buffer->gr_index = EMGD_READ8(mmio + GR_PORT);
#if 0
/*
* Save the AR index register and last write status. Not sure that
* this is really necessary so skip it for now.
*/
READ_VGA(mmio, CR_PORT, CR24, isARData); // Next write to AR index reg
isARData &= 0x80;
// Save AR index and last write status
vga_buffer->ar_index = EMGD_READ8(mmio + AR_PORT) | isARData;
#endif
/* Save CRT Controller registers. */
for (i=0; cr_regs[i] != 0xff; i++) {
READ_VGA(mmio, CR_PORT, cr_regs[i], vga_buffer->cr[i]);
}
/* Save Attribute Controller registers. */
for (i=0; ar_regs[i] != 0xff; i++) {
READ_AR(mmio, (unsigned char)i, vga_buffer->ar[i]);
}
/* Save Graphics Controller registers. */
for (i=0; gr_regs[i] != 0xff; i++) {
READ_VGA(mmio, GR_PORT, gr_regs[i], vga_buffer->gr[i]);
}
/* Save Sequencer registers. */
for (i=0; sr_regs[i] != 0xff; i++) {
READ_VGA(mmio, SR_PORT, sr_regs[i], vga_buffer->sr[i]);
}
return 0;
}