void start_responder() { uint8_t int1,int2; if(resp) stop_responder(); REGW(si_inten1,0); REGW(si_inten2,0); REGW(si_pklen,2); REGW(si_mode02,si_ffclrrx|si_ffclrtx); REGW(si_mode02,0); REGR(si_interrupt1,int1); REGR(si_interrupt2,int2); #if HW_VER == 0 REGW(si_GPIO2,si_gpio2rxstate); #endif #if HW_VER == 1 REGW(si_GPIO0,si_gpio0rxstate); #endif REGW(si_fifo,0); REGW(si_fifo,0); TIFR=(1<<TICIE1); TIMSK|=(1<<TICIE1); REGW(si_mode01,si_rxon|si_pllon|si_xton); resp=1; TCCR1A=0; TCCR1B=(0<<ICES1)|1; }
void stop_responder() { TIMSK&=~(1<<TICIE1); resp=0; REGW(si_mode01,0); REGW(si_mode02,si_ffclrrx|si_ffclrtx); REGW(si_mode02,0); }
ISR(SIG_INPUT_CAPTURE1,ISR_NOBLOCK) { if(resp) { resp=2; REGW(si_mode01,si_txon|si_pllon|si_xton); uint8_t k; do{ REGR(si_mode01,k); }while(k&si_txon); REGW(si_mode01,si_rxon|si_pllon|si_xton); }else{ uint16_t de=ICR1-ilast; ilast=ICR1; if((de<imax)&&(de>=imin)) intbuf[iwp++]=de; } }
static void t11_set_info(UINT32 state, cpuinfo *info) { switch (state) { /* --- the following bits of info are set as 64-bit signed integers --- */ case CPUINFO_INT_INPUT_STATE + T11_IRQ0: set_irq_line(T11_IRQ0, info->i); break; case CPUINFO_INT_INPUT_STATE + T11_IRQ1: set_irq_line(T11_IRQ1, info->i); break; case CPUINFO_INT_INPUT_STATE + T11_IRQ2: set_irq_line(T11_IRQ2, info->i); break; case CPUINFO_INT_INPUT_STATE + T11_IRQ3: set_irq_line(T11_IRQ3, info->i); break; case CPUINFO_INT_PC: case CPUINFO_INT_REGISTER + T11_PC: PC = info->i; change_pc(PC); break; case CPUINFO_INT_SP: case CPUINFO_INT_REGISTER + T11_SP: SP = info->i; break; case CPUINFO_INT_REGISTER + T11_PSW: PSW = info->i; break; case CPUINFO_INT_REGISTER + T11_R0: REGW(0) = info->i; break; case CPUINFO_INT_REGISTER + T11_R1: REGW(1) = info->i; break; case CPUINFO_INT_REGISTER + T11_R2: REGW(2) = info->i; break; case CPUINFO_INT_REGISTER + T11_R3: REGW(3) = info->i; break; case CPUINFO_INT_REGISTER + T11_R4: REGW(4) = info->i; break; case CPUINFO_INT_REGISTER + T11_R5: REGW(5) = info->i; break; } }
void main(void) { uchar i; rxtxrx_state=0; SET_SDN(1); DDRD|=(1<<4)|(1<<5); PORTC=(1<<1)|(1<<2); DDRC=(1<<0)|(1<<1); usbDeviceDisconnect(); /* enforce re-enumeration, do this while interrupts are disabled! */ usbInit(); init_usart(); i = 0; SET_SDN(0); while(--i){ /* fake USB disconnect for > 250 ms */ _delay_ms(1); } init_spi(); si4432_swreset(); #if HW_VER == 0 si4432_setupgpio(si_gpio0txstate,si_gpio1rxstate,si_gpio2rxdat,0x58); #endif #if HW_VER == 1 si4432_setupgpio(si_gpio0txstate,si_gpio1txstate,si_gpio2rxstate,0x58); #endif set_modem_conf(5); si4432_tune_base(433000000); si4432_hop(1,180); REGW(si_headcon1,0); REGW(si_headcon2,si_fixpklen|si_syncword3210); // REGW(si_headcon2,0); REGW(si_prealenl,16); REGW(si_sync3,0x0f); REGW(si_sync2,0x34); REGW(si_sync1,0x21); REGW(si_sync0,0xff); REGW(si_data_access_contorl,si_enpacrx|si_enpactx|si_encrc|si_crc16); //start_responder(); set_sleep_mode(SLEEP_MODE_IDLE); usbDeviceConnect(); sei(); DDRD&=~(1<<4); for(;;){ /* main event loop */ if((rxtxrx_state&0x7f)<=0) { sleep_enable(); sleep_cpu(); sleep_disable(); } LED0_ON(); usbPoll(); if(iwp!=irp) if(UCSRA&(1<<UDRE)) { UDR=intbuf[irp++]; } /* if(usbInterruptIsReady()) { if(iwp!=irp) usbSetInterrupt(&intbuf[irp++],1); }*/ LED0_OFF(); radioPoll(); if(resp) { uint8_t tmp; rx1buf_p=0; do{ TIMSK&=~(1<<TICIE1); REGR(si_status,tmp); TIMSK|=(1<<TICIE1); if(tmp&si_rxffem) break; TIMSK&=~(1<<TICIE1); REGR(si_fifo,rx1buf[rx1buf_p++]); TIMSK|=(1<<TICIE1); }while(1); if(rx1buf[rx1buf_p-1]>0) { TIMSK&=~(1<<TICIE1); REGW(si_mode02,si_ffclrtx); REGW(si_mode02,0); REGW(si_fifo,rx1buf[rx1buf_p-1]); REGW(si_fifo,0); REGW(si_txpower,0x18|(rx1buf[rx1buf_p-1]&0x07)); TIMSK|=(1<<TICIE1); } } /* if(resp==2) { uint8_t tmp,int1,int2; REGR(si_ezmac_stat,tmp); if(tmp&si_pksent) { REGW(si_mode02,si_ffclrrx|si_ffclrtx); REGW(si_mode02,0); REGR(si_interrupt1,int1); REGR(si_interrupt2,int2); REGW(si_fifo,0); REGW(si_fifo,0); REGW(si_mode01,si_rxon|si_pllon|si_xton); resp=1; } }*/ }; }
void radioPoll() { uint8_t int1; uint8_t int2; switch(rxtxrx_state) { case RXTXRX_IDLE://idle return; case RXTXRX_RX1://rx1 REGW(si_pklen,rx1buf_len); REGW(si_mode02,si_ffclrrx); REGW(si_mode02,0); REGW(si_inten1,si_ipkvalid); REGW(si_inten2,0); REGR(si_interrupt1,int1); REGR(si_interrupt2,int2); REGW(si_mode01,si_rxon); rxtxrx_state=RXTXRX_TX1; case RXTXRX_TX1://tx1 if(GET_nIRQ()==0) { BURSTR(si_fifo,rx1buf,rx1buf_len); REGW(si_mode02,si_ffclrtx); REGW(si_mode02,0); REGW(si_pklen,tx1buf_len); BURSTW(si_fifo,tx1buf,tx1buf_len); REGW(si_inten1,si_ipksent); REGR(si_interrupt1,int1); REGR(si_interrupt2,int2); REGW(si_mode01,si_txon); rxtxrx_state=RXTXRX_RX2; } case RXTXRX_RX2://rx2 if(GET_nIRQ()==0) { REGW(si_pklen,rx2buf_len); REGW(si_mode02,si_ffclrrx); REGW(si_mode02,0); REGW(si_inten1,si_ipkvalid); REGW(si_inten2,si_ipreaval|si_iswdet); REGR(si_interrupt1,int1); REGR(si_interrupt2,int2); REGW(si_mode01,si_rxon); rxtxrx_state=RXTXRX_FIN; } case RXTXRX_FIN://finish if(GET_nIRQ()==0) { REGR(si_interrupt2,int2); if(int2&(si_ipreaval|si_iswdet)) { REGR(si_rssi,rxtxrx_rssi); REGW(si_inten2,0); } REGR(si_interrupt1,int1); if(int1&si_ipkvalid) { BURSTR(si_fifo,rx2buf,rx2buf_len); REGW(si_mode02,si_ffclrtx|si_ffclrrx); REGW(si_mode02,0); REGW(si_inten1,0); REGW(si_inten2,0); REGR(si_interrupt1,int1); REGR(si_interrupt2,int2); REGW(si_mode01,0); rxtxrx_state=RXTXRX_DONE; } } default://all done return; } }
usbMsgLen_t usbFunctionSetup(uchar data[8]) { struct usbRequest *rq = (void *)data; static uint8_t replyBuffer[4]; bRequest=rq->bRequest; usbMsgPtr=(void*)&replyBuffer; switch(bRequest) { case CUSTOM_RQ_LED: if(rq->bmRequestType&USBRQ_DIR_DEVICE_TO_HOST) { if(rq->wValue.bytes[0]&0x02) { if(rq->wValue.bytes[0]&0x01) DDRD|=(1<<4); else DDRD&=~(1<<4); } replyBuffer[0]=(DDRD&(1<<4))!=0; return 1; }else return 0; case SPI_TRANS: if(rq->bmRequestType&USBRQ_DIR_DEVICE_TO_HOST) { if(rq->wIndex.bytes[0]&SPI_CS2) { SI_CS(1); N_CS(rq->wIndex.bytes[0]&SPI_CS_BEFORE); }else{ N_CS(1); SI_CS(rq->wIndex.bytes[0]&SPI_CS_BEFORE); } if(rq->wLength.bytes[0]>0) { SPDR=rq->wValue.bytes[0]; while((SPSR&(1<<SPIF))==0); replyBuffer[0]=SPDR; if(rq->wLength.bytes[0]>1) { SPDR=rq->wValue.bytes[1]; while((SPSR&(1<<SPIF))==0); replyBuffer[1]=SPDR; } } if(rq->wIndex.bytes[0]&SPI_CS2) N_CS(rq->wIndex.bytes[0]&SPI_CS_AFTER); else SI_CS(rq->wIndex.bytes[0]&SPI_CS_AFTER); N_CE(rq->wIndex.bytes[0]&SPI_CE); return rq->wLength.bytes[0]; }else{ return 0; } case SPI_BURST: if(rq->wIndex.bytes[0]&SPI_CS2) { SI_CS(1); N_CS(rq->wIndex.bytes[0]&SPI_CS_BEFORE); }else{ N_CS(1); SI_CS(rq->wIndex.bytes[0]&SPI_CS_BEFORE); } burst_cs_after=rq->wIndex.bytes[0]; bLength=rq->wLength.word; return USB_NO_MSG; case CUSTOM_RXTXRX: bLength=rq->wLength.word; if(rq->bmRequestType&USBRQ_DIR_DEVICE_TO_HOST) { wValue=rq->wValue.word; if(wValue==4) { rxtxrx_state=0; return 0; } if(wValue==2) { replyBuffer[0]=rxtxrx_state; replyBuffer[1]=rx1buf_len; replyBuffer[2]=rx2buf_len; replyBuffer[3]=rxtxrx_rssi; return 4; } rx1buf_p=0; rx2buf_p=0; }else{ tx1buf_len=bLength; tx1buf_p=0; rx1buf_len=rq->wValue.bytes[0]; rx1buf_p=0; rx2buf_len=rq->wValue.bytes[1]; rx2buf_p=0; } return USB_NO_MSG; case CUSTOM_INTERVALS: bLength=rq->wLength.word; if(rq->bmRequestType&USBRQ_DIR_DEVICE_TO_HOST) { if(bLength==0) { uint8_t int1,int2; REGW(si_mode01,0); REGW(si_mode02,si_ffclrrx); REGW(si_mode02,si_rxmpk); REGW(si_preadetcon,0xf8); REGR(si_modcon2,int1); int1&=0x0f; REGW(si_modcon2,int1); TCCR1B=rq->wValue.bytes[0]; ilast=TCNT1=0; TIMSK|=(1<<TICIE1); imin=rq->wValue.bytes[1]; imax=rq->wIndex.bytes[0]; irp=iwp=0; REGR(si_interrupt1,int1); REGR(si_interrupt2,int2); REGW(si_mode01,si_rxon); return 0; }else{ if(rq->wValue.word&1) { REGW(si_mode01,0); TCCR1B=0; TIMSK&=~(1<<TICIE1); } if(rq->wValue.word&2) { replyBuffer[0]=iwp-irp; return 1; } } }else{ //tx not implemented so far return 0; } return USB_NO_MSG; case CUSTOM_RESPONDER: if(rq->wValue.bytes[0]) { start_responder(); }else{ stop_responder(); } return 0; } return 0; /* default for not implemented requests: return no data back to host */ }