static void read_dce_straps(
struct dc_context *ctx,
struct resource_straps *straps)
{
REG_GET_2(CC_DC_HDMI_STRAPS,
HDMI_DISABLE, &straps->hdmi_disable,
AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
}
void hubp1_read_state(struct hubp *hubp)
{
struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
struct dcn_hubp_state *s = &hubp1->state;
struct _vcs_dpi_display_dlg_regs_st *dlg_attr = &s->dlg_attr;
struct _vcs_dpi_display_ttu_regs_st *ttu_attr = &s->ttu_attr;
struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;
/* Requester */
REG_GET(HUBPRET_CONTROL,
DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs->plane1_base_address);
REG_GET_4(DCN_EXPANSION_MODE,
DRQ_EXPANSION_MODE, &rq_regs->drq_expansion_mode,
PRQ_EXPANSION_MODE, &rq_regs->prq_expansion_mode,
MRQ_EXPANSION_MODE, &rq_regs->mrq_expansion_mode,
CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode);
REG_GET_8(DCHUBP_REQ_SIZE_CONFIG,
CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size,
MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size,
META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size,
MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size,
DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size,
MPTE_GROUP_SIZE, &rq_regs->rq_regs_l.mpte_group_size,
SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height,
PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear);
REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C,
CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size,
MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size,
META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size,
MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size,
DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size,
MPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.mpte_group_size,
SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height,
PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear);
/* DLG - Per hubp */
REG_GET_2(BLANK_OFFSET_0,
REFCYC_H_BLANK_END, &dlg_attr->refcyc_h_blank_end,
DLG_V_BLANK_END, &dlg_attr->dlg_vblank_end);
REG_GET(BLANK_OFFSET_1,
MIN_DST_Y_NEXT_START, &dlg_attr->min_dst_y_next_start);
REG_GET(DST_DIMENSIONS,
REFCYC_PER_HTOTAL, &dlg_attr->refcyc_per_htotal);
REG_GET_2(DST_AFTER_SCALER,
REFCYC_X_AFTER_SCALER, &dlg_attr->refcyc_x_after_scaler,
DST_Y_AFTER_SCALER, &dlg_attr->dst_y_after_scaler);
if (REG(PREFETCH_SETTINS))
REG_GET_2(PREFETCH_SETTINS,
DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch,
VRATIO_PREFETCH, &dlg_attr->vratio_prefetch);
else
REG_GET_2(PREFETCH_SETTINGS,
DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch,
VRATIO_PREFETCH, &dlg_attr->vratio_prefetch);
REG_GET_2(VBLANK_PARAMETERS_0,
DST_Y_PER_VM_VBLANK, &dlg_attr->dst_y_per_vm_vblank,
DST_Y_PER_ROW_VBLANK, &dlg_attr->dst_y_per_row_vblank);
REG_GET(REF_FREQ_TO_PIX_FREQ,
REF_FREQ_TO_PIX_FREQ, &dlg_attr->ref_freq_to_pix_freq);
/* DLG - Per luma/chroma */
REG_GET(VBLANK_PARAMETERS_1,
REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr->refcyc_per_pte_group_vblank_l);
REG_GET(VBLANK_PARAMETERS_3,
REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr->refcyc_per_meta_chunk_vblank_l);
if (REG(NOM_PARAMETERS_0))
REG_GET(NOM_PARAMETERS_0,
DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr->dst_y_per_pte_row_nom_l);
if (REG(NOM_PARAMETERS_1))
REG_GET(NOM_PARAMETERS_1,
REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr->refcyc_per_pte_group_nom_l);
REG_GET(NOM_PARAMETERS_4,
DST_Y_PER_META_ROW_NOM_L, &dlg_attr->dst_y_per_meta_row_nom_l);
REG_GET(NOM_PARAMETERS_5,
REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr->refcyc_per_meta_chunk_nom_l);
REG_GET_2(PER_LINE_DELIVERY_PRE,
REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr->refcyc_per_line_delivery_pre_l,
REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr->refcyc_per_line_delivery_pre_c);
REG_GET_2(PER_LINE_DELIVERY,
REFCYC_PER_LINE_DELIVERY_L, &dlg_attr->refcyc_per_line_delivery_l,
REFCYC_PER_LINE_DELIVERY_C, &dlg_attr->refcyc_per_line_delivery_c);
if (REG(PREFETCH_SETTINS_C))
REG_GET(PREFETCH_SETTINS_C,
VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c);
else
REG_GET(PREFETCH_SETTINGS_C,
VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c);
REG_GET(VBLANK_PARAMETERS_2,
REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr->refcyc_per_pte_group_vblank_c);
REG_GET(VBLANK_PARAMETERS_4,
REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr->refcyc_per_meta_chunk_vblank_c);
if (REG(NOM_PARAMETERS_2))
REG_GET(NOM_PARAMETERS_2,
DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr->dst_y_per_pte_row_nom_c);
if (REG(NOM_PARAMETERS_3))
REG_GET(NOM_PARAMETERS_3,
REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr->refcyc_per_pte_group_nom_c);
REG_GET(NOM_PARAMETERS_6,
DST_Y_PER_META_ROW_NOM_C, &dlg_attr->dst_y_per_meta_row_nom_c);
REG_GET(NOM_PARAMETERS_7,
REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr->refcyc_per_meta_chunk_nom_c);
/* TTU - per hubp */
REG_GET_2(DCN_TTU_QOS_WM,
QoS_LEVEL_LOW_WM, &ttu_attr->qos_level_low_wm,
QoS_LEVEL_HIGH_WM, &ttu_attr->qos_level_high_wm);
REG_GET_2(DCN_GLOBAL_TTU_CNTL,
MIN_TTU_VBLANK, &ttu_attr->min_ttu_vblank,
QoS_LEVEL_FLIP, &ttu_attr->qos_level_flip);
/* TTU - per luma/chroma */
/* Assumed surf0 is luma and 1 is chroma */
REG_GET_3(DCN_SURF0_TTU_CNTL0,
REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_l,
QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_l,
QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_l);
REG_GET(DCN_SURF0_TTU_CNTL1,
REFCYC_PER_REQ_DELIVERY_PRE,
&ttu_attr->refcyc_per_req_delivery_pre_l);
REG_GET_3(DCN_SURF1_TTU_CNTL0,
REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_c,
QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_c,
QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_c);
REG_GET(DCN_SURF1_TTU_CNTL1,
REFCYC_PER_REQ_DELIVERY_PRE,
&ttu_attr->refcyc_per_req_delivery_pre_c);
/* Rest of hubp */
REG_GET(DCSURF_SURFACE_CONFIG,
SURFACE_PIXEL_FORMAT, &s->pixel_format);
REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH,
SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &s->inuse_addr_hi);
REG_GET(DCSURF_SURFACE_EARLIEST_INUSE,
SURFACE_EARLIEST_INUSE_ADDRESS, &s->inuse_addr_lo);
REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION,
PRI_VIEWPORT_WIDTH, &s->viewport_width,
PRI_VIEWPORT_HEIGHT, &s->viewport_height);
REG_GET_2(DCSURF_SURFACE_CONFIG,
ROTATION_ANGLE, &s->rotation_angle,
H_MIRROR_EN, &s->h_mirror_en);
REG_GET(DCSURF_TILING_CONFIG,
SW_MODE, &s->sw_mode);
REG_GET(DCSURF_SURFACE_CONTROL,
PRIMARY_SURFACE_DCC_EN, &s->dcc_en);
REG_GET_3(DCHUBP_CNTL,
HUBP_BLANK_EN, &s->blank_en,
HUBP_TTU_DISABLE, &s->ttu_disable,
HUBP_UNDERFLOW_STATUS, &s->underflow_status);
REG_GET(DCN_GLOBAL_TTU_CNTL,
MIN_TTU_VBLANK, &s->min_ttu_vblank);
REG_GET_2(DCN_TTU_QOS_WM,
QoS_LEVEL_LOW_WM, &s->qos_level_low_wm,
QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm);
}
