void mdss_vbif_qos_remapper_setup(struct msm_panel_info *pinfo)
{
uint32_t mask, reg_val, i;
uint32_t left_pipe_xin_id, right_pipe_xin_id;
uint32_t mdp_hw_rev = readl(MDP_HW_REV);
uint32_t vbif_qos[4] = {0, 0, 0, 0};
uint32_t vbif_offset;
mdp_select_pipe_xin_id(pinfo,
&left_pipe_xin_id, &right_pipe_xin_id);
if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_106) ||
MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_108) ||
MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_112)) {
vbif_qos[0] = 2;
vbif_qos[1] = 2;
vbif_qos[2] = 2;
vbif_qos[3] = 2;
} else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_105) ||
MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_109) ||
MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_107) ||
MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_110)) {
vbif_qos[0] = 1;
vbif_qos[1] = 2;
vbif_qos[2] = 2;
vbif_qos[3] = 2;
} else {
return;
}
vbif_offset = mdss_mdp_vbif_qos_remap_get_offset();
for (i = 0; i < 4; i++) {
/* VBIF_VBIF_QOS_REMAP_00 */
reg_val = readl(REG_MDP(vbif_offset) + i*4);
mask = 0x3 << (left_pipe_xin_id * 2);
reg_val &= ~(mask);
reg_val |= vbif_qos[i] << (left_pipe_xin_id * 2);
if (pinfo->lcdc.dual_pipe) {
mask = 0x3 << (right_pipe_xin_id * 2);
reg_val &= ~(mask);
reg_val |= vbif_qos[i] << (right_pipe_xin_id * 2);
}
writel(reg_val, REG_MDP(vbif_offset) + i*4);
}
}
int mdp_dsi_cmd_config(struct msm_panel_info *pinfo,
struct fbcon_config *fb)
{
uint32_t intf_sel, sintf_sel;
uint32_t intf_base, sintf_base;
uint32_t reg;
int ret = NO_ERROR;
uint32_t left_pipe, right_pipe;
struct lcdc_panel_info *lcdc = NULL;
if (pinfo == NULL)
return ERR_INVALID_ARGS;
lcdc = &(pinfo->lcdc);
if (lcdc == NULL)
return ERR_INVALID_ARGS;
mdp_set_intf_base(pinfo, &intf_sel, &sintf_sel, &intf_base, &sintf_base);
if (pinfo->lcdc.split_display) {
reg = BIT(1); /* Command mode */
if (pinfo->lcdc.dst_split)
reg |= BIT(2); /* Enable SMART_PANEL_FREE_RUN mode */
if (pinfo->lcdc.pipe_swap)
reg |= BIT(4); /* Use intf2 as trigger */
else
reg |= BIT(8); /* Use intf1 as trigger */
writel(reg, MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL);
writel(reg, MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL);
writel(0x1, MDP_REG_SPLIT_DISPLAY_EN);
}
if (pinfo->lcdc.dst_split) {
uint32_t ppb_offset = mdss_mdp_get_ppb_offset();
writel(BIT(16) | BIT(20) | BIT(21), REG_MDP(ppb_offset + 0x4)); /* MMSS_MDP_PPB0_CNTL */
writel(BIT(5), REG_MDP(ppb_offset)); /* MMSS_MDP_PPB0_CONFIG */
}
mdp_clk_gating_ctrl();
if (pinfo->mipi.dual_dsi)
intf_sel |= sintf_sel; /* INTF 2 enable */
writel(intf_sel, MDP_DISP_INTF_SEL);
mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe);
mdss_vbif_setup();
mdss_smp_setup(pinfo, left_pipe, right_pipe);
mdss_qos_remapper_setup();
mdss_vbif_qos_remapper_setup(pinfo);
mdss_source_pipe_config(fb, pinfo, left_pipe);
if (pinfo->lcdc.dual_pipe)
mdss_source_pipe_config(fb, pinfo, right_pipe);
mdss_layer_mixer_setup(fb, pinfo);
writel(0x213F, MDP_PANEL_FORMAT + intf_base);
reg = 0x21f00 | mdss_mdp_ctl_out_sel(pinfo, 1);
writel(reg, MDP_CTL_0_BASE + CTL_TOP);
if (pinfo->fbc.enabled)
mdss_fbc_cfg(pinfo);
if (pinfo->mipi.dual_dsi) {
writel(0x213F, sintf_base + MDP_PANEL_FORMAT);
if (!pinfo->lcdc.dst_split) {
reg = 0x21f00 | mdss_mdp_ctl_out_sel(pinfo, 0);
writel(reg, MDP_CTL_1_BASE + CTL_TOP);
}
}
return ret;
}
static void mdss_intf_tg_setup(struct msm_panel_info *pinfo, uint32_t intf_base)
{
uint32_t hsync_period, vsync_period;
uint32_t hsync_start_x, hsync_end_x;
uint32_t display_hctl, hsync_ctl, display_vstart, display_vend;
uint32_t adjust_xres = 0;
struct lcdc_panel_info *lcdc = NULL;
struct intf_timing_params itp = {0};
if (pinfo == NULL)
return;
lcdc = &(pinfo->lcdc);
if (lcdc == NULL)
return;
adjust_xres = pinfo->xres;
if (pinfo->lcdc.split_display) {
adjust_xres /= 2;
if (intf_base == (MDP_INTF_1_BASE + mdss_mdp_intf_offset())) {
writel(BIT(8), MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL);
writel(BIT(8), MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL);
writel(0x1, MDP_REG_SPLIT_DISPLAY_EN);
}
}
if (pinfo->lcdc.dst_split && (intf_base == (MDP_INTF_1_BASE + mdss_mdp_intf_offset()))) {
uint32_t ppb_offset = mdss_mdp_get_ppb_offset();
writel(BIT(16), REG_MDP(ppb_offset + 0x4)); /* MMSS_MDP_PPB0_CNTL */
writel(BIT(5), REG_MDP(ppb_offset)); /* MMSS_MDP_PPB0_CONFIG */
}
if (!pinfo->fbc.enabled || !pinfo->fbc.comp_ratio)
pinfo->fbc.comp_ratio = 1;
itp.xres = (adjust_xres / pinfo->fbc.comp_ratio);
itp.yres = pinfo->yres;
itp.width =((adjust_xres + pinfo->lcdc.xres_pad) / pinfo->fbc.comp_ratio);
itp.height = pinfo->yres + pinfo->lcdc.yres_pad;
itp.h_back_porch = pinfo->lcdc.h_back_porch;
itp.h_front_porch = pinfo->lcdc.h_front_porch;
itp.v_back_porch = pinfo->lcdc.v_back_porch;
itp.v_front_porch = pinfo->lcdc.v_front_porch;
itp.hsync_pulse_width = pinfo->lcdc.h_pulse_width;
itp.vsync_pulse_width = pinfo->lcdc.v_pulse_width;
itp.border_clr = pinfo->lcdc.border_clr;
itp.underflow_clr = pinfo->lcdc.underflow_clr;
itp.hsync_skew = pinfo->lcdc.hsync_skew;
hsync_period = itp.hsync_pulse_width + itp.h_back_porch +
itp.width + itp.h_front_porch;
vsync_period = itp.vsync_pulse_width + itp.v_back_porch +
itp.height + itp.v_front_porch;
hsync_start_x =
itp.hsync_pulse_width +
itp.h_back_porch;
hsync_end_x =
hsync_period - itp.h_front_porch - 1;
display_vstart = (itp.vsync_pulse_width +
itp.v_back_porch)
* hsync_period + itp.hsync_skew;
display_vend = ((vsync_period - itp.v_front_porch) * hsync_period)
+ itp.hsync_skew - 1;
if (intf_base == (MDP_INTF_0_BASE + mdss_mdp_intf_offset())) { /* eDP */
display_vstart += itp.hsync_pulse_width + itp.h_back_porch;
display_vend -= itp.h_front_porch;
}
hsync_ctl = (hsync_period << 16) | itp.hsync_pulse_width;
display_hctl = (hsync_end_x << 16) | hsync_start_x;
writel(hsync_ctl, MDP_HSYNC_CTL + intf_base);
writel(vsync_period*hsync_period, MDP_VSYNC_PERIOD_F0 +
intf_base);
writel(0x00, MDP_VSYNC_PERIOD_F1 + intf_base);
writel(itp.vsync_pulse_width*hsync_period,
MDP_VSYNC_PULSE_WIDTH_F0 +
intf_base);
writel(0x00, MDP_VSYNC_PULSE_WIDTH_F1 + intf_base);
writel(display_hctl, MDP_DISPLAY_HCTL + intf_base);
writel(display_vstart, MDP_DISPLAY_V_START_F0 +
intf_base);
writel(0x00, MDP_DISPLAY_V_START_F1 + intf_base);
writel(display_vend, MDP_DISPLAY_V_END_F0 +
intf_base);
writel(0x00, MDP_DISPLAY_V_END_F1 + intf_base);
writel(0x00, MDP_ACTIVE_HCTL + intf_base);
writel(0x00, MDP_ACTIVE_V_START_F0 + intf_base);
writel(0x00, MDP_ACTIVE_V_START_F1 + intf_base);
writel(0x00, MDP_ACTIVE_V_END_F0 + intf_base);
writel(0x00, MDP_ACTIVE_V_END_F1 + intf_base);
writel(0xFF, MDP_UNDERFFLOW_COLOR + intf_base);
if (intf_base == (MDP_INTF_0_BASE + mdss_mdp_intf_offset())) /* eDP */
writel(0x212A, MDP_PANEL_FORMAT + intf_base);
else
writel(0x213F, MDP_PANEL_FORMAT + intf_base);
}
