/* Enable the HSUART */
REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, UART_BASE_ADDRESS),
REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_MEMORY),
REG_SCRIPT_END
};
static const struct reg_script mtrr_init[] = {
/* Use write-through caching, for FSP 2.0 the cache will be invalidated
* postchar (arch/x86/exit_car.S).
*/
/* Enable the cache */
REG_CPU_CR_AND(0, ~(CR0_CD | CR0_NW)),
/* Cache the SPI flash */
REG_MSR_WRITE(MTRR_PHYS_BASE(0), (uint32_t)((-CONFIG_ROM_SIZE)
| MTRR_TYPE_WRTHROUGH)),
REG_MSR_WRITE(MTRR_PHYS_MASK(0), (uint32_t)((-CONFIG_ROM_SIZE)
| MTRR_PHYS_MASK_VALID)),
/* Cache ESRAM */
REG_MSR_WRITE(MTRR_PHYS_BASE(1), (uint32_t)(0x80000000
| MTRR_TYPE_WRTHROUGH)),
REG_MSR_WRITE(MTRR_PHYS_MASK(1), (uint32_t)((~0x7ffff)
| MTRR_PHYS_MASK_VALID)),
/* Enable the variable MTRRs */
REG_MSR_WRITE(MTRR_DEF_TYPE_MSR, MTRR_DEF_TYPE_EN
| MTRR_TYPE_UNCACHEABLE),
REG_SCRIPT_END
};
/*
* MP and SMM loading initialization.
*/
struct smm_relocation_attrs {
uint32_t smbase;
uint32_t smrr_base;
uint32_t smrr_mask;
};
static struct smm_relocation_attrs relo_attrs;
/* Package level MSRs */
static const struct reg_script package_msr_script[] = {
/* Set Package TDP to ~7W */
REG_MSR_WRITE(MSR_PKG_POWER_LIMIT, 0x3880fa),
REG_MSR_RMW(MSR_PP1_POWER_LIMIT, ~(0x7f << 17), 0),
REG_MSR_WRITE(MSR_PKG_TURBO_CFG1, 0x702),
REG_MSR_WRITE(MSR_CPU_TURBO_WKLD_CFG1, 0x200b),
REG_MSR_WRITE(MSR_CPU_TURBO_WKLD_CFG2, 0),
REG_MSR_WRITE(MSR_CPU_THERM_CFG1, 0x00000305),
REG_MSR_WRITE(MSR_CPU_THERM_CFG2, 0x0405500d),
REG_MSR_WRITE(MSR_CPU_THERM_SENS_CFG, 0x27),
REG_SCRIPT_END
};
static void pre_mp_init(void)
{
uint32_t bsmrwac;
/* Set up MTRRs based on physical address size. */
