void i2c_init_early(void)
{
LTRACE_ENTRY;
/* enable clocks on i2c 0-2 */
RMWREG32(CM_FCLKEN1_CORE, 15, 3, 0x7),
RMWREG32(CM_ICLKEN1_CORE, 15, 3, 0x7),
i2c_reset_bus(0);
i2c_reset_bus(1);
i2c_reset_bus(2);
#if 0
// write something into a reg
char buf[2];
i2c_write_reg(0, 0x4b, 0x14, 0x99);
i2c_write_reg(0, 0x4b, 0x15, 0x98);
i2c_read_reg(0, 0x4b, 0x15, buf);
printf("0x%hhx\n", buf[0]);
i2c_read_reg(0, 0x4b, 0x14, buf);
printf("0x%hhx\n", buf[0]);
int i;
for (i=0; i < 255; i++) {
char buf[1];
buf[0] = i;
i2c_transmit(0, 0x4b, buf, 1);
i2c_receive(0, 0x4b, buf, sizeof(buf));
printf("0x%hhx\n", buf[0]);
}
#endif
LTRACE_EXIT;
}
/*
* Function: sdhci msm init
* Arg : MSM specific config data for sdhci
* Return : None
* Flow: : Enable sdhci mode & do msm specific init
*/
void sdhci_msm_init(struct sdhci_host *host, struct sdhci_msm_data *config)
{
/* Disable HC mode */
RMWREG32((config->pwrctl_base + SDCC_MCI_HC_MODE), SDHCI_HC_START_BIT, SDHCI_HC_WIDTH, 0);
/* Core power reset */
RMWREG32((config->pwrctl_base + SDCC_MCI_POWER), CORE_SW_RST_START, CORE_SW_RST_WIDTH, 1);
/* Wait for the core power reset to complete*/
mdelay(1);
/* Enable sdhc mode */
RMWREG32((config->pwrctl_base + SDCC_MCI_HC_MODE), SDHCI_HC_START_BIT, SDHCI_HC_WIDTH, SDHCI_HC_MODE_EN);
/* Set the FF_CLK_SW_RST_DIS to 1 */
RMWREG32((config->pwrctl_base + SDCC_MCI_HC_MODE), FF_CLK_SW_RST_DIS_START, FF_CLK_SW_RST_DIS_WIDTH, 1);
/*
* Reset the controller
*/
sdhci_reset(host, SDHCI_SOFT_RESET);
/*
* CORE_SW_RST may trigger power irq if previous status of PWRCTL
* was either BUS_ON or IO_HIGH. So before we enable the power irq
* interrupt in GIC (by registering the interrupt handler), we need to
* ensure that any pending power irq interrupt status is acknowledged
* otherwise power irq interrupt handler would be fired prematurely.
*/
sdhci_clear_power_ctrl_irq(config);
/*
* Register the interrupt handler for pwr irq
*/
register_int_handler(config->pwr_irq, sdhci_int_handler, (void *)config);
unmask_interrupt(config->pwr_irq);
/* Enable pwr control interrupt */
writel(SDCC_HC_PWR_CTRL_INT, (config->pwrctl_base + SDCC_HC_PWRCTL_MASK_REG));
config->tuning_done = false;
config->calibration_done = false;
host->tuning_in_progress = false;
}
int tcc_gpio_config(unsigned gpio, unsigned flags)
{
gpioregs *r = tcc892x_gpio_to_reg((gpio&GPIO_REGMASK));
unsigned num = gpio & GPIO_BITMASK;;
unsigned bit = (1<<num);
if(r == NULL)
return -EINVAL;
if (flags & GPIO_FN_BITMASK) {
unsigned fn = ((flags & GPIO_FN_BITMASK) >> GPIO_FN_SHIFT) - 1;
if (num < 8)
RMWREG32(&r->func_select0, num*4, 4, fn);
else if (num < 16)
RMWREG32(&r->func_select1, (num-8)*4, 4, fn);
else if (num < 24)
RMWREG32(&r->func_select2, (num-16)*4, 4, fn);
else
RMWREG32(&r->func_select3, (num-24)*4, 4, fn);
}
int tcc_gpio_config_ext_intr(unsigned intr, unsigned source) /* intr: irq num, source: external interrupt source */
{
int extint;
GPIO *reg = (GPIO *) GPIO_REG(HwGPIO_BASE);
switch (intr) {
case INT_EI0: extint = EXINT_EI0; break;
case INT_EI1: extint = EXINT_EI1; break;
case INT_EI2: extint = EXINT_EI2; break;
case INT_EI3: extint = EXINT_EI3; break;
case INT_EI4: extint = EXINT_EI4; break;
case INT_EI5: extint = EXINT_EI5; break;
case INT_EI6: extint = EXINT_EI6; break;
case INT_EI7: extint = EXINT_EI7; break;
case INT_EI8: extint = EXINT_EI8; break;
case INT_EI9: extint = EXINT_EI9; break;
case INT_EI10: extint = EXINT_EI10; break;
case INT_EI11: extint = EXINT_EI11; break;
default:
extint = -1;
break;
}
if (extint < 0)
return -1;
if(extint < 4) {
RMWREG32(®->EINTSEL0.nREG, extint*8, 7, source);
}
else if(extint < 8) {
RMWREG32(®->EINTSEL1.nREG, (extint-4)*8, 7, source);
}
else if(extint < 12) {
RMWREG32(®->EINTSEL2.nREG, (extint-8)*8, 7, source);
}
return 0;
}
void platform_init_timer(void)
{
/* GPT2 */
RMWREG32(CM_CLKSEL_PER, 0, 1, 1);
RMWREG32(CM_ICLKEN_PER, 3, 1, 1);
RMWREG32(CM_FCLKEN_PER, 3, 1, 1);
// reset the GP timer
TIMER_REG(TIOCP_CFG) = 0x2;
while ((TIMER_REG(TISTAT) & 1) == 0)
;
// set GPT2-9 clock inputs over to 32k
*REG32(CM_CLKSEL_PER) = 0;
// disable ints
TIMER_REG(TIER) = 0;
TIMER_REG(TISR) = 0x7; // clear any pending bits
// XXX make sure 32K timer is running
register_int_handler(GPT2_IRQ, &os_timer_tick, NULL);
}
void
ArchUART8250Omap::InitEarly()
{
// Perform special hardware UART configuration
/* UART1 */
RMWREG32(CM_FCLKEN1_CORE, 13, 1, 1);
RMWREG32(CM_ICLKEN1_CORE, 13, 1, 1);
/* UART2 */
RMWREG32(CM_FCLKEN1_CORE, 14, 1, 1);
RMWREG32(CM_ICLKEN1_CORE, 14, 1, 1);
/* UART3 */
RMWREG32(CM_FCLKEN_PER, 11, 1, 1);
RMWREG32(CM_ICLKEN_PER, 11, 1, 1);
}
/*
* API to disable HC mode
*/
void sdhci_mode_disable(struct sdhci_host *host)
{
/* Disable HC mode */
RMWREG32((host->msm_host->pwrctl_base + SDCC_MCI_HC_MODE), SDHCI_HC_START_BIT, SDHCI_HC_WIDTH, 0);
}
/*
* Function: sdhci msm init
* Arg : MSM specific config data for sdhci
* Return : None
* Flow: : Enable sdhci mode & do msm specific init
*/
void sdhci_msm_init(struct sdhci_host *host, struct sdhci_msm_data *config)
{
uint32_t io_switch;
uint32_t caps = 0;
uint32_t version;
/* Disable HC mode */
RMWREG32((config->pwrctl_base + SDCC_MCI_HC_MODE), SDHCI_HC_START_BIT, SDHCI_HC_WIDTH, 0);
/* Core power reset */
RMWREG32((config->pwrctl_base + SDCC_MCI_POWER), CORE_SW_RST_START, CORE_SW_RST_WIDTH, 1);
/* Wait for the core power reset to complete*/
mdelay(1);
/* Enable sdhc mode */
RMWREG32((config->pwrctl_base + SDCC_MCI_HC_MODE), SDHCI_HC_START_BIT, SDHCI_HC_WIDTH, SDHCI_HC_MODE_EN);
/* Set the FF_CLK_SW_RST_DIS to 1 */
RMWREG32((config->pwrctl_base + SDCC_MCI_HC_MODE), FF_CLK_SW_RST_DIS_START, FF_CLK_SW_RST_DIS_WIDTH, 1);
/*
* Reset the controller
*/
sdhci_reset(host, SDHCI_SOFT_RESET);
/*
* Some platforms have same SDC instance shared between emmc & sd card.
* For such platforms the emmc IO voltage has to be switched from 3.3 to
* 1.8 for the contoller to work with emmc.
*/
if(config->use_io_switch)
{
io_switch = REG_READ32(host, SDCC_VENDOR_SPECIFIC_FUNC);
io_switch |= HC_IO_PAD_PWR_SWITCH | HC_IO_PAD_PWR_SWITCH_EN;
REG_WRITE32(host, io_switch, SDCC_VENDOR_SPECIFIC_FUNC);
}
/*
* CORE_SW_RST may trigger power irq if previous status of PWRCTL
* was either BUS_ON or IO_HIGH. So before we enable the power irq
* interrupt in GIC (by registering the interrupt handler), we need to
* ensure that any pending power irq interrupt status is acknowledged
* otherwise power irq interrupt handler would be fired prematurely.
*/
sdhci_clear_power_ctrl_irq(config);
/*
* Register the interrupt handler for pwr irq
*/
register_int_handler(config->pwr_irq, (int_handler)sdhci_int_handler, (void *)config);
unmask_interrupt(config->pwr_irq);
/* Enable pwr control interrupt */
writel(SDCC_HC_PWR_CTRL_INT, (config->pwrctl_base + SDCC_HC_PWRCTL_MASK_REG));
version = readl(host->msm_host->pwrctl_base + MCI_VERSION);
host->major = (version & CORE_VERSION_MAJOR_MASK) >> CORE_VERSION_MAJOR_SHIFT;
host->minor = (version & CORE_VERSION_MINOR_MASK);
/*
* For SDCC5 the capabilities registers does not have voltage advertised
* Override the values using SDCC_HC_VENDOR_SPECIFIC_CAPABILITIES0
*/
if (host->major >= 1 && host->minor != 0x11 && host->minor != 0x12)
{
caps = REG_READ32(host, SDHCI_CAPS_REG1);
if (config->slot == 0x1)
REG_WRITE32(host, (caps | SDHCI_1_8_VOL_MASK), SDCC_HC_VENDOR_SPECIFIC_CAPABILITIES0);
else
REG_WRITE32(host, (caps | SDHCI_3_0_VOL_MASK), SDCC_HC_VENDOR_SPECIFIC_CAPABILITIES0);
}
config->tuning_done = false;
config->calibration_done = false;
host->tuning_in_progress = false;
}
/* mux hs phy to route to dwc controller */
static void phy_mux_configure_with_tcsr()
{
/* As per the hardware team, set the mux for snps controller */
RMWREG32(TCSR_PHSS_USB2_PHY_SEL, 0x0, 0x1, 0x1);
}
