static void nouveau_perf_voltage(struct drm_device *dev, struct bit_entry *P, struct nouveau_pm_level *perflvl) { struct drm_nouveau_private *dev_priv = dev->dev_private; struct nvbios *bios = &dev_priv->vbios; u8 *vmap; int id; id = perflvl->volt_min; perflvl->volt_min = 0; /* boards using voltage table version <0x40 store the voltage * level directly in the perflvl entry as a multiple of 10mV */ if (dev_priv->engine.pm.voltage.version < 0x40) { perflvl->volt_min = id * 10000; perflvl->volt_max = perflvl->volt_min; return; } /* on newer ones, the perflvl stores an index into yet another * vbios table containing a min/max voltage value for the perflvl */ if (P->version != 2 || P->length < 34) { NV_DEBUG(dev, "where's our volt map table ptr? %d %d\n", P->version, P->length); return; } vmap = ROMPTR(bios, P->data[32]); if (!vmap) { NV_DEBUG(dev, "volt map table pointer invalid\n"); return; } if (id < vmap[3]) { vmap += vmap[1] + (vmap[2] * id); perflvl->volt_min = ROM32(vmap[0]); perflvl->volt_max = ROM32(vmap[4]); } }
static bool mxms_foreach(struct drm_device *dev, u8 types, bool (*exec)(struct drm_device *, u8 *, void *), void *info) { u8 *mxms = mxms_data(dev); u8 *desc = mxms + mxms_headerlen(dev); u8 *fini = desc + mxms_structlen(dev) - 1; while (desc < fini) { u8 type = desc[0] & 0x0f; u8 headerlen = 0; u8 recordlen = 0; u8 entries = 0; switch (type) { case 0: if (mxms_version(dev) >= 0x0300) headerlen = 8; else headerlen = 6; break; case 1: case 2: case 3: headerlen = 4; break; case 4: headerlen = 4; recordlen = 2; entries = (ROM32(desc[0]) & 0x01f00000) >> 20; break; case 5: headerlen = 8; break; case 6: if (mxms_version(dev) >= 0x0300) { headerlen = 4; recordlen = 8; entries = (desc[1] & 0xf0) >> 4; } else { headerlen = 8; } break; case 7: headerlen = 8; recordlen = 4; entries = desc[1] & 0x07; break; default: MXM_DBG(dev, "unknown descriptor type %d\n", type); return false; }
static bool mxms_foreach(struct drm_device *dev, u8 types, bool (*exec)(struct drm_device *, u8 *, void *), void *info) { u8 *mxms = mxms_data(dev); u8 *desc = mxms + mxms_headerlen(dev); u8 *fini = desc + mxms_structlen(dev) - 1; while (desc < fini) { u8 type = desc[0] & 0x0f; u8 headerlen = 0; u8 recordlen = 0; u8 entries = 0; switch (type) { case 0: /* Output Device Structure */ if (mxms_version(dev) >= 0x0300) headerlen = 8; else headerlen = 6; break; case 1: /* System Cooling Capability Structure */ case 2: /* Thermal Structure */ case 3: /* Input Power Structure */ headerlen = 4; break; case 4: /* GPIO Device Structure */ headerlen = 4; recordlen = 2; entries = (ROM32(desc[0]) & 0x01f00000) >> 20; break; case 5: /* Vendor Specific Structure */ headerlen = 8; break; case 6: /* Backlight Control Structure */ if (mxms_version(dev) >= 0x0300) { headerlen = 4; recordlen = 8; entries = (desc[1] & 0xf0) >> 4; } else { headerlen = 8; } break; case 7: /* Fan Control Structure */ headerlen = 8; recordlen = 4; entries = desc[1] & 0x07; break; default: MXM_DBG(dev, "unknown descriptor type %d\n", type); return false; }
u8 * nouveau_perf_timing(struct drm_device *dev, u32 freq, u8 *ver, u8 *len) { struct drm_nouveau_private *dev_priv = dev->dev_private; struct nvbios *bios = &dev_priv->vbios; struct bit_entry P; u8 *perf, *timing = NULL; u8 i = 0, hdr, cnt; if (bios->type == NVBIOS_BMP) { while ((perf = nouveau_perf_entry(dev, i++, ver, &hdr, &cnt, len)) && *ver == 0x15) { if (freq <= ROM32(perf[5]) * 20) { *ver = 0x00; *len = 14; return perf + 41; } } return NULL; } if (!bit_table(dev, 'P', &P)) { if (P.version == 1) timing = ROMPTR(dev, P.data[4]); else if (P.version == 2) timing = ROMPTR(dev, P.data[8]); } if (timing && timing[0] == 0x10) { u8 *ramcfg = nouveau_perf_ramcfg(dev, freq, ver, len); if (ramcfg && ramcfg[1] < timing[2]) { *ver = timing[0]; *len = timing[3]; return timing + timing[1] + (ramcfg[1] * timing[3]); } } return NULL; }
void nouveau_perf_init(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_pm_engine *pm = &dev_priv->engine.pm; struct nvbios *bios = &dev_priv->vbios; struct bit_entry P; struct nouveau_pm_memtimings *memtimings = &pm->memtimings; struct nouveau_pm_tbl_header mt_hdr; u8 version, headerlen, recordlen, entries; u8 *perf, *entry; int vid, i; if (bios->type == NVBIOS_BIT) { if (bit_table(dev, 'P', &P)) return; if (P.version != 1 && P.version != 2) { NV_WARN(dev, "unknown perf for BIT P %d\n", P.version); return; } perf = ROMPTR(bios, P.data[0]); version = perf[0]; headerlen = perf[1]; if (version < 0x40) { recordlen = perf[3] + (perf[4] * perf[5]); entries = perf[2]; } else { recordlen = perf[2] + (perf[3] * perf[4]); entries = perf[5]; } } else { if (bios->data[bios->offset + 6] < 0x25) { legacy_perf_init(dev); return; } perf = ROMPTR(bios, bios->data[bios->offset + 0x94]); if (!perf) { NV_DEBUG(dev, "perf table pointer invalid\n"); return; } version = perf[1]; headerlen = perf[0]; recordlen = perf[3]; entries = perf[2]; } if (entries > NOUVEAU_PM_MAX_LEVEL) { NV_DEBUG(dev, "perf table has too many entries - buggy vbios?\n"); entries = NOUVEAU_PM_MAX_LEVEL; } entry = perf + headerlen; /* For version 0x15, initialize memtiming table */ if(version == 0x15) { memtimings->timing = kcalloc(entries, sizeof(*memtimings->timing), GFP_KERNEL); if(!memtimings) { NV_WARN(dev,"Could not allocate memtiming table\n"); return; } mt_hdr.entry_cnt = entries; mt_hdr.entry_len = 14; mt_hdr.version = version; mt_hdr.header_len = 4; } for (i = 0; i < entries; i++) { struct nouveau_pm_level *perflvl = &pm->perflvl[pm->nr_perflvl]; perflvl->timing = NULL; if (entry[0] == 0xff) { entry += recordlen; continue; } switch (version) { case 0x12: case 0x13: case 0x15: perflvl->fanspeed = entry[55]; if (recordlen > 56) perflvl->volt_min = entry[56]; perflvl->core = ROM32(entry[1]) * 10; perflvl->memory = ROM32(entry[5]) * 20; break; case 0x21: case 0x23: case 0x24: perflvl->fanspeed = entry[4]; perflvl->volt_min = entry[5]; perflvl->shader = ROM16(entry[6]) * 1000; perflvl->core = perflvl->shader; perflvl->core += (signed char)entry[8] * 1000; if (dev_priv->chipset == 0x49 || dev_priv->chipset == 0x4b) perflvl->memory = ROM16(entry[11]) * 1000; else perflvl->memory = ROM16(entry[11]) * 2000; break; case 0x25: perflvl->fanspeed = entry[4]; perflvl->volt_min = entry[5]; perflvl->core = ROM16(entry[6]) * 1000; perflvl->shader = ROM16(entry[10]) * 1000; perflvl->memory = ROM16(entry[12]) * 1000; break; case 0x30: perflvl->memscript = ROM16(entry[2]); case 0x35: perflvl->fanspeed = entry[6]; perflvl->volt_min = entry[7]; perflvl->core = ROM16(entry[8]) * 1000; perflvl->shader = ROM16(entry[10]) * 1000; perflvl->memory = ROM16(entry[12]) * 1000; /*XXX: confirm on 0x35 */ perflvl->unk05 = ROM16(entry[16]) * 1000; break; case 0x40: #define subent(n) (ROM16(entry[perf[2] + ((n) * perf[3])]) & 0xfff) * 1000 perflvl->fanspeed = 0; /*XXX*/ perflvl->volt_min = entry[2]; if (dev_priv->card_type == NV_50) { perflvl->core = subent(0); perflvl->shader = subent(1); perflvl->memory = subent(2); perflvl->vdec = subent(3); perflvl->unka0 = subent(4); } else { perflvl->hub06 = subent(0); perflvl->hub01 = subent(1); perflvl->copy = subent(2); perflvl->shader = subent(3); perflvl->rop = subent(4); perflvl->memory = subent(5); perflvl->vdec = subent(6); perflvl->daemon = subent(10); perflvl->hub07 = subent(11); perflvl->core = perflvl->shader / 2; } break; } /* make sure vid is valid */ nouveau_perf_voltage(dev, &P, perflvl); if (pm->voltage.supported && perflvl->volt_min) { vid = nouveau_volt_vid_lookup(dev, perflvl->volt_min); if (vid < 0) { NV_DEBUG(dev, "drop perflvl %d, bad vid\n", i); entry += recordlen; continue; } } /* get the corresponding memory timings */ if (version == 0x15) { memtimings->timing[i].id = i; nv30_mem_timing_entry(dev,&mt_hdr,(struct nouveau_pm_tbl_entry*) &entry[41],0,&memtimings->timing[i]); perflvl->timing = &memtimings->timing[i]; } else if (version > 0x15) { /* last 3 args are for < 0x40, ignored for >= 0x40 */ perflvl->timing = nouveau_perf_timing(dev, &P, perflvl->memory / 1000, entry + perf[3], perf[5], perf[4]); } snprintf(perflvl->name, sizeof(perflvl->name), "performance_level_%d", i); perflvl->id = i; pm->nr_perflvl++; entry += recordlen; } }
void nouveau_perf_init(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_pm_engine *pm = &dev_priv->engine.pm; struct nvbios *bios = &dev_priv->vbios; struct bit_entry P; u8 version, headerlen, recordlen, entries; u8 *perf, *entry; int vid, i; if (bios->type == NVBIOS_BIT) { if (bit_table(dev, 'P', &P)) return; if (P.version != 1 && P.version != 2) { NV_WARN(dev, "unknown perf for BIT P %d\n", P.version); return; } perf = ROMPTR(bios, P.data[0]); version = perf[0]; headerlen = perf[1]; if (version < 0x40) { recordlen = perf[3] + (perf[4] * perf[5]); entries = perf[2]; } else { recordlen = perf[2] + (perf[3] * perf[4]); entries = perf[5]; } } else { if (bios->data[bios->offset + 6] < 0x25) { legacy_perf_init(dev); return; } perf = ROMPTR(bios, bios->data[bios->offset + 0x94]); if (!perf) { NV_DEBUG(dev, "perf table pointer invalid\n"); return; } version = perf[1]; headerlen = perf[0]; recordlen = perf[3]; entries = perf[2]; } entry = perf + headerlen; for (i = 0; i < entries; i++) { struct nouveau_pm_level *perflvl = &pm->perflvl[pm->nr_perflvl]; if (entry[0] == 0xff) { entry += recordlen; continue; } switch (version) { case 0x12: case 0x13: case 0x15: perflvl->fanspeed = entry[55]; perflvl->voltage = entry[56]; perflvl->core = ROM32(entry[1]) * 10; perflvl->memory = ROM32(entry[5]) * 20; break; case 0x21: case 0x23: case 0x24: perflvl->fanspeed = entry[4]; perflvl->voltage = entry[5]; perflvl->core = ROM16(entry[6]) * 1000; if (dev_priv->chipset == 0x49 || dev_priv->chipset == 0x4b) perflvl->memory = ROM16(entry[11]) * 1000; else perflvl->memory = ROM16(entry[11]) * 2000; break; case 0x25: perflvl->fanspeed = entry[4]; perflvl->voltage = entry[5]; perflvl->core = ROM16(entry[6]) * 1000; perflvl->shader = ROM16(entry[10]) * 1000; perflvl->memory = ROM16(entry[12]) * 1000; break; case 0x30: perflvl->memscript = ROM16(entry[2]); case 0x35: perflvl->fanspeed = entry[6]; perflvl->voltage = entry[7]; perflvl->core = ROM16(entry[8]) * 1000; perflvl->shader = ROM16(entry[10]) * 1000; perflvl->memory = ROM16(entry[12]) * 1000; /*XXX: confirm on 0x35 */ perflvl->unk05 = ROM16(entry[16]) * 1000; break; case 0x40: #define subent(n) entry[perf[2] + ((n) * perf[3])] perflvl->fanspeed = 0; /*XXX*/ perflvl->voltage = entry[2]; perflvl->core = (ROM16(subent(0)) & 0xfff) * 1000; perflvl->shader = (ROM16(subent(1)) & 0xfff) * 1000; perflvl->memory = (ROM16(subent(2)) & 0xfff) * 1000; break; } /* make sure vid is valid */ if (pm->voltage.supported && perflvl->voltage) { vid = nouveau_volt_vid_lookup(dev, perflvl->voltage); if (vid < 0) { NV_DEBUG(dev, "drop perflvl %d, bad vid\n", i); entry += recordlen; continue; } } snprintf(perflvl->name, sizeof(perflvl->name), "performance_level_%d", i); perflvl->id = i; pm->nr_perflvl++; entry += recordlen; } }
void nouveau_perf_init(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_pm_engine *pm = &dev_priv->engine.pm; struct nvbios *bios = &dev_priv->vbios; u8 *perf, ver, hdr, cnt, len; int ret, vid, i = -1; if (bios->type == NVBIOS_BMP && bios->data[bios->offset + 6] < 0x25) { legacy_perf_init(dev); return; } perf = nouveau_perf_table(dev, &ver); if (ver >= 0x20 && ver < 0x40) pm->fan.pwm_divisor = ROM16(perf[6]); while ((perf = nouveau_perf_entry(dev, ++i, &ver, &hdr, &cnt, &len))) { struct nouveau_pm_level *perflvl = &pm->perflvl[pm->nr_perflvl]; if (perf[0] == 0xff) continue; switch (ver) { case 0x12: case 0x13: case 0x15: perflvl->fanspeed = perf[55]; if (hdr > 56) perflvl->volt_min = perf[56]; perflvl->core = ROM32(perf[1]) * 10; perflvl->memory = ROM32(perf[5]) * 20; break; case 0x21: case 0x23: case 0x24: perflvl->fanspeed = perf[4]; perflvl->volt_min = perf[5]; perflvl->shader = ROM16(perf[6]) * 1000; perflvl->core = perflvl->shader; perflvl->core += (signed char)perf[8] * 1000; if (dev_priv->chipset == 0x49 || dev_priv->chipset == 0x4b) perflvl->memory = ROM16(perf[11]) * 1000; else perflvl->memory = ROM16(perf[11]) * 2000; break; case 0x25: perflvl->fanspeed = perf[4]; perflvl->volt_min = perf[5]; perflvl->core = ROM16(perf[6]) * 1000; perflvl->shader = ROM16(perf[10]) * 1000; perflvl->memory = ROM16(perf[12]) * 1000; break; case 0x30: perflvl->memscript = ROM16(perf[2]); case 0x35: perflvl->fanspeed = perf[6]; perflvl->volt_min = perf[7]; perflvl->core = ROM16(perf[8]) * 1000; perflvl->shader = ROM16(perf[10]) * 1000; perflvl->memory = ROM16(perf[12]) * 1000; perflvl->vdec = ROM16(perf[16]) * 1000; perflvl->dom6 = ROM16(perf[20]) * 1000; break; case 0x40: #define subent(n) ((ROM16(perf[hdr + (n) * len]) & 0xfff) * 1000) perflvl->fanspeed = 0; /*XXX*/ perflvl->volt_min = perf[2]; if (dev_priv->card_type == NV_50) { perflvl->core = subent(0); perflvl->shader = subent(1); perflvl->memory = subent(2); perflvl->vdec = subent(3); perflvl->unka0 = subent(4); } else { perflvl->hub06 = subent(0); perflvl->hub01 = subent(1); perflvl->copy = subent(2); perflvl->shader = subent(3); perflvl->rop = subent(4); perflvl->memory = subent(5); perflvl->vdec = subent(6); perflvl->daemon = subent(10); perflvl->hub07 = subent(11); perflvl->core = perflvl->shader / 2; } break; } /* make sure vid is valid */ nouveau_perf_voltage(dev, perflvl); if (pm->voltage.supported && perflvl->volt_min) { vid = nouveau_volt_vid_lookup(dev, perflvl->volt_min); if (vid < 0) { NV_DEBUG(dev, "perflvl %d, bad vid\n", i); continue; } } /* get the corresponding memory timings */ ret = nouveau_mem_timing_calc(dev, perflvl->memory, &perflvl->timing); if (ret) { NV_DEBUG(dev, "perflvl %d, bad timing: %d\n", i, ret); continue; } snprintf(perflvl->name, sizeof(perflvl->name), "performance_level_%d", i); perflvl->id = i; snprintf(perflvl->profile.name, sizeof(perflvl->profile.name), "%d", perflvl->id); perflvl->profile.func = &nouveau_pm_static_profile_func; list_add_tail(&perflvl->profile.head, &pm->profiles); pm->nr_perflvl++; } }