void TwoWire::forceStop(void) {
//force a stop to release the bus
ROM_GPIOPinTypeGPIOOutput(g_uli2cBase[i2cModule],
g_uli2cSCLPins[i2cModule] | g_uli2cSDAPins[i2cModule]);
ROM_GPIOPinWrite(g_uli2cBase[i2cModule], g_uli2cSDAPins[i2cModule], 0);
ROM_GPIOPinWrite(g_uli2cBase[i2cModule],
g_uli2cSCLPins[i2cModule], g_uli2cSCLPins[i2cModule]);
ROM_GPIOPinWrite(g_uli2cBase[i2cModule],
g_uli2cSDAPins[i2cModule], g_uli2cSDAPins[i2cModule]);
ROM_GPIOPinTypeI2C(g_uli2cBase[i2cModule], g_uli2cSDAPins[i2cModule]);
ROM_GPIOPinTypeI2CSCL(g_uli2cBase[i2cModule], g_uli2cSCLPins[i2cModule]);
//reset I2C controller
//without resetting the I2C controller, the I2C module will
//bring the bus back to it's erroneous state
ROM_SysCtlPeripheralReset(g_uli2cPeriph[i2cModule]);
while(!ROM_SysCtlPeripheralReady(g_uli2cPeriph[i2cModule]));
ROM_I2CMasterInitExpClk(MASTER_BASE, F_CPU, speedMode);//Bus speed
if(speedMode==I2C_SPEED_FASTMODE_PLUS)//Force 1Mhz
{
uint32_t ui32TPR = ((F_CPU + (2 * 10 * 1000000l) - 1) / (2 * 10 * 1000000l)) - 1;
HWREG(MASTER_BASE + I2C_O_MTPR) = ui32TPR;
}
}
void i2c_0_init()
{
//enable I2C module 0
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_I2C0);
//reset module
ROM_SysCtlPeripheralReset(SYSCTL_PERIPH_I2C0);
//enable GPIO peripheral that contains I2C 0
// SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);
// Configure the pin muxing for I2C0 functions on port B2 and B3.
ROM_GPIOPinConfigure(GPIO_PIN_2);
ROM_GPIOPinConfigure(GPIO_PIN_3);
// Select the I2C function for these pins.
GPIOPinTypeI2CSCL(GPIO_PORTB_BASE, GPIO_PIN_2);
GPIOPinTypeI2C(GPIO_PORTB_BASE, GPIO_PIN_3);
// Enable and initialize the I2C0 master module. Use the system clock for
// the I2C0 module. The last parameter sets the I2C data transfer rate.
// If false the data rate is set to 100kbps and if true the data rate will
// be set to 400kbps.
ROM_I2CMasterInitExpClk(I2C0_BASE, SysCtlClockGet(), true);
//clear I2C FIFOs
// HWREG(I2C0_BASE + I2C_O_FIFOCTL) = 80008000;
}
/*
Set up I2C pins and clock slow/fast
rate400 true = 400KHz, false 100KHz
*/
void MasterI2C0Init(int rate400)
{
//I2CMasterEnable(I2C0_MASTER_BASE); // causes fault
//
// Enable the I2C and GPIO port B blocks as they are needed by this driver.
//
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_I2C0);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);
//
// Configure the I2C SCL and SDA pins for I2C operation.
//
GPIOPinTypeI2CSCL(GPIO_PORTB_BASE, GPIO_PIN_2);
GPIOPinTypeI2C(GPIO_PORTB_BASE, GPIO_PIN_3);
GPIOPinConfigure(GPIO_PB2_I2C0SCL);
GPIOPinConfigure(GPIO_PB3_I2C0SDA);
//
// Initialize the I2C master.
//
ROM_I2CMasterInitExpClk(I2C0_MASTER_BASE, SysCtlClockGet(), rate400);
// Register interrupt handler
// or we could just edit the startup.c file
//I2CIntRegister(I2C0_MASTER_BASE,I2C0IntHandler);
//
// Enable the I2C interrupt.
//
ROM_IntEnable(INT_I2C0); // already done via I2CIntRegister
//
// Enable the I2C master interrupt.
//
ROM_I2CMasterIntEnable(I2C0_MASTER_BASE);
}
//Initialize as a master
void TwoWire::begin(void)
{
if(i2cModule == NOT_ACTIVE) {
i2cModule = BOOST_PACK_WIRE;
}
ROM_SysCtlPeripheralEnable(g_uli2cPeriph[i2cModule]);
//Configure GPIO pins for I2C operation
ROM_GPIOPinConfigure(g_uli2cConfig[i2cModule][0]);
ROM_GPIOPinConfigure(g_uli2cConfig[i2cModule][1]);
ROM_GPIOPinTypeI2C(g_uli2cBase[i2cModule], g_uli2cSDAPins[i2cModule]);
ROM_GPIOPinTypeI2CSCL(g_uli2cBase[i2cModule], g_uli2cSCLPins[i2cModule]);
ROM_I2CMasterInitExpClk(MASTER_BASE, F_CPU, speedMode);//Bus speed
if(speedMode==I2C_SPEED_FASTMODE_PLUS)//Force 1Mhz
{
uint32_t ui32TPR = ((F_CPU + (2 * 10 * 1000000l) - 1) / (2 * 10 * 1000000l)) - 1;
HWREG(MASTER_BASE + I2C_O_MTPR) = ui32TPR;
}
//force a stop condition
if(!ROM_GPIOPinRead(g_uli2cBase[i2cModule], g_uli2cSCLPins[i2cModule]))
forceStop();
//Handle any startup issues by pulsing SCL
if(ROM_I2CMasterBusBusy(MASTER_BASE) || ROM_I2CMasterErr(MASTER_BASE)
|| !ROM_GPIOPinRead(g_uli2cBase[i2cModule], g_uli2cSCLPins[i2cModule])) {
uint8_t doI = 0;
ROM_GPIOPinTypeGPIOOutput(g_uli2cBase[i2cModule], g_uli2cSCLPins[i2cModule]);
unsigned long mask = 0;
do {
for(unsigned long i = 0; i < 10 ; i++) {
if(speedMode==I2C_SPEED_FASTMODE_PLUS)
ROM_SysCtlDelay(F_CPU/1000000/3);//1000Hz=desired frequency, delay iteration=3 cycles
else if(speedMode==I2C_SPEED_FASTMODE)
ROM_SysCtlDelay(F_CPU/400000/3);//400Hz=desired frequency, delay iteration=3 cycles
else
ROM_SysCtlDelay(F_CPU/100000/3);//100Hz=desired frequency, delay iteration=3 cycles
mask = (i%2) ? g_uli2cSCLPins[i2cModule] : 0;
ROM_GPIOPinWrite(g_uli2cBase[i2cModule], g_uli2cSCLPins[i2cModule], mask);
}
doI++;
} while(ROM_I2CMasterBusBusy(MASTER_BASE) && doI < 100);
ROM_GPIOPinTypeI2CSCL(g_uli2cBase[i2cModule], g_uli2cSCLPins[i2cModule]);
if(!ROM_GPIOPinRead(g_uli2cBase[i2cModule], g_uli2cSCLPins[i2cModule]))
forceStop();
}
}
void Init_I2C(void)
{
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_I2C0);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);
ROM_GPIOPinConfigure(GPIO_PB2_I2C0SCL);
ROM_GPIOPinConfigure(GPIO_PB3_I2C0SDA);
ROM_GPIOPinTypeI2C(GPIO_PORTB_BASE, GPIO_PIN_3);
GPIOPinTypeI2CSCL(GPIO_PORTB_BASE, GPIO_PIN_2);
ROM_GPIOPadConfigSet(GPIO_PORTB_BASE, GPIO_PIN_2, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
ROM_GPIOPadConfigSet(GPIO_PORTB_BASE, GPIO_PIN_3, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_OD);
ROM_I2CMasterInitExpClk(I2C0_BASE,ROM_SysCtlClockGet(),true);
SysCtlDelay(500000);
ROM_I2CMasterEnable(I2C0_BASE);
}
//*****************************************************************************
//
//! Initializes and enables the specified I2C block.
//!
//! \param I2C_PORT is the I2C peripheral to be used.
//! \param ulI2CSpeed defines the normal (100kbps) or fast (400kbps) I2C mode.
//!
//! This function enables the specified I2C block and sets it up to run at
//! the either 100kbps or 400kbps. If the \e ulI2CSpeed is false, the I2C will
//! run at 100kbps and if true, then the I2C will run at 400kbps. The
//! \e I2C_PORT parameter can be one of the following values:
//!
//! \return None.
//
//*****************************************************************************
void SetupI2C(void)
{
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
GPIOPinTypeI2CSCL(GPIO_PORTA_BASE, GPIO_PIN_6);
ROM_GPIOPinTypeI2C(GPIO_PORTA_BASE, GPIO_PIN_7);
ROM_GPIOPinConfigure(GPIO_PA6_I2C1SCL);
ROM_GPIOPinConfigure(GPIO_PA7_I2C1SDA);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_I2C1);
ROM_I2CMasterInitExpClk(I2C_PORT, SysCtlClockGet(), 1); // 1 : 400Khz, 0 : 100Khz
}
void ConfigureI2C3(void){
// Enable peripherals used by I2C
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_I2C3);
// Setup GPIO
ROM_GPIOPinTypeI2CSCL(GPIO_PORTD_BASE, GPIO_PIN_0);
ROM_GPIOPinTypeI2C(GPIO_PORTD_BASE, GPIO_PIN_1);
// Set GPIO D0 and D1 as SCL and SDA
ROM_GPIOPinConfigure(GPIO_PD0_I2C3SCL);
ROM_GPIOPinConfigure(GPIO_PD1_I2C3SDA);
// Initialize as master - 'true' for fastmode, 'false' for regular
ROM_I2CMasterInitExpClk(I2C3_BASE, ROM_SysCtlClockGet(), true);
}
//Initialize as a master
void TwoWire::begin(void)
{
pinMode(RED_LED, OUTPUT);
if(i2cModule == NOT_ACTIVE) {
i2cModule = BOOST_PACK_WIRE;
}
ROM_SysCtlPeripheralEnable(g_uli2cPeriph[i2cModule]);
//Configure GPIO pins for I2C operation
ROM_GPIOPinConfigure(g_uli2cConfig[i2cModule][0]);
ROM_GPIOPinConfigure(g_uli2cConfig[i2cModule][1]);
ROM_GPIOPinTypeI2C(g_uli2cBase[i2cModule], g_uli2cSDAPins[i2cModule]);
ROM_GPIOPinTypeI2CSCL(g_uli2cBase[i2cModule], g_uli2cSCLPins[i2cModule]);
ROM_I2CMasterInitExpClk(MASTER_BASE, F_CPU, false);//max bus speed=400kHz for gyroscope
//force a stop condition
if(!ROM_GPIOPinRead(g_uli2cBase[i2cModule], g_uli2cSCLPins[i2cModule]))
forceStop();
//Handle any startup issues by pulsing SCL
if(ROM_I2CMasterBusBusy(MASTER_BASE) || ROM_I2CMasterErr(MASTER_BASE)
|| !ROM_GPIOPinRead(g_uli2cBase[i2cModule], g_uli2cSCLPins[i2cModule])){
uint8_t doI = 0;
ROM_GPIOPinTypeGPIOOutput(g_uli2cBase[i2cModule], g_uli2cSCLPins[i2cModule]);
unsigned long mask = 0;
do{
for(unsigned long i = 0; i < 10 ; i++) {
ROM_SysCtlDelay(F_CPU/100000/3);//100Hz=desired frequency, delay iteration=3 cycles
mask = (i%2) ? g_uli2cSCLPins[i2cModule] : 0;
ROM_GPIOPinWrite(g_uli2cBase[i2cModule], g_uli2cSCLPins[i2cModule], mask);
}
doI++;
}while(ROM_I2CMasterBusBusy(MASTER_BASE) && doI < 100);
ROM_GPIOPinTypeI2CSCL(g_uli2cBase[i2cModule], g_uli2cSCLPins[i2cModule]);
if(!ROM_GPIOPinRead(g_uli2cBase[i2cModule], g_uli2cSCLPins[i2cModule]))
forceStop();
}
}
void TwoWire::forceStop(void) {
//force a stop to release the bus
ROM_GPIOPinTypeGPIOOutput(g_uli2cBase[i2cModule],
g_uli2cSCLPins[i2cModule] | g_uli2cSDAPins[i2cModule]);
ROM_GPIOPinWrite(g_uli2cBase[i2cModule], g_uli2cSDAPins[i2cModule], 0);
ROM_GPIOPinWrite(g_uli2cBase[i2cModule],
g_uli2cSCLPins[i2cModule], g_uli2cSCLPins[i2cModule]);
ROM_GPIOPinWrite(g_uli2cBase[i2cModule],
g_uli2cSDAPins[i2cModule], g_uli2cSDAPins[i2cModule]);
ROM_GPIOPinTypeI2C(g_uli2cBase[i2cModule], g_uli2cSDAPins[i2cModule]);
ROM_GPIOPinTypeI2CSCL(g_uli2cBase[i2cModule], g_uli2cSCLPins[i2cModule]);
//reset I2C controller
//without resetting the I2C controller, the I2C module will
//bring the bus back to it's erroneous state
ROM_SysCtlPeripheralReset(g_uli2cPeriph[i2cModule]);
while(!ROM_SysCtlPeripheralReady(g_uli2cPeriph[i2cModule]));
ROM_I2CMasterInitExpClk(MASTER_BASE, F_CPU, false);
}
//*****************************************************************************
//
//! Initializes and enables the specified I2C block.
//!
//! \param ACCEL_I2C_MASTER_BASE is the I2C peripheral to be used.
//! \param ulI2CSpeed defines the normal (100kbps) or fast (400kbps) I2C mode.
//!
//! This function enables the specified I2C block and sets it up to run at
//! the either 100kbps or 400kbps. If the \e ulI2CSpeed is false, the I2C will
//! run at 100kbps and if true, then the I2C will run at 400kbps. The
//! \e ACCEL_I2C_MASTER_BASE parameter can be one of the following values:
//!
//! \return None.
//
//*****************************************************************************
void i2c_Config(void) {
// I2C1 is used with PortA[7:6].
SysCtlPeripheralEnable(ACCEL_I2C_PHERIPHERAL);
SysCtlPeripheralEnable(ACCEL_PHERIPHERAL);
GPIOPinConfigure(ACCEL_SCL_PIN_CONF);
GPIOPinTypeI2CSCL(ACCEL_I2C_PORT, ACCEL_SCL_PIN);
GPIOPinConfigure(ACCEL_SDA_PIN_CONF);
GPIOPinTypeI2CSCL(ACCEL_I2C_PORT, ACCEL_SDA_PIN);
// GPIOPinTypeI2CSCL(ACCEL_I2C_PORT, ACCEL_SCL_PIN);
// ROM_GPIOPinTypeI2C(ACCEL_I2C_PORT,ACCEL_SDA_PIN );
//
// ROM_GPIOPinConfigure(ACCEL_SCL_PIN_CONF);
// ROM_GPIOPinConfigure(ACCEL_SDA_PIN_CONF);
//
// ROM_SysCtlPeripheralEnable(ACCEL_I2C_PHERIPHERAL);
//
ROM_I2CMasterInitExpClk(ACCEL_I2C_MASTER_BASE, SysCtlClockGet(), 1); // 1 : 400Khz, 0 : 100Khz
}
//*****************************************************************************
//
//! Initializes the TLV320AIC3107 DAC.
//!
//! This function initializes the I2C interface and the TLV320AIC3107 DAC. It
//! must be called prior to any other API in the DAC module.
//!
//! \return Returns \b true on success or \b false on failure.
//
//*****************************************************************************
tBoolean
DACInit(void)
{
tBoolean bRetcode;
unsigned char ucTest;
//
// Enable the GPIO port containing the I2C pins and set the SDA pin as a
// GPIO input for now and engage a weak pull-down. If the daughter board
// is present, the pull-up on the board should easily overwhelm
// the pull-down and we should read the line state as high.
//
ROM_SysCtlPeripheralEnable(DAC_I2CSCL_GPIO_PERIPH);
ROM_GPIOPinTypeGPIOInput(DAC_I2CSCL_GPIO_PORT, DAC_I2CSDA_PIN);
ROM_GPIOPadConfigSet(DAC_I2CSCL_GPIO_PORT, DAC_I2CSDA_PIN,
GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPD);
//
// Enable the I2C peripheral.
//
ROM_SysCtlPeripheralEnable(DAC_I2C_PERIPH);
//
// Delay a while to ensure that we read a stable value from the SDA
// GPIO pin. If we read too quickly, the result is unpredictable.
// This delay is around 2mS.
//
SysCtlDelay(ROM_SysCtlClockGet() / (3 * 500));
//
// Configure the pin mux.
//
GPIOPinConfigure(GPIO_PB2_I2C0SCL);
GPIOPinConfigure(GPIO_PB3_I2C0SDA);
//
// Configure the I2C SCL and SDA pins for I2C operation.
//
ROM_GPIOPinTypeI2C(DAC_I2CSCL_GPIO_PORT, DAC_I2CSCL_PIN | DAC_I2CSDA_PIN);
//
// Initialize the I2C master.
//
ROM_I2CMasterInitExpClk(DAC_I2C_MASTER_BASE, SysCtlClockGet(), 0);
//
// Enable the I2C peripheral.
//
ROM_SysCtlPeripheralEnable(DAC_RESET_GPIO_PERIPH);
//
// Configure the PH2 as a GPIO output.
//
ROM_GPIOPinTypeGPIOOutput(DAC_RESET_GPIO_PORT, DAC_RESET_PIN);
//
// Reset the DAC
//
ROM_GPIOPinWrite(DAC_RESET_GPIO_PORT , DAC_RESET_PIN, 0);
ROM_GPIOPinWrite(DAC_RESET_GPIO_PORT , DAC_RESET_PIN, DAC_RESET_PIN);
//
// Reset the DAC. Check the return code on this call since we use it to
// indicate whether or not the DAC is present. If the register write
// fails, we assume the I2S daughter board and DAC are not present and
// return false.
//
bRetcode = DACWriteRegister(TI_SOFTWARE_RESET_R, 0x80);
if(!bRetcode)
{
return(bRetcode);
}
//
// Codec Datapath Setup Register
// ----------------------
// D7 = 1 : Fsref = 44.1-kHz
// D6 = 0 : ADC Dual rate mode is disabled
// D5 = 0 : DAC Dual rate mode is disabled
// D[4:3] = 11 : Left DAC datapath plays mono mix of left and right channel
// input data
// D[1:1] = 00 : Right DAC datapath is off
// D0 = 0 : reserved
// ----------------------
// D[7:0] = 10011010
//
DACWriteRegister(TI_CODEC_DATAPATH_R, 0x98);
//
// Audio Serial Data Interface Control Register A
// ----------------------
// D7 = 0 : BCLK is an input (slave mode)
// D6 = 0 : WCLK (or GPIO1 if programmed as WCLK) is an input
// (slave mode)
// D5 = 0 : Do not 3-state DOUT when valid data is not being sent
// D4 = 0 : BCLK / WCLK (or GPIO1 if programmed as WCLK) will not
// continue to be transmitted when running in master mode if codec is powered down
// D3 = 0 : Reserved.
// D2 = 0 : Disable 3-D digital effect processing
// D[1:0] = 00 : reserved
// ----------------------
// D[7:0] = 00000000
//
DACWriteRegister(TI_ASDI_CTL_A_R, 0x00);
//
// Audio Serial Data Interface Control Register B
// ----------------------
// D[7:6] = 00 : Serial data bus uses I2S mode
// D[5:4] = 00 : Audio data word length = 16-bits
// D3 = 0 : Continuous-transfer mode used to determine master mode
// bit clock rate
// D2 = 0 : Don't Care
// D1 = 0 : Don't Care
// D0 = 0 : Re-Sync is done without soft-muting the channel. (ADC/DAC)
// ----------------------
// D[7:0] = 00000000
//
DACWriteRegister(TI_ASDI_CTL_B_R, 0x00);
//
// Audio Serial Data Interface Control Register C
// ----------------------
// D[7:0] = 00000000 : Data offset = 0 bit clocks
// ----------------------
// D[7:0] = 00000000
//
DACWriteRegister(TI_ASDI_CTL_C_R, 0x00);
//
// DAC Power and Output Driver Control Register
// ----------------------
// D7 = 1 : Left DAC is powered up
// D6 = 1 : Right DAC is powered up
// D[5:4] = 00 : HPCOM configured as differential of HPLOUT
// D[3:0] = 0 : reserved
// ----------------------
// D[7:0] = 11000000
//
DACWriteRegister(TI_DACPOD_CTL_R, 0xC0);
//
// Left DAC Digital Volume Control Register
// ----------------------
// D7 = 0 : The left DAC channel is not muted
// D[6:0] = 0 :
// ----------------------
// D[7:0] =
//
DACWriteRegister(TI_LEFT_DAC_DIG_VOL_CTL_R, 0x00);
//
// Right DAC Digital Volume Control Register
// ----------------------
// D7 = 0 : The right DAC channel is not muted
// D[6:0] = 0 :
// ----------------------
// D[7:0] =
//
DACWriteRegister(TI_RIGHT_DAC_DIG_VOL_CTL_R, 0x00);
//
// DAC_L1 to LEFT_LOP Volume Control Register
// ----------------------
// D7 = 1 : DAC_L1 is routed to LEFT_LOP
// D[6:0] = 0110010 (50) : Gain
// ----------------------
// D[7:0] = 10110010
//
DACWriteRegister(TI_DAC_L1_LEFT_LOP_VOL_CTL_R, 0xA0);
//
// LEFT_LOP Output Level Control Register
// ----------------------
// D[7:4] = 0110 : Output level control = 6 dB
// D3 = 1 : LEFT_LOP is not muted
// D2 = 0 : Reserved.
// D1 = 0 : All programmed gains to LEFT_LOP have been applied
// D0 = 1 : LEFT_LOP is fully powered up
// ----------------------
// D[7:0] = 00001001
//
DACWriteRegister(TI_LEFT_LOP_OUTPUT_LVL_CTL_R, 0xC9);
//
// From the TLV320AIC3107 datasheet:
// The following initialization sequence must be written to the AIC3107
// registers prior to enabling the class-D amplifier:
// register data:
// 1. 0x00 0x0D
// 2. 0x0D 0x0D
// 3. 0x08 0x5C
// 4. 0x08 0x5D
// 5. 0x08 0x5C
// 6. 0x00 0x00
//
DACWriteRegister(0x00, 0x0D);
DACWriteRegister(0x0D, 0x0D);
DACWriteRegister(0x08, 0x5C);
DACWriteRegister(0x08, 0x5D);
DACWriteRegister(0x08, 0x5C);
DACWriteRegister(0x00, 0x00);
//
// Class-D and Bypass Switch Control Register
// ----------------------
// D[7:6] = 01 : Left Class-D amplifier gain = 6.0 dB
// D[5:4] = 00 : Right Class-D amplifier gain = 0.0 dB
// D3 = 1 : enable left class-D channel
// D2 = 0 : disable right class-D channel
// D1 = 0 : disable bypass switch
// D0 = 0 : disable bypass switch bootstrap clock
// ----------------------
// D[7:0] = 01001000
//
DACWriteRegister(TI_CLASSD_BYPASS_SWITCH_CTL_R, 0x40);
//
//Read Module Power Status Register
//
bRetcode = DACReadRegister(TI_MODULE_PWR_STAT_R, &ucTest);
if(!bRetcode)
{
return(bRetcode);
}
return(true);
}
