//***************************************************************************** // // Initializes the uDMA software channel to perform a memory to memory uDMA // transfer. // //***************************************************************************** void InitSWTransfer(void) { unsigned int uIdx; // // Fill the source memory buffer with a simple incrementing pattern. // for(uIdx = 0; uIdx < MEM_BUFFER_SIZE; uIdx++) { g_ulSrcBuf[uIdx] = uIdx; } // // Enable interrupts from the uDMA software channel. // ROM_IntEnable(INT_UDMA); // // Put the attributes in a known state for the uDMA software channel. // These should already be disabled by default. // ROM_uDMAChannelAttributeDisable(UDMA_CHANNEL_SW, UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT | (UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK)); // // Configure the control parameters for the SW channel. The SW channel // will be used to transfer between two memory buffers, 32 bits at a time. // Therefore the data size is 32 bits, and the address increment is 32 bits // for both source and destination. The arbitration size will be set to 8, // which causes the uDMA controller to rearbitrate after 8 items are // transferred. This keeps this channel from hogging the uDMA controller // once the transfer is started, and allows other channels cycles if they // are higher priority. // ROM_uDMAChannelControlSet(UDMA_CHANNEL_SW | UDMA_PRI_SELECT, UDMA_SIZE_32 | UDMA_SRC_INC_32 | UDMA_DST_INC_32 | UDMA_ARB_8); // // Set up the transfer parameters for the software channel. This will // configure the transfer buffers and the transfer size. Auto mode must be // used for software transfers. // ROM_uDMAChannelTransferSet(UDMA_CHANNEL_SW | UDMA_PRI_SELECT, UDMA_MODE_AUTO, g_ulSrcBuf, g_ulDstBuf, MEM_BUFFER_SIZE); // // Now the software channel is primed to start a transfer. The channel // must be enabled. For software based transfers, a request must be // issued. After this, the uDMA memory transfer begins. // ROM_uDMAChannelEnable(UDMA_CHANNEL_SW); ROM_uDMAChannelRequest(UDMA_CHANNEL_SW); }
//***************************************************************************** // // The interrupt handler for uDMA interrupts from the memory channel. This // interrupt will increment a counter, and then restart another memory // transfer. // //***************************************************************************** void uDMAIntHandler(void) { uint32_t ui32Mode; // // Check for the primary control structure to indicate complete. // ui32Mode = ROM_uDMAChannelModeGet(UDMA_CHANNEL_SW); if(ui32Mode == UDMA_MODE_STOP) { // // Increment the count of completed transfers. // g_ui32MemXferCount++; // // Configure it for another transfer. // ROM_uDMAChannelTransferSet(UDMA_CHANNEL_SW, UDMA_MODE_AUTO, g_ui32SrcBuf, g_ui32DstBuf, MEM_BUFFER_SIZE); // // Initiate another transfer. // ROM_uDMAChannelEnable(UDMA_CHANNEL_SW); ROM_uDMAChannelRequest(UDMA_CHANNEL_SW); } // // If the channel is not stopped, then something is wrong. // else { g_ui32BadISR++; } }
//***************************************************************************** // // Process data to produce a CRC-32 checksum. // //***************************************************************************** uint32_t CRC32DataProcess(uint32_t *pui32Data, uint32_t ui32Length, uint32_t ui32Seed, bool bUseDMA) { uint32_t ui32Result; // // Perform a soft reset. // ROM_SysCtlPeripheralReset(SYSCTL_PERIPH_CCM0); while(!ROM_SysCtlPeripheralReady(SYSCTL_PERIPH_CCM0)) { } // // Configure the CRC engine. // ROM_CRCConfigSet(CCM0_BASE, (CRC_CFG_INIT_SEED | CRC_CFG_TYPE_P4C11DB7 | CRC_CFG_SIZE_32BIT)); // // Write the seed. // ROM_CRCSeedSet(CCM0_BASE, ui32Seed); // // Generate CRC using uDMA to copy data. // if(bUseDMA) { // // Setup the DMA module to copy data in. // ROM_uDMAChannelAssign(UDMA_CH30_SW); ROM_uDMAChannelAttributeDisable(UDMA_CH30_SW, UDMA_ATTR_ALTSELECT | UDMA_ATTR_USEBURST | UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK); ROM_uDMAChannelControlSet(UDMA_CH30_SW | UDMA_PRI_SELECT, UDMA_SIZE_32 | UDMA_SRC_INC_32 | UDMA_DST_INC_NONE | UDMA_ARB_1 | UDMA_DST_PROT_PRIV); ROM_uDMAChannelTransferSet(UDMA_CH30_SW | UDMA_PRI_SELECT, UDMA_MODE_AUTO, (void *)g_pui32RandomData, (void *)(CCM0_BASE + CCM_O_CRCDIN), ui32Length); ROM_uDMAChannelEnable(UDMA_CH30_SW); UARTprintf(" Data in DMA request enabled.\n"); // // Start the uDMA. // ROM_uDMAChannelRequest(UDMA_CH30_SW | UDMA_PRI_SELECT); // // Wait for the transfer to finish. // while(ROM_uDMAChannelIsEnabled(UDMA_CH30_SW)) { } // // Read the result. // ui32Result = ROM_CRCResultRead(CCM0_BASE, false); } // // Generate CRC using CPU to copy data. // else { ui32Result = ROM_CRCDataProcess(CCM0_BASE, g_pui32RandomData, ui32Length, false); } return(ui32Result); }