static void test(void)
{
rtems_status_code sc;
rtems_id task_id;
Thread_Control *executing;
Scheduler_SMP_Node *node;
size_t i;
size_t j;
size_t k;
sc = rtems_task_create(
rtems_build_name('T', 'A', 'S', 'K'),
3,
RTEMS_MINIMUM_STACK_SIZE,
RTEMS_DEFAULT_MODES,
RTEMS_DEFAULT_ATTRIBUTES,
&task_id
);
rtems_test_assert(sc == RTEMS_SUCCESSFUL);
sc = rtems_task_start(task_id, task, 0);
rtems_test_assert(sc == RTEMS_SUCCESSFUL);
_Thread_Disable_dispatch();
executing = _Thread_Executing;
node = _Scheduler_SMP_Node_get( executing );
for (i = 0; i < RTEMS_ARRAY_SIZE(states); ++i) {
for (j = 0; j < RTEMS_ARRAY_SIZE(priorities); ++j) {
for (k = 0; k < RTEMS_ARRAY_SIZE(prepend_it); ++k) {
test_case(
executing,
node,
states[i],
priorities[j],
prepend_it[k],
states[j]
);
}
}
}
_Thread_Change_priority(executing, 1, true);
rtems_test_assert(node->state == SCHEDULER_SMP_NODE_SCHEDULED);
_Thread_Enable_dispatch();
sc = rtems_task_delete(task_id);
rtems_test_assert(sc == RTEMS_SUCCESSFUL);
}
rtems_status_code console_initialize(
rtems_device_major_number major,
rtems_device_minor_number minor,
void *arg
)
{
size_t i;
rtems_termios_initialize();
for (i = 0; i < RTEMS_ARRAY_SIZE(atsam_usart_instances); ++i) {
char usart[] = "/dev/ttyUSARTX";
usart[sizeof(usart) - 2] = (char) ('0' + i);
rtems_termios_device_install(
&usart[0],
&atsam_usart_handler,
NULL,
&atsam_usart_instances[i].base
);
#if ATSAM_CONSOLE_DEVICE_TYPE == 0
if (i == ATSAM_CONSOLE_DEVICE_INDEX) {
atsam_usart_instances[i].console = true;
link(&usart[0], CONSOLE_DEVICE_NAME);
}
#endif
}
for (i = 0; i < RTEMS_ARRAY_SIZE(atsam_uart_instances); ++i) {
char uart[] = "/dev/ttyUARTX";
uart[sizeof(uart) - 2] = (char) ('0' + i);
rtems_termios_device_install(
&uart[0],
&atsam_uart_handler,
NULL,
&atsam_uart_instances[i].base
);
#if ATSAM_CONSOLE_DEVICE_TYPE == 1
if (i == ATSAM_CONSOLE_DEVICE_INDEX) {
atsam_uart_instances[i].console = true;
link(&usart[0], CONSOLE_DEVICE_NAME);
}
#endif
}
return RTEMS_SUCCESSFUL;
}
rtems_status_code console_initialize(
rtems_device_major_number major,
rtems_device_minor_number minor,
void *arg
)
{
size_t i;
rtems_termios_initialize();
for (i = 0; i < RTEMS_ARRAY_SIZE(zynqmp_uart_instances); ++i) {
char uart[] = "/dev/ttySX";
uart[sizeof(uart) - 2] = (char) ('0' + i);
rtems_termios_device_install(
&uart[0],
&zynq_uart_handler,
NULL,
&zynqmp_uart_instances[i].base
);
if (i == BSP_CONSOLE_MINOR) {
link(&uart[0], CONSOLE_DEVICE_NAME);
}
}
return RTEMS_SUCCESSFUL;
}
static void test_unblock_op(void)
{
rtems_status_code sc;
rtems_id task_id;
Thread_Control *executing;
Scheduler_SMP_Node *executing_node;
Thread_Control *other;
size_t i;
task_id = start_task(3);
_Thread_Disable_dispatch();
executing = _Thread_Executing;
executing_node = _Scheduler_SMP_Thread_get_node(executing);
other = get_thread_by_id(task_id);
for (i = 0; i < RTEMS_ARRAY_SIZE(states); ++i) {
test_case_unblock_op(
executing,
executing_node,
other,
states[i]
);
}
_Thread_Change_priority(executing, 1, true);
rtems_test_assert(executing_node->state == SCHEDULER_SMP_NODE_SCHEDULED);
_Thread_Enable_dispatch();
sc = rtems_task_delete(task_id);
rtems_test_assert(sc == RTEMS_SUCCESSFUL);
}
static void switch_priorities(test_context *self)
{
rtems_status_code sc;
size_t index = self->task_index;
size_t next = (index + 1) % RTEMS_ARRAY_SIZE(self->validate_tasks);
size_t task_current_high = index;
size_t task_next_high = next;
rtems_task_priority priority;
self->task_index = next;
sc = rtems_task_set_priority(
self->validate_tasks[task_next_high],
PRIORITY_HIGH,
&priority
);
rtems_test_assert(sc == RTEMS_SUCCESSFUL);
sc = rtems_task_set_priority(
self->validate_tasks[task_current_high],
PRIORITY_LOW,
&priority
);
rtems_test_assert(sc == RTEMS_SUCCESSFUL);
}
static void test_chain_insert_ordered( void )
{
Chain_Control chain = CHAIN_INITIALIZER_EMPTY(chain);
Chain_Node nodes[5];
const Chain_Node *tail;
const Chain_Node *node;
size_t n = RTEMS_ARRAY_SIZE( nodes );
size_t i = 0;
puts( "INIT - Verify _Chain_Insert_ordered_unprotected" );
_Chain_Insert_ordered_unprotected( &chain, &nodes[4], test_order );
_Chain_Insert_ordered_unprotected( &chain, &nodes[2], test_order );
_Chain_Insert_ordered_unprotected( &chain, &nodes[0], test_order );
_Chain_Insert_ordered_unprotected( &chain, &nodes[3], test_order );
_Chain_Insert_ordered_unprotected( &chain, &nodes[1], test_order );
tail = _Chain_Immutable_tail( &chain );
node = _Chain_Immutable_first( &chain );
while ( node != tail && i < n ) {
rtems_test_assert( node == &nodes[ i ] );
++i;
node = _Chain_Immutable_next( node );
}
rtems_test_assert( i == n );
}
void tms570_pinmux_init_by_list( void )
{
int pincnt = RTEMS_ARRAY_SIZE( tms570_pinmmr_init_list );
const uint32_t *pinfnc = tms570_pinmmr_init_list;
while ( pincnt-- )
tms570_bsp_pin_config_one( *(pinfnc++) );
}
/*
* Use a timer to execute the actions, since it runs with thread dispatching
* disabled. This is necessary to check the expected processor allocations.
*/
static void timer(rtems_id id, void *arg)
{
test_context *ctx;
rtems_status_code sc;
size_t i;
ctx = arg;
i = ctx->action_index;
if (i == 0) {
sc = rtems_task_suspend(ctx->master_id);
rtems_test_assert(sc == RTEMS_SUCCESSFUL);
}
if (i < RTEMS_ARRAY_SIZE(test_actions)) {
const test_action *action = &test_actions[i];
rtems_id task;
ctx->action_index = i + 1;
task = ctx->task_ids[action->index];
switch (action->kind) {
case KIND_SET_PRIORITY:
set_priority(task, action->data.priority);
break;
case KIND_SET_AFFINITY:
set_affinity(task, action->data.cpu_set);
break;
case KIND_BLOCK:
sc = rtems_task_suspend(task);
rtems_test_assert(sc == RTEMS_SUCCESSFUL);
break;
case KIND_UNBLOCK:
sc = rtems_task_resume(task);
rtems_test_assert(sc == RTEMS_SUCCESSFUL);
break;
default:
rtems_test_assert(action->kind == KIND_RESET);
reset(ctx);
break;
}
check_cpu_allocations(ctx, action);
sc = rtems_timer_reset(id);
rtems_test_assert(sc == RTEMS_SUCCESSFUL);
} else {
sc = rtems_task_resume(ctx->master_id);
rtems_test_assert(sc == RTEMS_SUCCESSFUL);
sc = rtems_event_transient_send(ctx->master_id);
rtems_test_assert(sc == RTEMS_SUCCESSFUL);
}
}
const char *rtems_fatal_source_text( rtems_fatal_source source )
{
size_t i = source;
const char *text = "?";
if ( i < RTEMS_ARRAY_SIZE( fatal_source_text ) ) {
text = fatal_source_text[ i ];
}
return text;
}
const char *rtems_internal_error_text( rtems_fatal_code error )
{
size_t i = error;
const char *text = "?";
if ( i < RTEMS_ARRAY_SIZE( internal_error_text ) ) {
text = internal_error_text[ i ];
}
return text;
}
static void test_change_priority(void)
{
rtems_status_code sc;
rtems_id task_id;
Thread_Control *executing;
Scheduler_SMP_Node *node;
size_t i;
size_t j;
size_t k;
task_id = start_task(3);
_Thread_Disable_dispatch();
executing = _Thread_Executing;
node = _Scheduler_SMP_Thread_get_node( executing );
for (i = 0; i < RTEMS_ARRAY_SIZE(states); ++i) {
for (j = 0; j < RTEMS_ARRAY_SIZE(priorities); ++j) {
for (k = 0; k < RTEMS_ARRAY_SIZE(prepend_it); ++k) {
test_case_change_priority(
executing,
node,
states[i],
priorities[j],
prepend_it[k],
states[j]
);
}
}
}
_Thread_Change_priority(executing, 1, true);
rtems_test_assert(node->state == SCHEDULER_SMP_NODE_SCHEDULED);
_Thread_Enable_dispatch();
sc = rtems_task_delete(task_id);
rtems_test_assert(sc == RTEMS_SUCCESSFUL);
}
static int test_transfer(i2c_bus *base, i2c_msg *msgs, uint32_t msg_count)
{
test_bus *bus = (test_bus *) base;
uint16_t addr;
test_device *dev;
addr = msgs[0].addr >> SPARE_ADDRESS_BITS;
if (addr >= RTEMS_ARRAY_SIZE(bus->devices)) {
return -EIO;
}
dev = bus->devices[addr];
return (*dev->transfer)(&bus->base, msgs, msg_count, dev);
}
static volatile qoriq_pic_src_cfg *get_src_cfg(rtems_vector_number vector)
{
uint32_t n = MIN(RTEMS_ARRAY_SIZE(qoriq.pic.ii_0), QORIQ_IRQ_EXT_BASE);
if (vector < n) {
return &qoriq.pic.ii_0 [vector];
} else if (vector < QORIQ_IRQ_EXT_BASE) {
return &qoriq.pic.ii_1 [vector - n];
} else {
uint32_t offs = ((uint32_t)
src_cfg_offsets [vector - QORIQ_IRQ_EXT_BASE]) << 4;
return (volatile qoriq_pic_src_cfg *) ((uint32_t) &qoriq.pic + offs);
}
}
BSP_START_TEXT_SECTION void zynq_setup_mmu_and_cache(void)
{
uint32_t ctrl = arm_cp15_start_setup_mmu_and_cache(
ARM_CP15_CTRL_A,
ARM_CP15_CTRL_AFE | ARM_CP15_CTRL_Z
);
arm_cp15_start_setup_translation_table_and_enable_mmu_and_cache(
ctrl,
(uint32_t *) bsp_translation_table_base,
ARM_MMU_DEFAULT_CLIENT_DOMAIN,
&zynq_mmu_config_table[0],
RTEMS_ARRAY_SIZE(zynq_mmu_config_table)
);
}
/**
* @brief Serial drivers init function
*
* Initialize all serial drivers specified in driver_context_table
*
* @param[in] major
* @param[in] minor
* @param[in] arg
* @retval RTEMS_SUCCESSFUL Initialization completed
*/
rtems_device_driver console_initialize(
rtems_device_major_number major,
rtems_device_minor_number minor,
void *arg
)
{
rtems_status_code sc;
#if CONSOLE_USE_INTERRUPTS
const rtems_termios_device_handler *handler = &tms570_sci_handler_interrupt;
#else
const rtems_termios_device_handler *handler = &tms570_sci_handler_polled;
#endif
/*
* Initialize the Termios infrastructure. If Termios has already
* been initialized by another device driver, then this call will
* have no effect.
*/
rtems_termios_initialize();
/* Initialize each device */
for (
minor = 0;
minor < RTEMS_ARRAY_SIZE(driver_context_table);
++minor
) {
tms570_sci_context *ctx = &driver_context_table[minor];
/*
* Install this device in the file system and Termios. In order
* to use the console (i.e. being able to do printf, scanf etc.
* on stdin, stdout and stderr), one device must be registered as
* "/dev/console" (CONSOLE_DEVICE_NAME).
*/
sc = rtems_termios_device_install(
ctx->device_name,
major,
minor,
handler,
NULL,
&ctx->base
);
if ( sc != RTEMS_SUCCESSFUL ) {
bsp_fatal(BSP_FATAL_CONSOLE_NO_DEV);
}
}
return RTEMS_SUCCESSFUL;
}
static uint64_t store(void)
{
rtems_counter_ticks a;
rtems_counter_ticks b;
rtems_counter_ticks d;
size_t i;
volatile int *vdata = &data[0];
a = rtems_counter_read();
for (i = 0; i < RTEMS_ARRAY_SIZE(data); ++i) {
vdata[i] = 0;
}
b = rtems_counter_read();
d = rtems_counter_difference(b, a);
return rtems_counter_ticks_to_nanoseconds(d);
}
static void
test_main(void)
{
const char name[] = "foobarclient";
int rv;
DNSQuestion question;
rtems_status_code sc;
rv = sethostname(&name[0], sizeof(name) - 1);
assert(rv == 0);
sc = rtems_mdns_initialize(254, &rr_cache[0], RTEMS_ARRAY_SIZE(rr_cache));
assert(sc == RTEMS_SUCCESSFUL);
foobar_register(&question);
rtems_task_delete(RTEMS_SELF);
assert(0);
}
static void test_chain_node_count(void)
{
rtems_chain_control chain;
rtems_chain_node nodes[3];
size_t count;
size_t i;
puts( "INIT - Verify rtems_chain_node_count_unprotected" );
rtems_chain_initialize_empty( &chain );
count = rtems_chain_node_count_unprotected( &chain );
rtems_test_assert( count == 0 );
for (i = 0; i < RTEMS_ARRAY_SIZE( nodes ); ++i) {
rtems_chain_append_unprotected( &chain, &nodes[i] );
count = rtems_chain_node_count_unprotected( &chain );
rtems_test_assert( count == i + 1 );
}
}
static BSP_START_TEXT_SECTION void setup_mmu_and_cache(void)
{
uint32_t ctrl = arm_cp15_start_setup_mmu_and_cache(
ARM_CP15_CTRL_I | ARM_CP15_CTRL_R | ARM_CP15_CTRL_C
| ARM_CP15_CTRL_V | ARM_CP15_CTRL_M,
ARM_CP15_CTRL_S | ARM_CP15_CTRL_A
);
arm_cp15_cache_invalidate();
#ifndef LPC32XX_DISABLE_MMU
arm_cp15_start_setup_translation_table_and_enable_mmu_and_cache(
ctrl,
(uint32_t *) bsp_translation_table_base,
LPC32XX_MMU_CLIENT_DOMAIN,
&lpc32xx_mmu_config_table [0],
RTEMS_ARRAY_SIZE(lpc32xx_mmu_config_table)
);
#endif
}
static uint32_t discover_processors(void)
{
#if defined(HAS_UBOOT)
return QORIQ_CPU_COUNT;
#elif defined(U_BOOT_USE_FDT)
const void *fdt = bsp_fdt_get();
int cpus = fdt_path_offset(fdt, "/cpus");
int node = fdt_first_subnode(fdt, cpus);
uint32_t cpu = 0;
uintptr_t last = 0;
uintptr_t begin = last - 1;
while (node >= 0) {
int len;
fdt64_t *addr_fdt = (fdt64_t *)
fdt_getprop(fdt, node, "cpu-release-addr", &len);
if (
addr_fdt != NULL
&& cpu < RTEMS_ARRAY_SIZE(qoriq_start_spin_table_addr)
) {
uintptr_t addr = (uintptr_t) fdt64_to_cpu(*addr_fdt);
if (addr < begin) {
begin = addr;
}
if (addr > last) {
last = addr;
}
qoriq_start_spin_table_addr[cpu] = (qoriq_start_spin_table *) addr;
++cpu;
}
node = fdt_next_subnode(fdt, node);
}
return cpu * QORIQ_THREAD_COUNT;
#endif
}
int atsam_register_spi_0(void)
{
static const Pin pins[] = {
PIN_SPI0_MISO,
PIN_SPI0_MOSI,
PIN_SPI0_NPCS0,
PIN_SPI0_NPCS1_1,
PIN_SPI0_NPCS1_2,
PIN_SPI0_NPCS2,
PIN_SPI0_NPCS3,
PIN_SPI0_CLOCK
};
return spi_bus_register_atsam(
ATSAM_SPI_0_BUS_PATH,
ID_SPI0,
SPI0,
pins,
RTEMS_ARRAY_SIZE(pins)
);
}
static void test_sha512(void)
{
size_t i;
printf("test SHA512\n");
for (i = 0; i < RTEMS_ARRAY_SIZE(test_vectors); ++i) {
SHA512_CTX ctx;
unsigned char r[64];
const char *s = test_vectors[i];
SHA512_Init(&ctx);
SHA512_Update(&ctx, s, strlen(s));
SHA512_Final(r, &ctx);
print_result(&r[0], sizeof(r));
rtems_test_assert(
memcmp(&r[0], &test_sha512_results[i][0], sizeof(r)) == 0
);
}
}
static int imx_i2c_set_clock(i2c_bus *base, unsigned long clock)
{
imx_i2c_bus *bus;
uint32_t ipg_clock;
uint16_t div;
size_t i;
const imx_i2c_clock_divisor *clock_divisor;
bus = (imx_i2c_bus *) base;
ipg_clock = imx_ccm_ipg_hz();
div = (uint16_t) ((ipg_clock + clock - 1) / clock);
for (i = 0; i < RTEMS_ARRAY_SIZE(imx_i2c_clock_divisor_table); ++i) {
clock_divisor = &imx_i2c_clock_divisor_table[i];
if (clock_divisor->divisor >= div) {
break;
}
}
bus->regs->ifdr = clock_divisor->ifdr;
return 0;
}
void rtems_resource_snapshot_take(rtems_resource_snapshot *snapshot)
{
uint32_t *active = &snapshot->active_posix_keys;
size_t i;
memset(snapshot, 0, sizeof(*snapshot));
_RTEMS_Lock_allocator();
_Thread_Kill_zombies();
get_heap_info(RTEMS_Malloc_Heap, &snapshot->heap_info);
get_heap_info(&_Workspace_Area, &snapshot->workspace_info);
for (i = 0; i < RTEMS_ARRAY_SIZE(objects_info_table); ++i) {
active [i] = _Objects_Active_count(objects_info_table[i]);
}
_RTEMS_Unlock_allocator();
snapshot->active_posix_key_value_pairs = get_active_posix_key_value_pairs();
snapshot->open_files = open_files();
}
static uint32_t discover_processors(void)
{
const void *fdt = bsp_fdt_get();
int cpus = fdt_path_offset(fdt, "/cpus");
int node = fdt_first_subnode(fdt, cpus);
uint32_t cpu = 0;
while (node >= 0 && cpu < RTEMS_ARRAY_SIZE(qoriq_start_spin_table_addr)) {
int len;
fdt64_t *addr_fdt = (fdt64_t *)
fdt_getprop(fdt, node, "cpu-release-addr", &len);
if (addr_fdt != NULL) {
uintptr_t addr = (uintptr_t) fdt64_to_cpu(*addr_fdt);
qoriq_start_spin_table_addr[cpu] = (qoriq_start_spin_table *) addr;
}
++cpu;
node = fdt_next_subnode(fdt, node);
}
return cpu * QORIQ_THREAD_COUNT;
}
.context = &lpc176x_uart_context_0.base
},
#endif
#ifdef LPC176X_CONFIG_UART_1
{
.device_file = "/dev/ttyS1",
.probe = lpc176x_uart1_probe,
.handler = &ns16550_handler_interrupt,
.context = &lpc176x_uart_context_1.base
},
#endif
#ifdef LPC176X_CONFIG_UART_2
{
.device_file = "/dev/ttyS2",
.probe = lpc176x_uart2_probe,
.handler = &ns16550_handler_interrupt,
.context = &lpc176x_uart_context_2.base
},
#endif
#ifdef LPC176X_CONFIG_UART_3
{
.device_file = "/dev/ttyS3",
.probe = lpc176x_uart3_probe,
.handler = &ns16550_handler_interrupt,
.context = &lpc176x_uart_context_3.base
},
#endif
};
const size_t console_device_count = RTEMS_ARRAY_SIZE(console_device_table);
{
.type = RTEMS_BSD_RES_MEMORY,
.start_request = 0,
.start_actual = 0x4e000000
}, {
.type = RTEMS_BSD_RES_IRQ,
.start_request = 0,
.start_actual = RVPBXA9_IRQ_ETHERNET
}
};
const rtems_bsd_device rtems_bsd_nexus_devices[] = {
{
.name = "smc",
.unit = 0,
.resource_count = RTEMS_ARRAY_SIZE(smc0_res),
.resources = &smc0_res[0]
}
};
SYSINIT_DRIVER_REFERENCE(smc, nexus);
#elif defined(__GENMCF548X_BSP_H)
const rtems_bsd_device rtems_bsd_nexus_devices[] = {
{
.name = "fec",
.unit = 0
}, {
.name = "fec",
.unit = 1
/**
* @brief setups pin multiplexer according to precomputed registers values (HCG:muxInit)
*/
void tms570_pinmux_init( void )
{
tms570_bsp_pinmmr_config( tms570_pinmmr_init_data, 0,
RTEMS_ARRAY_SIZE( tms570_pinmmr_init_data ) );
}
puts( "\n\n*** TEST fsdosfsname01 ***" );
test();
puts( "*** END OF TEST fsdosfsname01 ***" );
rtems_test_exit( 0 );
}
rtems_ramdisk_config rtems_ramdisk_configuration [] = {
{ .block_size = BLOCK_SIZE, .block_num = BLOCK_NUM },
{ .block_size = BLOCK_SIZE, .block_num = BLOCK_NUM, .location = &IMAGE_BIN_LE_SINGLEBYTE[0] },
{ .block_size = BLOCK_SIZE, .block_num = BLOCK_NUM, .location = &IMAGE_BIN_LE_MULTIBYTE[0] }
};
size_t rtems_ramdisk_configuration_size = RTEMS_ARRAY_SIZE(rtems_ramdisk_configuration);
#define CONFIGURE_INIT_TASK_STACK_SIZE ( 1024 * 64 )
#define CONFIGURE_APPLICATION_DOES_NOT_NEED_CLOCK_DRIVER
#define CONFIGURE_APPLICATION_NEEDS_CONSOLE_DRIVER
#define CONFIGURE_MAXIMUM_DRIVERS 4
#define CONFIGURE_MAXIMUM_SEMAPHORES (2 * RTEMS_DOSFS_SEMAPHORES_PER_INSTANCE)
#define CONFIGURE_APPLICATION_EXTRA_DRIVERS RAMDISK_DRIVER_TABLE_ENTRY
#define CONFIGURE_APPLICATION_NEEDS_LIBBLOCK
#define CONFIGURE_USE_IMFS_AS_BASE_FILESYSTEM
#define CONFIGURE_FILESYSTEM_DOSFS
/* 2 RAM disk device files + 2 mount_dir + stdin + stdout + stderr +
.flags = ARMV7_MMU_READ_WRITE
}, {
.begin = (uint32_t) bsp_section_rodata_begin,
.end = (uint32_t) bsp_section_rodata_end,
.flags = ARMV7_MMU_DATA_READ_ONLY_CACHED
}, {
.begin = (uint32_t) bsp_section_data_begin,
.end = (uint32_t) bsp_section_data_end,
.flags = ARMV7_MMU_DATA_READ_WRITE_CACHED
}, {
.begin = (uint32_t) bsp_section_bss_begin,
.end = (uint32_t) bsp_section_bss_end,
.flags = ARMV7_MMU_DATA_READ_WRITE_CACHED
}, {
.begin = (uint32_t) bsp_section_work_begin,
.end = (uint32_t) bsp_section_work_end,
.flags = ARMV7_MMU_DATA_READ_WRITE_CACHED
}, {
.begin = (uint32_t) bsp_section_stack_begin,
.end = (uint32_t) bsp_section_stack_end,
.flags = ARMV7_MMU_DATA_READ_WRITE_CACHED
}, {
.begin = 0x20000000,
.end = 0x21000000,
.flags = ARMV7_MMU_DEVICE
}
};
BSP_START_DATA_SECTION const size_t bsp_mm_config_table_size =
RTEMS_ARRAY_SIZE(bsp_mm_config_table);
