void NICInitRT3090RFRegisters(struct rt_rtmp_adapter *pAd)
{
int i;
/* Driver must read EEPROM to get RfIcType before initial RF registers */
/* Initialize RF register to default value */
if (IS_RT3090(pAd)) {
/* Init RF calibration */
/* Driver should toggle RF R30 bit7 before init RF registers */
u32 RfReg = 0, data;
RT30xxReadRFRegister(pAd, RF_R30, (u8 *)&RfReg);
RfReg |= 0x80;
RT30xxWriteRFRegister(pAd, RF_R30, (u8)RfReg);
RTMPusecDelay(1000);
RfReg &= 0x7F;
RT30xxWriteRFRegister(pAd, RF_R30, (u8)RfReg);
/* init R24, R31 */
RT30xxWriteRFRegister(pAd, RF_R24, 0x0F);
RT30xxWriteRFRegister(pAd, RF_R31, 0x0F);
/* RT309x version E has fixed this issue */
if ((pAd->NicConfig2.field.DACTestBit == 1)
&& ((pAd->MACVersion & 0xffff) < 0x0211)) {
/* patch tx EVM issue temporarily */
RTMP_IO_READ32(pAd, LDO_CFG0, &data);
data = ((data & 0xE0FFFFFF) | 0x0D000000);
RTMP_IO_WRITE32(pAd, LDO_CFG0, data);
} else {
RTMP_IO_READ32(pAd, LDO_CFG0, &data);
data = ((data & 0xE0FFFFFF) | 0x01000000);
RTMP_IO_WRITE32(pAd, LDO_CFG0, data);
}
/* patch LNA_PE_G1 failed issue */
RTMP_IO_READ32(pAd, GPIO_SWITCH, &data);
data &= ~(0x20);
RTMP_IO_WRITE32(pAd, GPIO_SWITCH, data);
/* Initialize RF register to default value */
for (i = 0; i < NUM_RF_REG_PARMS; i++) {
RT30xxWriteRFRegister(pAd,
RT30xx_RFRegTable[i].Register,
RT30xx_RFRegTable[i].Value);
}
/* Driver should set RF R6 bit6 on before calibration */
RT30xxReadRFRegister(pAd, RF_R06, (u8 *)&RfReg);
RfReg |= 0x40;
RT30xxWriteRFRegister(pAd, RF_R06, (u8)RfReg);
/*For RF filter Calibration */
RTMPFilterCalibration(pAd);
/* Initialize RF R27 register, set RF R27 must be behind RTMPFilterCalibration() */
if ((pAd->MACVersion & 0xffff) < 0x0211)
RT30xxWriteRFRegister(pAd, RF_R27, 0x3);
/* set led open drain enable */
RTMP_IO_READ32(pAd, OPT_14, &data);
data |= 0x01;
RTMP_IO_WRITE32(pAd, OPT_14, data);
/* set default antenna as main */
if (pAd->RfIcType == RFIC_3020)
AsicSetRxAnt(pAd, pAd->RxAnt.Pair1PrimaryRxAnt);
/* add by johnli, RF power sequence setup, load RF normal operation-mode setup */
RT30xxLoadRFNormalModeSetup(pAd);
}
}
VOID NICInitRT3572RFRegisters(IN PRTMP_ADAPTER pAd)
{
INT i;
UINT8 RfReg = 0;
UINT32 data;
/*
Driver must read EEPROM to get RfIcType before initial RF registers
Initialize RF register to default value
Init RF calibration
Driver should toggle RF R30 bit7 before init RF registers
*/
RT30xxReadRFRegister(pAd, RF_R30, (PUCHAR)&RfReg);
RfReg |= 0x80;
RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RfReg);
RTMPusecDelay(1000);
RfReg &= 0x7F;
RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RfReg);
/* Initialize RF register to default value */
for (i = 0; i < NUM_RF_3572REG_PARMS; i++)
{
RT30xxWriteRFRegister(pAd, RF3572_RFRegTable[i].Register, RF3572_RFRegTable[i].Value);
}
/* Driver should set RF R6 bit6 on before init RF registers */
RT30xxReadRFRegister(pAd, RF_R06, (PUCHAR)&RfReg);
RfReg |= 0x40;
RT30xxWriteRFRegister(pAd, RF_R06, (UCHAR)RfReg);
/* init R31 */
/*RT30xxWriteRFRegister(pAd, RF_R31, 0x14);*/
if ((pAd->NicConfig2.field.DACTestBit == 1) && ((pAd->MACVersion & 0xffff) < 0x0211))
{
/* patch tx EVM issue temporarily */
RTMP_IO_READ32(pAd, LDO_CFG0, &data);
data = ((data & 0xF0FFFFFF) | 0x0D000000);
RTMP_IO_WRITE32(pAd, LDO_CFG0, data);
}
else
{
/* Patch for SRAM, increase voltage to 1.35V on core voltage and down to 1.2V after 1 msec*/
RTMP_IO_READ32(pAd, LDO_CFG0, &data);
data = ((data & 0xE0FFFFFF) | 0x0D000000);
RTMP_IO_WRITE32(pAd, LDO_CFG0, data);
RTMPusecDelay(1000);
data = ((data & 0xE0FFFFFF) | 0x01000000);
RTMP_IO_WRITE32(pAd, LDO_CFG0, data);
}
/* patch LNA_PE_G1 (toggle GPIO_SWITCH) is not necessary for 3572 */
/*
RTMP_IO_READ32(pAd, GPIO_SWITCH, &data);
data &= ~(0x20);
RTMP_IO_WRITE32(pAd, GPIO_SWITCH, data);
*/
/* For RF filter Calibration */
RTMPFilterCalibration(pAd);
/* save R25, R26 for 2.4GHz */
BBP_IO_READ8_BY_REG_ID(pAd, BBP_R25, &pAd->Bbp25);
BBP_IO_READ8_BY_REG_ID(pAd, BBP_R26, &pAd->Bbp26);
/* set led open drain enable */
RTMP_IO_READ32(pAd, OPT_14, &data);
data |= 0x01;
RTMP_IO_WRITE32(pAd, OPT_14, data);
}
VOID NICInitRT3370RFRegisters(IN PRTMP_ADAPTER pAd)
{
INT i;
// Driver must read EEPROM to get RfIcType before initial RF registers
// Initialize RF register to default value
if (IS_RT3090(pAd)||IS_RT3390(pAd)||IS_RT3572(pAd))
{
// Init RF calibration
// Driver should toggle RF R30 bit7 before init RF registers
UINT32 RfReg = 0, data;
RT30xxReadRFRegister(pAd, RF_R30, (PUCHAR)&RfReg);
RfReg |= 0x80;
RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RfReg);
RTMPusecDelay(1000);
RfReg &= 0x7F;
RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RfReg);
// init R24, R31
RT30xxWriteRFRegister(pAd, RF_R24, 0x0F);
RT30xxWriteRFRegister(pAd, RF_R31, 0x0F);
if (IS_RT3390(pAd))
{
// patch LNA_PE_G1 failed issue
RTMP_IO_READ32(pAd, GPIO_SWITCH, &data);
data &= ~(0x20);
RTMP_IO_WRITE32(pAd, GPIO_SWITCH, data);
// RF registers initialization
for (i = 0; i < NUM_RF_REG_PARMS_OVER_RT3390; i++)
{
RT30xxWriteRFRegister(pAd, RFRegTableOverRT3390[i].Register, RFRegTableOverRT3390[i].Value);
}
}
// patch LNA_PE_G1 failed issue
RTMP_IO_READ32(pAd, GPIO_SWITCH, &data);
data &= ~(0x20);
RTMP_IO_WRITE32(pAd, GPIO_SWITCH, data);
// Initialize RF register to default value
for (i = 0; i < NUM_RF_REG_PARMS_OVER_RT3390; i++)
{
RT30xxWriteRFRegister(pAd, RT30xx_RFRegTable[i].Register, RT30xx_RFRegTable[i].Value);
}
// Driver should set RF R6 bit6 on before calibration
RT30xxReadRFRegister(pAd, RF_R06, (PUCHAR)&RfReg);
RfReg |= 0x40;
RT30xxWriteRFRegister(pAd, RF_R06, (UCHAR)RfReg);
//For RF filter Calibration
RTMPFilterCalibration(pAd);
// Initialize RF R27 register, set RF R27 must be behind RTMPFilterCalibration()
if ((pAd->MACVersion & 0xffff) < 0x0211)
RT30xxWriteRFRegister(pAd, RF_R27, 0x3);
// set led open drain enable
RTMP_IO_READ32(pAd, OPT_14, &data);
data |= 0x01;
RTMP_IO_WRITE32(pAd, OPT_14, data);
// set default antenna as main
if (pAd->RfIcType == RFIC_3020)
AsicSetRxAnt(pAd, pAd->RxAnt.Pair1PrimaryRxAnt);
// add by johnli, RF power sequence setup, load RF normal operation-mode setup
RT30xxLoadRFNormalModeSetup(pAd);
}
}
VOID NICInitRT3070RFRegisters(IN PRTMP_ADAPTER pAd)
{
INT i;
UCHAR RFValue;
/*
Driver must read EEPROM to get RfIcType before initial RF registers
Initialize RF register to default value
*/
if (IS_RT3070(pAd) || IS_RT3071(pAd))
{
/*
Init RF calibration
Driver should toggle RF R30 bit7 before init RF registers
*/
UINT8 RfReg = 0;
UINT32 data;
RT30xxReadRFRegister(pAd, RF_R30, (PUCHAR)&RfReg);
RfReg |= 0x80;
RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RfReg);
RTMPusecDelay(1000);
RfReg &= 0x7F;
RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RfReg);
/* set default antenna as main */
if (pAd->RfIcType == RFIC_3020 || pAd->RfIcType == RFIC_2020)
AsicSetRxAnt(pAd, pAd->RxAnt.Pair1PrimaryRxAnt);
/* Initialize RF register to default value */
for (i = 0; i < NUM_RF_3020_REG_PARMS; i++)
{
RT30xxWriteRFRegister(pAd, RT3020_RFRegTable[i].Register, RT3020_RFRegTable[i].Value);
}
RT30xxWriteRFRegister(pAd, RF_R31, 0x14);
/* add by johnli */
if (IS_RT3070(pAd))
{
/*
The DAC issue(LDO_CFG0) has been fixed in RT3070(F).
The voltage raising patch is no longer needed for RT3070(F)
*/
if ((pAd->MACVersion & 0xffff) < 0x0201)
{
/* Update MAC 0x05D4 from 01xxxxxx to 0Dxxxxxx (voltage 1.2V to 1.35V) for RT3070 to improve yield rate */
RTUSBReadMACRegister(pAd, LDO_CFG0, &data);
data = ((data & 0xF0FFFFFF) | 0x0D000000);
RTUSBWriteMACRegister(pAd, LDO_CFG0, data);
}
}
else if (IS_RT3071(pAd))
{
/* Driver should set RF R6 bit6 on before init RF registers */
RT30xxReadRFRegister(pAd, RF_R06, (PUCHAR)&RfReg);
RfReg |= 0x40;
RT30xxWriteRFRegister(pAd, RF_R06, (UCHAR)RfReg);
/* RT3071 version E has fixed this issue */
if ((pAd->NicConfig2.field.DACTestBit == 1) && ((pAd->MACVersion & 0xffff) < 0x0211))
{
/* patch tx EVM issue temporarily */
RTUSBReadMACRegister(pAd, LDO_CFG0, &data);
data = ((data & 0xE0FFFFFF) | 0x0D000000);
RTUSBWriteMACRegister(pAd, LDO_CFG0, data);
}
else
{
RTMP_IO_READ32(pAd, LDO_CFG0, &data);
data = ((data & 0xE0FFFFFF) | 0x01000000);
RTMP_IO_WRITE32(pAd, LDO_CFG0, data);
}
/* patch LNA_PE_G1 failed issue */
RTUSBReadMACRegister(pAd, GPIO_SWITCH, &data);
data &= ~(0x20);
RTUSBWriteMACRegister(pAd, GPIO_SWITCH, data);
}
/* For RF filter Calibration */
RTMPFilterCalibration(pAd);
/*
Initialize RF R27 register, set RF R27 must be behind RTMPFilterCalibration()
TX to RX IQ glitch(RF_R27) has been fixed in RT3070(F).
Raising RF voltage is no longer needed for RT3070(F)
*/
if ((IS_RT3070(pAd)) && ((pAd->MACVersion & 0xffff) < 0x0201))
{
RT30xxWriteRFRegister(pAd, RF_R27, 0x3);
}
else if ((IS_RT3071(pAd)) && ((pAd->MACVersion & 0xffff) < 0x0211))
{
RT30xxWriteRFRegister(pAd, RF_R27, 0x3);
}
/* set led open drain enable */
RTUSBReadMACRegister(pAd, OPT_14, &data);
data |= 0x01;
RTUSBWriteMACRegister(pAd, OPT_14, data);
if (IS_RT3071(pAd))
{
/* RF power sequence setup, load RF normal operation-mode setup */
RT30xxLoadRFNormalModeSetup(pAd);
}
else if (IS_RT3070(pAd))
{
/* TX_LO1_en, RF R17 register Bit 3 to 0 */
RT30xxReadRFRegister(pAd, RF_R17, &RFValue);
RFValue &= (~0x08);
/* to fix rx long range issue */
if (pAd->NicConfig2.field.ExternalLNAForG == 0)
{
if ((IS_RT3071(pAd) && ((pAd->MACVersion & 0xffff) >= 0x0211)) || IS_RT3070(pAd))
{
RFValue |= 0x20;
}
}
/* set RF_R17_bit[2:0] equal to EEPROM setting at 0x48h */
if (pAd->TxMixerGain24G >= 1)
{
RFValue &= (~0x7); /* clean bit [2:0] */
RFValue |= pAd->TxMixerGain24G;
}
RT30xxWriteRFRegister(pAd, RF_R17, RFValue);
/* add by johnli, reset RF_R27 when interface down & up to fix throughput problem */
/* LDORF_VC, RF R27 register Bit 2 to 0 */
RT30xxReadRFRegister(pAd, RF_R27, &RFValue);
/*
TX to RX IQ glitch(RF_R27) has been fixed in RT3070(F).
Raising RF voltage is no longer needed for RT3070(F)
*/
if ((pAd->MACVersion & 0xffff) < 0x0201)
RFValue = (RFValue & (~0x77)) | 0x3;
else
RFValue = (RFValue & (~0x77));
RT30xxWriteRFRegister(pAd, RF_R27, RFValue);
/* end johnli */
}
}
}
VOID NICInitRT3593RFRegisters(
IN PRTMP_ADAPTER pAd)
{
ULONG RfReg = 0;
ULONG data;
USHORT i;
// if (IS_RT3593(pAd))
{
// Init RF calibration
// Driver should toggle RF R30 bit7 before init RF registers
RT30xxReadRFRegister(pAd, RF_R02, (PUCHAR)&RfReg);
RfReg = ((RfReg & ~0x80) | 0x80); // rescal_en (initiate calbration)
RT30xxWriteRFRegister(pAd, RF_R02, (UCHAR)RfReg);
RTMPusecDelay(1000);
RfReg = (RfReg & ~0x80); // rescal_en (initiate calbration)
RT30xxWriteRFRegister(pAd, RF_R02, (UCHAR)RfReg);
// init R24, R31
RT30xxReadRFRegister(pAd, RF_R32, (PUCHAR)&RfReg);
RfReg = ((RfReg & ~0xF8) | 0x78); // tx_agc_fc (capacitor control in Tx baseband filter)
//RT30xxWriteRFRegister(pAd, RF_R32, (UCHAR)RfReg);
RT30xxReadRFRegister(pAd, RF_R31, (PUCHAR)&RfReg);
RfReg = ((RfReg & ~0xF8) | 0x78); // rx_agc_fc (capacitor control in Rx baseband filter)
//RT30xxWriteRFRegister(pAd, RF_R31, (UCHAR)RfReg);
// RT3071 version E has fixed this issue
if ((pAd->MACVersion & 0xffff) < 0x0211)
{
if (pAd->NicConfig2.field.DACTestBit == 1)
{
// patch tx EVM issue temporarily
RTMP_IO_READ32(pAd, LDO_CFG0, &data);
data = ((data & 0xE0FFFFFF) | 0x0D000000);
RTMP_IO_WRITE32(pAd, LDO_CFG0, data);
}
}
else
{
// Patch CCK ok, OFDM failed issue, just toggle and restore LDO_CFG0.
// Patch SRAM for 3572, increase voltage to 1.35V on core voltage and down to 1.2V after 1 msec
RTMP_IO_READ32(pAd, LDO_CFG0, &data);
data = ((data & 0xE0FFFFFF) | 0x0D000000);
RTMP_IO_WRITE32(pAd, LDO_CFG0, data);
RTMPusecDelay(1000);
data = ((data & 0xE0FFFFFF) | 0x01000000);
RTMP_IO_WRITE32(pAd, LDO_CFG0, data);
}
// patch LNA_PE_G1 failed issue
RTMP_IO_READ32(pAd, GPIO_SWITCH, &data);
data &= ~(0x20);
RTMP_IO_WRITE32(pAd, GPIO_SWITCH, data);
// Initialize RF register to default value
for (i = 0; i < NUM_RF_3053_REG_PARMS; i++)
{
RT30xxWriteRFRegister(pAd, RF3053RegTable[i].Register, RF3053RegTable[i].Value);
}
// Driver should set RF R6 bit6 on before calibration
RT30xxReadRFRegister(pAd, RF_R18, (PUCHAR)&RfReg);
RfReg |= ((RfReg & ~0x40) | 0x40); // xo_tune_bypass (0: XO is auto-tuned and 1: XO tuning bypassed)
RT30xxWriteRFRegister(pAd, RF_R18, (UCHAR)RfReg);
//For RF filter Calibration
RTMPFilterCalibration(pAd);
//2 TODO:?
pAd->Mlme.CaliBW20RfR24 = 0x1F;
pAd->Mlme.CaliBW40RfR24 = 0x2F;
// save R25, R26 for 2.4GHz
RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R25, &pAd->Bbp25);
RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R26, &pAd->Bbp26);
// Initialize RF R27 register, set RF R27 must be behind RTMPFilterCalibration()
if ((pAd->MACVersion & 0xffff) < 0x0211)
RT30xxWriteRFRegister(pAd, RF_R27, 0x3);
// set led open drain enable
RTMP_IO_READ32(pAd, OPT_14, &data);
data |= 0x01;
RTMP_IO_WRITE32(pAd, OPT_14, data);
// Initialize RT3090 serial MAc registers which is different from RT2860 serial
RTMP_IO_WRITE32(pAd, TX_SW_CFG1, 0);
// RT3071 version E has fixed this issue
if ((pAd->MACVersion & 0xffff) < 0x0211)
{
if (pAd->NicConfig2.field.DACTestBit == 1)
{
RTMP_IO_WRITE32(pAd, TX_SW_CFG2, 0x1F); // To fix throughput drop drastically
}
else
{
RTMP_IO_WRITE32(pAd, TX_SW_CFG2, 0x0F); // To fix throughput drop drastically
}
}
else
{
RTMP_IO_WRITE32(pAd, TX_SW_CFG2, 0x0);
}
// set default antenna as main
if (pAd->RfIcType == RFIC_3020)
AsicSetRxAnt(pAd, pAd->RxAnt.Pair1PrimaryRxAnt);
// add by johnli, RF power sequence setup, load RF normal operation-mode setup
RT3593LoadRFNormalModeSetup(pAd);
// adjust some BBP register contents
// also can put these BBP registers to pBBPRegTable
RT3593_PostBBPInitialization(pAd);
}
} /* End of NICInitRT3593RFRegisters */
VOID NICInitRT3090RFRegisters(IN PRTMP_ADAPTER pAd)
{
INT i;
if (IS_RT3090(pAd))
{
UINT32 RfReg = 0, data;
RT30xxReadRFRegister(pAd, RF_R30, (PUCHAR)&RfReg);
RfReg |= 0x80;
RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RfReg);
RTMPusecDelay(1000);
RfReg &= 0x7F;
RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RfReg);
RT30xxWriteRFRegister(pAd, RF_R24, 0x0F);
RT30xxWriteRFRegister(pAd, RF_R31, 0x0F);
if ((pAd->NicConfig2.field.DACTestBit == 1) && ((pAd->MACVersion & 0xffff) < 0x0211))
{
RTMP_IO_READ32(pAd, LDO_CFG0, &data);
data = ((data & 0xE0FFFFFF) | 0x0D000000);
RTMP_IO_WRITE32(pAd, LDO_CFG0, data);
}
else
{
RTMP_IO_READ32(pAd, LDO_CFG0, &data);
data = ((data & 0xE0FFFFFF) | 0x01000000);
RTMP_IO_WRITE32(pAd, LDO_CFG0, data);
}
RTMP_IO_READ32(pAd, GPIO_SWITCH, &data);
data &= ~(0x20);
RTMP_IO_WRITE32(pAd, GPIO_SWITCH, data);
for (i = 0; i < NUM_RF_REG_PARMS; i++)
{
RT30xxWriteRFRegister(pAd, RT30xx_RFRegTable[i].Register, RT30xx_RFRegTable[i].Value);
}
RT30xxReadRFRegister(pAd, RF_R06, (PUCHAR)&RfReg);
RfReg |= 0x40;
RT30xxWriteRFRegister(pAd, RF_R06, (UCHAR)RfReg);
RTMPFilterCalibration(pAd);
if ((pAd->MACVersion & 0xffff) < 0x0211)
RT30xxWriteRFRegister(pAd, RF_R27, 0x3);
RTMP_IO_READ32(pAd, OPT_14, &data);
data |= 0x01;
RTMP_IO_WRITE32(pAd, OPT_14, data);
if (pAd->RfIcType == RFIC_3020)
AsicSetRxAnt(pAd, pAd->RxAnt.Pair1PrimaryRxAnt);
RT30xxLoadRFNormalModeSetup(pAd);
}
}
VOID NICInitRT3090RFRegisters(IN PRTMP_ADAPTER pAd)
{
INT i;
// Driver must read EEPROM to get RfIcType before initial RF registers
// Initialize RF register to default value
if (IS_RT3090(pAd))
{
// Init RF calibration
// Driver should toggle RF R30 bit7 before init RF registers
UINT32 RfReg = 0, data;
RT30xxReadRFRegister(pAd, RF_R30, (PUCHAR)&RfReg);
RfReg |= 0x80;
RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RfReg);
RTMPusecDelay(1000);
RfReg &= 0x7F;
RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RfReg);
// init R24, R31
// RT30xxWriteRFRegister(pAd, RF_R24, 0x0F);
// RT30xxWriteRFRegister(pAd, RF_R31, 0x0F);
// RT309x version E has fixed this issue
if ((pAd->NicConfig2.field.DACTestBit == 1) && ((pAd->MACVersion & 0xffff) < 0x0211))
{
// patch tx EVM issue temporarily
RTMP_IO_READ32(pAd, LDO_CFG0, &data);
data = ((data & 0xE0FFFFFF) | 0x0D000000);
RTMP_IO_WRITE32(pAd, LDO_CFG0, data);
}
else
{
RTMP_IO_READ32(pAd, LDO_CFG0, &data);
data = ((data & 0xE0FFFFFF) | 0x01000000);
RTMP_IO_WRITE32(pAd, LDO_CFG0, data);
}
// patch LNA_PE_G1 failed issue
RTMP_IO_READ32(pAd, GPIO_SWITCH, &data);
data &= ~(0x20);
RTMP_IO_WRITE32(pAd, GPIO_SWITCH, data);
// Initialize RF register to default value
for (i = 0; i < NUM_RF_3020_REG_PARMS; i++)
{
RT30xxWriteRFRegister(pAd, RT3020_RFRegTable[i].Register, RT3020_RFRegTable[i].Value);
}
RT30xxWriteRFRegister(pAd, RF_R31, 0x14);
// Driver should set RF R6 bit6 on before calibration
RT30xxReadRFRegister(pAd, RF_R06, (PUCHAR)&RfReg);
RfReg |= 0x40;
RT30xxWriteRFRegister(pAd, RF_R06, (UCHAR)RfReg);
//For RF filter Calibration
RTMPFilterCalibration(pAd);
// Initialize RF R27 register, set RF R27 must be behind RTMPFilterCalibration()
if ((pAd->MACVersion & 0xffff) < 0x0211)
RT30xxWriteRFRegister(pAd, RF_R27, 0x3);
// set led open drain enable
RTMP_IO_READ32(pAd, OPT_14, &data);
data |= 0x01;
RTMP_IO_WRITE32(pAd, OPT_14, data);
// set default antenna as main
if (pAd->RfIcType == RFIC_3020)
AsicSetRxAnt(pAd, pAd->RxAnt.Pair1PrimaryRxAnt);
// From RT3071 Power Sequence v1.1 document, the Normal Operation Setting Registers as follow :
// BBP_R138 / RF_R1 / RF_R15 / RF_R17 / RF_R20 / RF_R21.
// add by johnli, RF power sequence setup, load RF normal operation-mode setup
RT30xxLoadRFNormalModeSetup(pAd);
}
}
