/*
==========================================================================
Description:
Setup Frame format.
NOTE:
This routine should only be used in ATE mode.
==========================================================================
*/
INT ATESetUpFrame(
IN PRTMP_ADAPTER pAd,
IN UINT32 TxIdx)
{
PATE_INFO pATEInfo = &(pAd->ate);
UINT pos = 0;
PTXD_STRUC pTxD;
#ifdef RT_BIG_ENDIAN
PTXD_STRUC pDestTxD;
TXD_STRUC TxD;
#endif
PNDIS_PACKET pPacket=NULL;
PUCHAR pDest=NULL;
PVOID AllocVa=NULL;
NDIS_PHYSICAL_ADDRESS AllocPa;
HTTRANSMIT_SETTING TxHTPhyMode;
PRTMP_TX_RING pTxRing = &pAd->TxRing[QID_AC_BE];
PTXWI_STRUC pTxWI = (PTXWI_STRUC) pTxRing->Cell[TxIdx].DmaBuf.AllocVa;
PUCHAR pDMAHeaderBufVA = (PUCHAR) pTxRing->Cell[TxIdx].DmaBuf.AllocVa;
UINT8 TXWISize = pAd->chipCap.TXWISize;
#ifdef RALINK_QA
PHEADER_802_11 pHeader80211;
#endif /* RALINK_QA */
/* fill TxWI */
TxHTPhyMode.field.BW = pATEInfo->TxWI.BW;
TxHTPhyMode.field.ShortGI = pATEInfo->TxWI.ShortGI;
TxHTPhyMode.field.STBC = pATEInfo->TxWI.STBC;
TxHTPhyMode.field.MCS = pATEInfo->TxWI.MCS;
TxHTPhyMode.field.MODE = pATEInfo->TxWI.PHYMODE;
if (pATEInfo->bQATxStart == TRUE)
{
/* always use QID_AC_BE and FIFO_EDCA */
ATEWriteTxWI(pAd, pTxWI, pATEInfo->TxWI.FRAG, pATEInfo->TxWI.CFACK,
pATEInfo->TxWI.TS, pATEInfo->TxWI.AMPDU, pATEInfo->TxWI.ACK,
pATEInfo->TxWI.NSEQ, pATEInfo->TxWI.BAWinSize, 0,
pATEInfo->TxWI.MPDUtotalByteCount, pATEInfo->TxWI.PacketId, 0, 0,
pATEInfo->TxWI.txop/*IFS_HTTXOP*/, pATEInfo->TxWI.CFACK/*FALSE*/,
&TxHTPhyMode);
}
else
{
ATEWriteTxWI(pAd, pTxWI, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE,
4, 0, pATEInfo->TxLength, 0, 0, 0, IFS_HTTXOP, FALSE, &TxHTPhyMode);
}
/* fill 802.11 header */
#ifdef RALINK_QA
if (pATEInfo->bQATxStart == TRUE)
{
NdisMoveMemory(pDMAHeaderBufVA + TXWISize, pATEInfo->Header, pATEInfo->HLen);
}
else
#endif /* RALINK_QA */
{
pATEInfo->HLen = LENGTH_802_11;
NdisMoveMemory(pDMAHeaderBufVA + TXWISize, TemplateFrame, pATEInfo->HLen);
NdisMoveMemory(pDMAHeaderBufVA + TXWISize + 4, pATEInfo->Addr1, ETH_LENGTH_OF_ADDRESS);
NdisMoveMemory(pDMAHeaderBufVA + TXWISize + 10, pATEInfo->Addr2, ETH_LENGTH_OF_ADDRESS);
NdisMoveMemory(pDMAHeaderBufVA + TXWISize + 16, pATEInfo->Addr3, ETH_LENGTH_OF_ADDRESS);
}
#ifdef RT_BIG_ENDIAN
RTMPFrameEndianChange(pAd, (((PUCHAR)pDMAHeaderBufVA) + TXWISize), DIR_READ, FALSE);
#endif /* RT_BIG_ENDIAN */
/* alloc buffer for payload */
#ifdef RALINK_QA
if ((pATEInfo->bQATxStart == TRUE) && (pATEInfo->DLen != 0))
{
pPacket = RTMP_AllocateRxPacketBuffer(pAd, ((POS_COOKIE)(pAd->OS_Cookie))->pci_dev,
pATEInfo->DLen + 0x100, FALSE, &AllocVa, &AllocPa);
}
else
#endif /* RALINK_QA */
{
pPacket = RTMP_AllocateRxPacketBuffer(pAd, ((POS_COOKIE)(pAd->OS_Cookie))->pci_dev,
pATEInfo->TxLength, FALSE, &AllocVa, &AllocPa);
}
if (pPacket == NULL)
{
pATEInfo->TxCount = 0;
DBGPRINT_ERR(("%s : fail to alloc packet space.\n", __FUNCTION__));
return -1;
}
pTxRing->Cell[TxIdx].pNextNdisPacket = pPacket;
pDest = (PUCHAR) AllocVa;
#ifdef RALINK_QA
if ((pATEInfo->bQATxStart == TRUE) && (pATEInfo->DLen != 0))
{
GET_OS_PKT_LEN(pPacket) = pATEInfo->DLen;
GET_OS_PKT_TOTAL_LEN(pPacket) = pATEInfo->DLen;
}
else
#endif /* RALINK_QA */
{
GET_OS_PKT_LEN(pPacket) = pATEInfo->TxLength - LENGTH_802_11;
GET_OS_PKT_TOTAL_LEN(pPacket) = pATEInfo->TxLength - LENGTH_802_11;
}
/* prepare frame payload */
#ifdef RALINK_QA
if ((pATEInfo->bQATxStart == TRUE) && (pATEInfo->DLen != 0))
{
/* copy pattern to payload */
if ((pATEInfo->PLen != 0))
{
for (pos = 0; pos < pATEInfo->DLen; pos += pATEInfo->PLen)
{
memcpy(GET_OS_PKT_DATAPTR(pPacket) + pos, pATEInfo->Pattern, pATEInfo->PLen);
}
}
}
else
#endif /* RALINK_QA */
{
for (pos = 0; pos < GET_OS_PKT_LEN(pPacket); pos++)
{
/* default payload is 0xA5 */
pDest[pos] = pATEInfo->Payload;
}
}
/* build Tx descriptor */
#ifndef RT_BIG_ENDIAN
pTxD = (PTXD_STRUC) pTxRing->Cell[TxIdx].AllocVa;
#else
pDestTxD = (PTXD_STRUC)pTxRing->Cell[TxIdx].AllocVa;
TxD = *pDestTxD;
pTxD = &TxD;
#endif /* !RT_BIG_ENDIAN */
#ifdef RALINK_QA
if (pATEInfo->bQATxStart == TRUE)
{
/* prepare TxD */
NdisZeroMemory(pTxD, TXD_SIZE);
RTMPWriteTxDescriptor(pAd, pTxD, FALSE, FIFO_EDCA);
/* build Tx descriptor */
pTxD->SDPtr0 = RTMP_GetPhysicalAddressLow(pTxRing->Cell[TxIdx].DmaBuf.AllocPa);
pTxD->SDLen0 = TXWISize + pATEInfo->HLen;
pTxD->SDPtr1 = AllocPa;
pTxD->SDLen1 = GET_OS_PKT_LEN(pPacket);
pTxD->LastSec0 = (pTxD->SDLen1 == 0) ? 1 : 0;
pTxD->LastSec1 = 1;
pDest = (PUCHAR)pTxWI;
pDest += TXWISize;
pHeader80211 = (PHEADER_802_11)pDest;
/* modify sequence number... */
if (pATEInfo->TxDoneCount == 0)
pATEInfo->seq = pHeader80211->Sequence;
else
pHeader80211->Sequence = ++pATEInfo->seq;
}
else
#endif /* RALINK_QA */
{
NdisZeroMemory(pTxD, TXD_SIZE);
RTMPWriteTxDescriptor(pAd, pTxD, FALSE, FIFO_EDCA);
/* build Tx descriptor */
pTxD->SDPtr0 = RTMP_GetPhysicalAddressLow (pTxRing->Cell[TxIdx].DmaBuf.AllocPa);
pTxD->SDLen0 = TXWISize + LENGTH_802_11;
pTxD->LastSec0 = 0;
pTxD->SDPtr1 = AllocPa;
pTxD->SDLen1 = GET_OS_PKT_LEN(pPacket);
pTxD->LastSec1 = 1;
}
#ifdef RT_BIG_ENDIAN
RTMPWIEndianChange(pAd, (PUCHAR)pTxWI, TYPE_TXWI);
RTMPFrameEndianChange(pAd, (((PUCHAR)pDMAHeaderBufVA) + TXWISize), DIR_WRITE, FALSE);
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
WriteBackToDescriptor((PUCHAR)pDestTxD, (PUCHAR)pTxD, FALSE, TYPE_TXD);
#endif /* RT_BIG_ENDIAN */
return 0;
}
PNDIS_PACKET GetPacketFromRxRing(
IN PRTMP_ADAPTER pAd,
OUT PRT28XX_RXD_STRUC pSaveRxD,
OUT BOOLEAN *pbReschedule,
IN OUT UINT32 *pRxPending)
{
PRXD_STRUC pRxD;
#ifdef RT_BIG_ENDIAN
PRXD_STRUC pDestRxD;
RXD_STRUC RxD;
#endif
PNDIS_PACKET pRxPacket = NULL;
PNDIS_PACKET pNewPacket;
PVOID AllocVa;
NDIS_PHYSICAL_ADDRESS AllocPa;
BOOLEAN bReschedule = FALSE;
RTMP_DMACB *pRxCell;
RTMP_SEM_LOCK(&pAd->RxRingLock);
if (*pRxPending == 0)
{
// Get how may packets had been received
RTMP_IO_READ32(pAd, RX_DRX_IDX , &pAd->RxRing.RxDmaIdx);
if (pAd->RxRing.RxSwReadIdx == pAd->RxRing.RxDmaIdx)
{
// no more rx packets
bReschedule = FALSE;
goto done;
}
// get rx pending count
if (pAd->RxRing.RxDmaIdx > pAd->RxRing.RxSwReadIdx)
*pRxPending = pAd->RxRing.RxDmaIdx - pAd->RxRing.RxSwReadIdx;
else
*pRxPending = pAd->RxRing.RxDmaIdx + RX_RING_SIZE - pAd->RxRing.RxSwReadIdx;
}
pRxCell = &pAd->RxRing.Cell[pAd->RxRing.RxSwReadIdx];
#ifdef RT_BIG_ENDIAN
pDestRxD = (PRXD_STRUC) pRxCell->AllocVa;
RxD = *pDestRxD;
pRxD = &RxD;
RTMPDescriptorEndianChange((PUCHAR)pRxD, TYPE_RXD);
#else
// Point to Rx indexed rx ring descriptor
pRxD = (PRXD_STRUC) pRxCell->AllocVa;
#endif
if (pRxD->DDONE == 0)
{
*pRxPending = 0;
// DMAIndx had done but DDONE bit not ready
bReschedule = TRUE;
goto done;
}
// return rx descriptor
NdisMoveMemory(pSaveRxD, pRxD, RXD_SIZE);
pNewPacket = RTMP_AllocateRxPacketBuffer(pAd, RX_BUFFER_AGGRESIZE, FALSE, &AllocVa, &AllocPa);
if (pNewPacket)
{
// unmap the rx buffer
PCI_UNMAP_SINGLE(pAd, pRxCell->DmaBuf.AllocPa,
pRxCell->DmaBuf.AllocSize, PCI_DMA_FROMDEVICE);
pRxPacket = pRxCell->pNdisPacket;
pRxCell->DmaBuf.AllocSize = RX_BUFFER_AGGRESIZE;
pRxCell->pNdisPacket = (PNDIS_PACKET) pNewPacket;
pRxCell->DmaBuf.AllocVa = AllocVa;
pRxCell->DmaBuf.AllocPa = AllocPa;
/* update SDP0 to new buffer of rx packet */
pRxD->SDP0 = AllocPa;
}
else
{
//DBGPRINT(RT_DEBUG_TRACE,("No Rx Buffer\n"));
pRxPacket = NULL;
bReschedule = TRUE;
}
pRxD->DDONE = 0;
// had handled one rx packet
*pRxPending = *pRxPending - 1;
// update rx descriptor and kick rx
#ifdef RT_BIG_ENDIAN
RTMPDescriptorEndianChange((PUCHAR)pRxD, TYPE_RXD);
WriteBackToDescriptor((PUCHAR)pDestRxD, (PUCHAR)pRxD, FALSE, TYPE_RXD);
#endif
INC_RING_INDEX(pAd->RxRing.RxSwReadIdx, RX_RING_SIZE);
pAd->RxRing.RxCpuIdx = (pAd->RxRing.RxSwReadIdx == 0) ? (RX_RING_SIZE-1) : (pAd->RxRing.RxSwReadIdx-1);
RTMP_IO_WRITE32(pAd, RX_CRX_IDX, pAd->RxRing.RxCpuIdx);
done:
RTMP_SEM_UNLOCK(&pAd->RxRingLock);
*pbReschedule = bReschedule;
return pRxPacket;
}
/*
==========================================================================
Description:
Setup Frame format.
NOTE:
This routine should only be used in ATE mode.
==========================================================================
*/
INT ATESetUpFrame(
IN PRTMP_ADAPTER pAd,
IN UINT32 TxIdx)
{
PATE_INFO pATEInfo = &(pAd->ate);
UINT pos = 0;
PTXD_STRUC pTxD;
#ifdef RT_BIG_ENDIAN
PTXD_STRUC pDestTxD;
TXD_STRUC TxD;
#endif
PNDIS_PACKET pPacket=NULL;
PUCHAR pDest=NULL;
PVOID AllocVa=NULL;
NDIS_PHYSICAL_ADDRESS AllocPa;
HTTRANSMIT_SETTING TxHTPhyMode;
PRTMP_TX_RING pTxRing = &pAd->TxRing[QID_AC_BE];
PTXWI_STRUC pTxWI = (PTXWI_STRUC) pTxRing->Cell[TxIdx].DmaBuf.AllocVa;
PUCHAR pDMAHeaderBufVA = (PUCHAR) pTxRing->Cell[TxIdx].DmaBuf.AllocVa;
UINT8 TXWISize = pAd->chipCap.TXWISize;
#ifdef RALINK_QA
PHEADER_802_11 pHeader80211;
#endif /* RALINK_QA */
/* fill TxWI */
TxHTPhyMode.field.BW = pATEInfo->TxWI.BW;
TxHTPhyMode.field.ShortGI = pATEInfo->TxWI.ShortGI;
TxHTPhyMode.field.STBC = pATEInfo->TxWI.STBC;
TxHTPhyMode.field.MCS = pATEInfo->TxWI.MCS;
TxHTPhyMode.field.MODE = pATEInfo->TxWI.PHYMODE;
if (pATEInfo->bQATxStart == TRUE)
{
/* always use QID_AC_BE and FIFO_EDCA */
ATEWriteTxWI(pAd, pTxWI, pATEInfo->TxWI.FRAG, pATEInfo->TxWI.CFACK,
pATEInfo->TxWI.TS, pATEInfo->TxWI.AMPDU, pATEInfo->TxWI.ACK,
pATEInfo->TxWI.NSEQ, pATEInfo->TxWI.BAWinSize, 0,
pATEInfo->TxWI.MPDUtotalByteCount, pATEInfo->TxWI.PacketId, 0, 0,
pATEInfo->TxWI.txop/*IFS_HTTXOP*/, pATEInfo->TxWI.CFACK/*FALSE*/,
&TxHTPhyMode);
#ifdef TXBF_SUPPORT
if (IS_RT2883(pAd) || IS_RT3883(pAd))
{
/* Must copy rsv bits to actual TxWI */
pTxWI->rsv = pATEInfo->TxWI.rsv;
pTxWI->iTxBF = pATEInfo->TxWI.iTxBF;
pTxWI->Sounding = pATEInfo->TxWI.Sounding;
pTxWI->eTxBF = pATEInfo->TxWI.eTxBF;
pTxWI->Autofallback = pATEInfo->TxWI.Autofallback;
pTxWI->NDPSndBW = pATEInfo->TxWI.NDPSndBW;
pTxWI->NDPSndRate = pATEInfo->TxWI.NDPSndRate;
}
#endif /* TXBF_SUPPORT */
}
else
{
ATEWriteTxWI(pAd, pTxWI, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE,
4, 0, pATEInfo->TxLength, 0, 0, 0, IFS_HTTXOP, FALSE, &TxHTPhyMode);
#ifdef TXBF_SUPPORT
if (pATEInfo->bTxBF == 1)
{
if (IS_RT2883(pAd) || IS_RT3883(pAd))
{
pTxWI->rsv = 0;
pTxWI->iTxBF = pATEInfo->TxWI.iTxBF;
pTxWI->Sounding = (pATEInfo->txSoundingMode == 1 ? 1 : 0);
pTxWI->eTxBF = pATEInfo->TxWI.eTxBF;
pTxWI->Autofallback = pATEInfo->TxWI.Autofallback;
pTxWI->NDPSndBW = pATEInfo->TxWI.BW;
if (pATEInfo->txSoundingMode == 3)
pTxWI->NDPSndRate = 2;
else if (pATEInfo->txSoundingMode == 2)
pTxWI->NDPSndRate = 1;
else
pTxWI->NDPSndRate = 0;
}
}
#endif /* TXBF_SUPPORT */
}
/* fill 802.11 header */
#ifdef RALINK_QA
if (pATEInfo->bQATxStart == TRUE)
{
NdisMoveMemory(pDMAHeaderBufVA + TXWISize, pATEInfo->Header, pATEInfo->HLen);
}
else
#endif /* RALINK_QA */
{
pATEInfo->HLen = LENGTH_802_11;
#ifdef TXBF_SUPPORT
TemplateFrame[0] = 0x08; /* Data */
TemplateFrame[1] = 0x00;
if (pATEInfo->bTxBF && pATEInfo->txSoundingMode!=0)
{
/* QoS Data */
pATEInfo->HLen = 32;
TemplateFrame[0] = 0x88;
TemplateFrame[1] = 0x80;
switch (pATEInfo->txSoundingMode)
{
case 1:
/* Data Sounding */
TemplateFrame[28] = pAd->CommonCfg.ETxBfNoncompress? 0x80: 0xc0;
TemplateFrame[29] = 0x00;
break;
case 2:
case 3:
/* 2 or 3 Stream NDP */
TemplateFrame[28] = pAd->CommonCfg.ETxBfNoncompress? 0x80: 0xc0;
TemplateFrame[29] = 0x01; /* NDP Announce */
break;
default:
TemplateFrame[28] = TemplateFrame[29] = 0x0;
}
}
#endif /* TXBF_SUPPORT */
NdisMoveMemory(pDMAHeaderBufVA + TXWISize, TemplateFrame, pATEInfo->HLen);
NdisMoveMemory(pDMAHeaderBufVA + TXWISize + 4, pATEInfo->Addr1, ETH_LENGTH_OF_ADDRESS);
NdisMoveMemory(pDMAHeaderBufVA + TXWISize + 10, pATEInfo->Addr2, ETH_LENGTH_OF_ADDRESS);
NdisMoveMemory(pDMAHeaderBufVA + TXWISize + 16, pATEInfo->Addr3, ETH_LENGTH_OF_ADDRESS);
}
#ifdef RT_BIG_ENDIAN
RTMPFrameEndianChange(pAd, (((PUCHAR)pDMAHeaderBufVA) + TXWISize), DIR_READ, FALSE);
#endif /* RT_BIG_ENDIAN */
/* alloc buffer for payload */
#ifdef RALINK_QA
if ((pATEInfo->bQATxStart == TRUE) && (pATEInfo->DLen != 0))
{
pPacket = RTMP_AllocateRxPacketBuffer(pAd, ((POS_COOKIE)(pAd->OS_Cookie))->pci_dev,
pATEInfo->DLen + 0x100, FALSE, &AllocVa, &AllocPa);
}
else
#endif /* RALINK_QA */
{
pPacket = RTMP_AllocateRxPacketBuffer(pAd, ((POS_COOKIE)(pAd->OS_Cookie))->pci_dev,
pATEInfo->TxLength, FALSE, &AllocVa, &AllocPa);
}
if (pPacket == NULL)
{
pATEInfo->TxCount = 0;
DBGPRINT_ERR(("%s : fail to alloc packet space.\n", __FUNCTION__));
return -1;
}
pTxRing->Cell[TxIdx].pNextNdisPacket = pPacket;
pDest = (PUCHAR) AllocVa;
#ifdef RALINK_QA
if ((pATEInfo->bQATxStart == TRUE) && (pATEInfo->DLen != 0))
{
GET_OS_PKT_LEN(pPacket) = pATEInfo->DLen;
#ifndef LINUX
GET_OS_PKT_TOTAL_LEN(pPacket) = pATEInfo->DLen;
#endif /* LIMUX */
}
else
#endif /* RALINK_QA */
{
GET_OS_PKT_LEN(pPacket) = pATEInfo->TxLength - LENGTH_802_11;
#ifndef LINUX
GET_OS_PKT_TOTAL_LEN(pPacket) = pATEInfo->TxLength - LENGTH_802_11;
#endif /* LINUX */
}
/* prepare frame payload */
#ifdef RALINK_QA
if ((pATEInfo->bQATxStart == TRUE) && (pATEInfo->DLen != 0))
{
/* copy pattern to payload */
if ((pATEInfo->PLen != 0))
{
for (pos = 0; pos < pATEInfo->DLen; pos += pATEInfo->PLen)
{
memcpy(GET_OS_PKT_DATAPTR(pPacket) + pos, pATEInfo->Pattern, pATEInfo->PLen);
}
}
}
else
#endif /* RALINK_QA */
{
for (pos = 0; pos < GET_OS_PKT_LEN(pPacket); pos++)
{
/* default payload is 0xA5 */
pDest[pos] = pATEInfo->Payload;
}
}
/* build Tx descriptor */
#ifndef RT_BIG_ENDIAN
pTxD = (PTXD_STRUC) pTxRing->Cell[TxIdx].AllocVa;
#else
pDestTxD = (PTXD_STRUC)pTxRing->Cell[TxIdx].AllocVa;
TxD = *pDestTxD;
pTxD = &TxD;
#endif /* !RT_BIG_ENDIAN */
#ifdef RALINK_QA
if (pATEInfo->bQATxStart == TRUE)
{
/* prepare TxD */
NdisZeroMemory(pTxD, TXD_SIZE);
RTMPWriteTxDescriptor(pAd, pTxD, FALSE, FIFO_EDCA);
/* build Tx descriptor */
pTxD->SDPtr0 = RTMP_GetPhysicalAddressLow(pTxRing->Cell[TxIdx].DmaBuf.AllocPa);
pTxD->SDLen0 = TXWISize + pATEInfo->HLen;
pTxD->SDPtr1 = AllocPa;
pTxD->SDLen1 = GET_OS_PKT_LEN(pPacket);
pTxD->LastSec0 = (pTxD->SDLen1 == 0) ? 1 : 0;
pTxD->LastSec1 = 1;
pDest = (PUCHAR)pTxWI;
pDest += TXWISize;
pHeader80211 = (PHEADER_802_11)pDest;
/* modify sequence number... */
if (pATEInfo->TxDoneCount == 0)
pATEInfo->seq = pHeader80211->Sequence;
else
pHeader80211->Sequence = ++pATEInfo->seq;
}
else
#endif /* RALINK_QA */
{
NdisZeroMemory(pTxD, TXD_SIZE);
RTMPWriteTxDescriptor(pAd, pTxD, FALSE, FIFO_EDCA);
/* build Tx descriptor */
pTxD->SDPtr0 = RTMP_GetPhysicalAddressLow (pTxRing->Cell[TxIdx].DmaBuf.AllocPa);
pTxD->SDLen0 = TXWISize + LENGTH_802_11;
pTxD->LastSec0 = 0;
pTxD->SDPtr1 = AllocPa;
pTxD->SDLen1 = GET_OS_PKT_LEN(pPacket);
pTxD->LastSec1 = 1;
}
#ifdef RT_BIG_ENDIAN
RTMPWIEndianChange(pAd, (PUCHAR)pTxWI, TYPE_TXWI);
RTMPFrameEndianChange(pAd, (((PUCHAR)pDMAHeaderBufVA) + TXWISize), DIR_WRITE, FALSE);
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
WriteBackToDescriptor((PUCHAR)pDestTxD, (PUCHAR)pTxD, FALSE, TYPE_TXD);
#endif /* RT_BIG_ENDIAN */
return 0;
}
PNDIS_PACKET GetPacketFromRxRing(
IN PRTMP_ADAPTER pAd,
OUT PRT28XX_RXD_STRUC pSaveRxD,
OUT BOOLEAN *pbReschedule,
IN OUT UINT32 *pRxPending)
{
PRXD_STRUC pRxD;
#ifdef RT_BIG_ENDIAN
PRXD_STRUC pDestRxD;
RXD_STRUC RxD;
#endif
PNDIS_PACKET pRxPacket = NULL;
PNDIS_PACKET pNewPacket;
PVOID AllocVa;
NDIS_PHYSICAL_ADDRESS AllocPa;
BOOLEAN bReschedule = FALSE;
RTMP_DMACB *pRxCell;
RTMP_SEM_LOCK(&pAd->RxRingLock);
if (*pRxPending == 0)
{
/* Get how may packets had been received*/
RTMP_IO_READ32(pAd, RX_DRX_IDX , &pAd->RxRing.RxDmaIdx);
if (pAd->RxRing.RxSwReadIdx == pAd->RxRing.RxDmaIdx)
{
/* no more rx packets*/
bReschedule = FALSE;
goto done;
}
/* get rx pending count*/
if (pAd->RxRing.RxDmaIdx > pAd->RxRing.RxSwReadIdx)
*pRxPending = pAd->RxRing.RxDmaIdx - pAd->RxRing.RxSwReadIdx;
else
*pRxPending = pAd->RxRing.RxDmaIdx + RX_RING_SIZE - pAd->RxRing.RxSwReadIdx;
#ifdef DESC_32B_SUPPORT
pRxCell = &pAd->RxRing.Cell[pAd->RxRing.RxSwReadIdx];
dma_cache_sync(NULL, pRxCell->AllocVa, RXD_SIZE, DMA_FROM_DEVICE);
#endif /* DESC_32B_SUPPORT */
}
pRxCell = &pAd->RxRing.Cell[pAd->RxRing.RxSwReadIdx];
/* flush dcache if no consistent memory is supported */
RTMP_DCACHE_FLUSH(pRxCell->AllocPa, RXD_SIZE);
#ifdef RT_BIG_ENDIAN
pDestRxD = (PRXD_STRUC) pRxCell->AllocVa;
RxD = *pDestRxD;
pRxD = &RxD;
RTMPDescriptorEndianChange((PUCHAR)pRxD, TYPE_RXD);
#else
/* Point to Rx indexed rx ring descriptor*/
pRxD = (PRXD_STRUC) pRxCell->AllocVa;
#endif
if (pRxD->DDONE == 0)
{
*pRxPending = 0;
/* DMAIndx had done but DDONE bit not ready*/
bReschedule = TRUE;
goto done;
}
#ifdef DESC_32B_SUPPORT
prefetch(&pAd->RxRing.Cell[(pAd->RxRing.RxSwReadIdx + 1) % RX_RING_SIZE].AllocVa);
#endif /* DESC_32B_SUPPORT */
/* return rx descriptor*/
NdisMoveMemory(pSaveRxD, pRxD, RXD_SIZE);
pNewPacket = RTMP_AllocateRxPacketBuffer(pAd, ((POS_COOKIE)(pAd->OS_Cookie))->pci_dev, RX_BUFFER_AGGRESIZE, FALSE, &AllocVa, &AllocPa);
if (pNewPacket)
{
/* unmap the rx buffer*/
PCI_UNMAP_SINGLE(pAd, pRxCell->DmaBuf.AllocPa,
pRxCell->DmaBuf.AllocSize, RTMP_PCI_DMA_FROMDEVICE);
/* flush dcache if no consistent memory is supported */
RTMP_DCACHE_FLUSH(pRxCell->DmaBuf.AllocPa, pRxCell->DmaBuf.AllocSize);
pRxPacket = pRxCell->pNdisPacket;
pRxCell->DmaBuf.AllocSize = RX_BUFFER_AGGRESIZE;
pRxCell->pNdisPacket = (PNDIS_PACKET) pNewPacket;
pRxCell->DmaBuf.AllocVa = AllocVa;
pRxCell->DmaBuf.AllocPa = AllocPa;
/* flush dcache if no consistent memory is supported */
RTMP_DCACHE_FLUSH(pRxCell->DmaBuf.AllocPa, pRxCell->DmaBuf.AllocSize);
/* update SDP0 to new buffer of rx packet */
pRxD->SDP0 = AllocPa;
#ifdef RX_DMA_SCATTER
pRxD->SDL0 = RX_BUFFER_AGGRESIZE;
#endif /* RX_DMA_SCATTER */
}
else
{
/*DBGPRINT(RT_DEBUG_TRACE,("No Rx Buffer\n"));*/
pRxPacket = NULL;
bReschedule = TRUE;
}
/* had handled one rx packet*/
*pRxPending = *pRxPending - 1;
#ifndef CACHE_LINE_32B
pRxD->DDONE = 0;
/* update rx descriptor and kick rx */
#ifdef RT_BIG_ENDIAN
RTMPDescriptorEndianChange((PUCHAR)pRxD, TYPE_RXD);
WriteBackToDescriptor((PUCHAR)pDestRxD, (PUCHAR)pRxD, FALSE, TYPE_RXD);
#endif
#ifdef DESC_32B_SUPPORT
dma_cache_sync(NULL, pRxCell->AllocVa, RXD_SIZE, DMA_TO_DEVICE);
#endif /* DESC_32B_SUPPORT */
INC_RING_INDEX(pAd->RxRing.RxSwReadIdx, RX_RING_SIZE);
pAd->RxRing.RxCpuIdx = (pAd->RxRing.RxSwReadIdx == 0) ? (RX_RING_SIZE-1) : (pAd->RxRing.RxSwReadIdx-1);
RTMP_IO_WRITE32(pAd, RX_CRX_IDX, pAd->RxRing.RxCpuIdx);
#else /* CACHE_LINE_32B */
/*
Because our RXD_SIZE is 16B, but if the cache line size is 32B, we
will suffer a problem as below:
1. We flush RXD 0, start address of RXD 0 is 32B-align.
Nothing occurs.
2. We flush RXD 1, start address of RXD 1 is 16B-align.
Because cache line size is 32B, cache must flush 32B, cannot flush
16B only, so RXD0 and RXD1 will be flushed.
But when traffic is busy, maybe RXD0 is updated by MAC, i.e.
DDONE bit is 1, so when the cache flushs RXD0, the DDONE bit will
be cleared to 0.
3. Then when we handle RXD0 in the future, we will find the DDONE bit
is 0 and we will wait for MAC to set it to 1 forever.
*/
if (pAd->RxRing.RxSwReadIdx & 0x01)
{
RTMP_DMACB *pRxCellLast;
#ifdef RT_BIG_ENDIAN
PRXD_STRUC pDestRxDLast;
#endif
/* 16B-align */
/* update last BD 32B-align, DMA Done bit = 0 */
pAd->RxRing.Cell[pAd->RxRing.RxSwReadIdx].LastBDInfo.DDONE = 0;
#ifdef RT_BIG_ENDIAN
pRxCellLast = &pAd->RxRing.Cell[pAd->RxRing.RxSwReadIdx - 1];
pDestRxDLast = (PRXD_STRUC) pRxCellLast->AllocVa;
RTMPDescriptorEndianChange((PUCHAR)&pAd->RxRing.Cell[pAd->RxRing.RxSwReadIdx].LastBDInfo, TYPE_RXD);
WriteBackToDescriptor((PUCHAR)pDestRxDLast, (PUCHAR)&pAd->RxRing.Cell[pAd->RxRing.RxSwReadIdx].LastBDInfo, FALSE, TYPE_RXD);
#endif
/* update current BD 16B-align, DMA Done bit = 0 */
pRxD->DDONE = 0;
#ifdef RT_BIG_ENDIAN
RTMPDescriptorEndianChange((PUCHAR)pRxD, TYPE_RXD);
WriteBackToDescriptor((PUCHAR)pDestRxD, (PUCHAR)pRxD, FALSE, TYPE_RXD);
#endif
/* flush cache from last BD */
RTMP_DCACHE_FLUSH(pRxCellLast->AllocPa, 32); /* use RXD_SIZE should be OK */
/* update SW read and CPU index */
INC_RING_INDEX(pAd->RxRing.RxSwReadIdx, RX_RING_SIZE);
pAd->RxRing.RxCpuIdx = (pAd->RxRing.RxSwReadIdx == 0) ? (RX_RING_SIZE-1) : (pAd->RxRing.RxSwReadIdx-1);
RTMP_IO_WRITE32(pAd, RX_CRX_IDX, pAd->RxRing.RxCpuIdx);
}
else
{
/* 32B-align */
/* do not set DDONE bit and backup it */
if (pAd->RxRing.RxSwReadIdx >= (RX_RING_SIZE-1))
{
DBGPRINT(RT_DEBUG_TRACE,
("Please change RX_RING_SIZE to mutiple of 2!\n"));
/* flush cache from current BD */
RTMP_DCACHE_FLUSH(pRxCell->AllocPa, RXD_SIZE);
/* update SW read and CPU index */
INC_RING_INDEX(pAd->RxRing.RxSwReadIdx, RX_RING_SIZE);
pAd->RxRing.RxCpuIdx = (pAd->RxRing.RxSwReadIdx == 0) ? (RX_RING_SIZE-1) : (pAd->RxRing.RxSwReadIdx-1);
RTMP_IO_WRITE32(pAd, RX_CRX_IDX, pAd->RxRing.RxCpuIdx);
}
else
{
/* backup current BD */
pRxCell = &pAd->RxRing.Cell[pAd->RxRing.RxSwReadIdx + 1];
pRxCell->LastBDInfo = *pRxD;
/* update CPU index */
INC_RING_INDEX(pAd->RxRing.RxSwReadIdx, RX_RING_SIZE);
}
}
#endif /* CACHE_LINE_32B */
done:
RTMP_SEM_UNLOCK(&pAd->RxRingLock);
*pbReschedule = bReschedule;
return pRxPacket;
}
void *GetPacketFromRxRing(struct rt_rtmp_adapter *pAd,
OUT PRT28XX_RXD_STRUC pSaveRxD,
OUT BOOLEAN * pbReschedule,
IN u32 * pRxPending)
{
struct rt_rxd * pRxD;
void *pRxPacket = NULL;
void *pNewPacket;
void *AllocVa;
dma_addr_t AllocPa;
BOOLEAN bReschedule = FALSE;
struct rt_rtmp_dmacb *pRxCell;
RTMP_SEM_LOCK(&pAd->RxRingLock);
if (*pRxPending == 0) {
/* Get how may packets had been received */
RTMP_IO_READ32(pAd, RX_DRX_IDX, &pAd->RxRing.RxDmaIdx);
if (pAd->RxRing.RxSwReadIdx == pAd->RxRing.RxDmaIdx) {
/* no more rx packets */
bReschedule = FALSE;
goto done;
}
/* get rx pending count */
if (pAd->RxRing.RxDmaIdx > pAd->RxRing.RxSwReadIdx)
*pRxPending =
pAd->RxRing.RxDmaIdx - pAd->RxRing.RxSwReadIdx;
else
*pRxPending =
pAd->RxRing.RxDmaIdx + RX_RING_SIZE -
pAd->RxRing.RxSwReadIdx;
}
pRxCell = &pAd->RxRing.Cell[pAd->RxRing.RxSwReadIdx];
/* Point to Rx indexed rx ring descriptor */
pRxD = (struct rt_rxd *) pRxCell->AllocVa;
if (pRxD->DDONE == 0) {
*pRxPending = 0;
/* DMAIndx had done but DDONE bit not ready */
bReschedule = TRUE;
goto done;
}
/* return rx descriptor */
NdisMoveMemory(pSaveRxD, pRxD, RXD_SIZE);
pNewPacket =
RTMP_AllocateRxPacketBuffer(pAd, RX_BUFFER_AGGRESIZE, FALSE,
&AllocVa, &AllocPa);
if (pNewPacket) {
/* unmap the rx buffer */
PCI_UNMAP_SINGLE(pAd, pRxCell->DmaBuf.AllocPa,
pRxCell->DmaBuf.AllocSize, PCI_DMA_FROMDEVICE);
pRxPacket = pRxCell->pNdisPacket;
pRxCell->DmaBuf.AllocSize = RX_BUFFER_AGGRESIZE;
pRxCell->pNdisPacket = (void *)pNewPacket;
pRxCell->DmaBuf.AllocVa = AllocVa;
pRxCell->DmaBuf.AllocPa = AllocPa;
/* update SDP0 to new buffer of rx packet */
pRxD->SDP0 = AllocPa;
} else {
/*DBGPRINT(RT_DEBUG_TRACE,("No Rx Buffer\n")); */
pRxPacket = NULL;
bReschedule = TRUE;
}
pRxD->DDONE = 0;
/* had handled one rx packet */
*pRxPending = *pRxPending - 1;
/* update rx descriptor and kick rx */
INC_RING_INDEX(pAd->RxRing.RxSwReadIdx, RX_RING_SIZE);
pAd->RxRing.RxCpuIdx =
(pAd->RxRing.RxSwReadIdx ==
0) ? (RX_RING_SIZE - 1) : (pAd->RxRing.RxSwReadIdx - 1);
RTMP_IO_WRITE32(pAd, RX_CRX_IDX, pAd->RxRing.RxCpuIdx);
done:
RTMP_SEM_UNLOCK(&pAd->RxRingLock);
*pbReschedule = bReschedule;
return pRxPacket;
}
PNDIS_PACKET GetPacketFromRxRing(
IN PRTMP_ADAPTER pAd,
OUT PRT28XX_RXD_STRUC pSaveRxD,
OUT BOOLEAN *pbReschedule,
IN OUT UINT32 *pRxPending)
{
PRXD_STRUC pRxD;
#ifdef RT_BIG_ENDIAN
PRXD_STRUC pDestRxD;
RXD_STRUC RxD;
#endif
PNDIS_PACKET pRxPacket = NULL;
PNDIS_PACKET pNewPacket;
PVOID AllocVa;
NDIS_PHYSICAL_ADDRESS AllocPa;
BOOLEAN bReschedule = FALSE;
RTMP_SEM_LOCK(&pAd->RxRingLock);
if (*pRxPending == 0)
{
RTMP_IO_READ32(pAd, RX_DRX_IDX , &pAd->RxRing.RxDmaIdx);
if (pAd->RxRing.RxSwReadIdx == pAd->RxRing.RxDmaIdx)
{
bReschedule = FALSE;
goto done;
}
if (pAd->RxRing.RxDmaIdx > pAd->RxRing.RxSwReadIdx)
*pRxPending = pAd->RxRing.RxDmaIdx - pAd->RxRing.RxSwReadIdx;
else
*pRxPending = pAd->RxRing.RxDmaIdx + RX_RING_SIZE - pAd->RxRing.RxSwReadIdx;
}
#ifdef RT_BIG_ENDIAN
pDestRxD = (PRXD_STRUC) pAd->RxRing.Cell[pAd->RxRing.RxSwReadIdx].AllocVa;
RxD = *pDestRxD;
pRxD = &RxD;
RTMPDescriptorEndianChange((PUCHAR)pRxD, TYPE_RXD);
#else
pRxD = (PRXD_STRUC) pAd->RxRing.Cell[pAd->RxRing.RxSwReadIdx].AllocVa;
#endif
if (pRxD->DDONE == 0)
{
*pRxPending = 0;
bReschedule = TRUE;
goto done;
}
NdisMoveMemory(pSaveRxD, pRxD, RXD_SIZE);
pNewPacket = RTMP_AllocateRxPacketBuffer(pAd, RX_BUFFER_AGGRESIZE, FALSE, &AllocVa, &AllocPa);
if (pNewPacket)
{
PCI_UNMAP_SINGLE(pAd, pAd->RxRing.Cell[pAd->RxRing.RxSwReadIdx].DmaBuf.AllocPa,
pAd->RxRing.Cell[pAd->RxRing.RxSwReadIdx].DmaBuf.AllocSize, PCI_DMA_FROMDEVICE);
pRxPacket = pAd->RxRing.Cell[pAd->RxRing.RxSwReadIdx].pNdisPacket;
pAd->RxRing.Cell[pAd->RxRing.RxSwReadIdx].DmaBuf.AllocSize = RX_BUFFER_AGGRESIZE;
pAd->RxRing.Cell[pAd->RxRing.RxSwReadIdx].pNdisPacket = (PNDIS_PACKET) pNewPacket;
pAd->RxRing.Cell[pAd->RxRing.RxSwReadIdx].DmaBuf.AllocVa = AllocVa;
pAd->RxRing.Cell[pAd->RxRing.RxSwReadIdx].DmaBuf.AllocPa = AllocPa;
pRxD->SDP0 = AllocPa;
}
else
{
pRxPacket = NULL;
bReschedule = TRUE;
}
pRxD->DDONE = 0;
*pRxPending = *pRxPending - 1;
#ifdef RT_BIG_ENDIAN
RTMPDescriptorEndianChange((PUCHAR)pRxD, TYPE_RXD);
WriteBackToDescriptor((PUCHAR)pDestRxD, (PUCHAR)pRxD, FALSE, TYPE_RXD);
#endif
INC_RING_INDEX(pAd->RxRing.RxSwReadIdx, RX_RING_SIZE);
pAd->RxRing.RxCpuIdx = (pAd->RxRing.RxSwReadIdx == 0) ? (RX_RING_SIZE-1) : (pAd->RxRing.RxSwReadIdx-1);
RTMP_IO_WRITE32(pAd, RX_CRX_IDX, pAd->RxRing.RxCpuIdx);
done:
RTMP_SEM_UNLOCK(&pAd->RxRingLock);
*pbReschedule = bReschedule;
return pRxPacket;
}
NDIS_STATUS RTMPAllocTxRxRingMemory(
IN PRTMP_ADAPTER pAd)
{
NDIS_STATUS Status = NDIS_STATUS_SUCCESS;
ULONG RingBasePaHigh;
ULONG RingBasePaLow;
PVOID RingBaseVa;
INT index, num;
PTXD_STRUC pTxD;
PRXD_STRUC pRxD;
ULONG ErrorValue = 0;
PRTMP_TX_RING pTxRing;
PRTMP_DMABUF pDmaBuf;
PNDIS_PACKET pPacket;
DBGPRINT(RT_DEBUG_TRACE, ("--> RTMPAllocTxRxRingMemory\n"));
do
{
for (num=0; num<NUM_OF_TX_RING; num++)
{
ULONG BufBasePaHigh;
ULONG BufBasePaLow;
PVOID BufBaseVa;
pAd->TxDescRing[num].AllocSize = TX_RING_SIZE * TXD_SIZE;
RTMP_AllocateTxDescMemory(
pAd,
num,
pAd->TxDescRing[num].AllocSize,
FALSE,
&pAd->TxDescRing[num].AllocVa,
&pAd->TxDescRing[num].AllocPa);
if (pAd->TxDescRing[num].AllocVa == NULL)
{
ErrorValue = ERRLOG_OUT_OF_SHARED_MEMORY;
DBGPRINT_ERR(("Failed to allocate a big buffer\n"));
Status = NDIS_STATUS_RESOURCES;
break;
}
NdisZeroMemory(pAd->TxDescRing[num].AllocVa, pAd->TxDescRing[num].AllocSize);
RingBasePaHigh = RTMP_GetPhysicalAddressHigh(pAd->TxDescRing[num].AllocPa);
RingBasePaLow = RTMP_GetPhysicalAddressLow (pAd->TxDescRing[num].AllocPa);
RingBaseVa = pAd->TxDescRing[num].AllocVa;
pAd->TxBufSpace[num].AllocSize = TX_RING_SIZE * TX_DMA_1ST_BUFFER_SIZE;
RTMP_AllocateFirstTxBuffer(
pAd,
num,
pAd->TxBufSpace[num].AllocSize,
FALSE,
&pAd->TxBufSpace[num].AllocVa,
&pAd->TxBufSpace[num].AllocPa);
if (pAd->TxBufSpace[num].AllocVa == NULL)
{
ErrorValue = ERRLOG_OUT_OF_SHARED_MEMORY;
DBGPRINT_ERR(("Failed to allocate a big buffer\n"));
Status = NDIS_STATUS_RESOURCES;
break;
}
NdisZeroMemory(pAd->TxBufSpace[num].AllocVa, pAd->TxBufSpace[num].AllocSize);
BufBasePaHigh = RTMP_GetPhysicalAddressHigh(pAd->TxBufSpace[num].AllocPa);
BufBasePaLow = RTMP_GetPhysicalAddressLow (pAd->TxBufSpace[num].AllocPa);
BufBaseVa = pAd->TxBufSpace[num].AllocVa;
pTxRing = &pAd->TxRing[num];
for (index = 0; index < TX_RING_SIZE; index++)
{
pTxRing->Cell[index].pNdisPacket = NULL;
pTxRing->Cell[index].pNextNdisPacket = NULL;
pTxRing->Cell[index].AllocSize = TXD_SIZE;
pTxRing->Cell[index].AllocVa = RingBaseVa;
RTMP_SetPhysicalAddressHigh(pTxRing->Cell[index].AllocPa, RingBasePaHigh);
RTMP_SetPhysicalAddressLow (pTxRing->Cell[index].AllocPa, RingBasePaLow);
pDmaBuf = &pTxRing->Cell[index].DmaBuf;
pDmaBuf->AllocSize = TX_DMA_1ST_BUFFER_SIZE;
pDmaBuf->AllocVa = BufBaseVa;
RTMP_SetPhysicalAddressHigh(pDmaBuf->AllocPa, BufBasePaHigh);
RTMP_SetPhysicalAddressLow(pDmaBuf->AllocPa, BufBasePaLow);
pTxD = (PTXD_STRUC) pTxRing->Cell[index].AllocVa;
pTxD->SDPtr0 = BufBasePaLow;
pTxD->DMADONE = 1;
RingBasePaLow += TXD_SIZE;
RingBaseVa = (PUCHAR) RingBaseVa + TXD_SIZE;
BufBasePaLow += TX_DMA_1ST_BUFFER_SIZE;
BufBaseVa = (PUCHAR) BufBaseVa + TX_DMA_1ST_BUFFER_SIZE;
}
DBGPRINT(RT_DEBUG_TRACE, ("TxRing[%d]: total %d entry allocated\n", num, index));
}
if (Status == NDIS_STATUS_RESOURCES)
break;
pAd->MgmtDescRing.AllocSize = MGMT_RING_SIZE * TXD_SIZE;
RTMP_AllocateMgmtDescMemory(
pAd,
pAd->MgmtDescRing.AllocSize,
FALSE,
&pAd->MgmtDescRing.AllocVa,
&pAd->MgmtDescRing.AllocPa);
if (pAd->MgmtDescRing.AllocVa == NULL)
{
ErrorValue = ERRLOG_OUT_OF_SHARED_MEMORY;
DBGPRINT_ERR(("Failed to allocate a big buffer\n"));
Status = NDIS_STATUS_RESOURCES;
break;
}
NdisZeroMemory(pAd->MgmtDescRing.AllocVa, pAd->MgmtDescRing.AllocSize);
RingBasePaHigh = RTMP_GetPhysicalAddressHigh(pAd->MgmtDescRing.AllocPa);
RingBasePaLow = RTMP_GetPhysicalAddressLow (pAd->MgmtDescRing.AllocPa);
RingBaseVa = pAd->MgmtDescRing.AllocVa;
for (index = 0; index < MGMT_RING_SIZE; index++)
{
pAd->MgmtRing.Cell[index].pNdisPacket = NULL;
pAd->MgmtRing.Cell[index].pNextNdisPacket = NULL;
pAd->MgmtRing.Cell[index].AllocSize = TXD_SIZE;
pAd->MgmtRing.Cell[index].AllocVa = RingBaseVa;
RTMP_SetPhysicalAddressHigh(pAd->MgmtRing.Cell[index].AllocPa, RingBasePaHigh);
RTMP_SetPhysicalAddressLow (pAd->MgmtRing.Cell[index].AllocPa, RingBasePaLow);
RingBasePaLow += TXD_SIZE;
RingBaseVa = (PUCHAR) RingBaseVa + TXD_SIZE;
pTxD = (PTXD_STRUC) pAd->MgmtRing.Cell[index].AllocVa;
pTxD->DMADONE = 1;
}
DBGPRINT(RT_DEBUG_TRACE, ("MGMT Ring: total %d entry allocated\n", index));
pAd->RxDescRing.AllocSize = RX_RING_SIZE * RXD_SIZE;
RTMP_AllocateRxDescMemory(
pAd,
pAd->RxDescRing.AllocSize,
FALSE,
&pAd->RxDescRing.AllocVa,
&pAd->RxDescRing.AllocPa);
if (pAd->RxDescRing.AllocVa == NULL)
{
ErrorValue = ERRLOG_OUT_OF_SHARED_MEMORY;
DBGPRINT_ERR(("Failed to allocate a big buffer\n"));
Status = NDIS_STATUS_RESOURCES;
break;
}
NdisZeroMemory(pAd->RxDescRing.AllocVa, pAd->RxDescRing.AllocSize);
printk("RX DESC %p size = %ld\n", pAd->RxDescRing.AllocVa,
pAd->RxDescRing.AllocSize);
RingBasePaHigh = RTMP_GetPhysicalAddressHigh(pAd->RxDescRing.AllocPa);
RingBasePaLow = RTMP_GetPhysicalAddressLow (pAd->RxDescRing.AllocPa);
RingBaseVa = pAd->RxDescRing.AllocVa;
for (index = 0; index < RX_RING_SIZE; index++)
{
pAd->RxRing.Cell[index].AllocSize = RXD_SIZE;
pAd->RxRing.Cell[index].AllocVa = RingBaseVa;
RTMP_SetPhysicalAddressHigh(pAd->RxRing.Cell[index].AllocPa, RingBasePaHigh);
RTMP_SetPhysicalAddressLow (pAd->RxRing.Cell[index].AllocPa, RingBasePaLow);
RingBasePaLow += RXD_SIZE;
RingBaseVa = (PUCHAR) RingBaseVa + RXD_SIZE;
pDmaBuf = &pAd->RxRing.Cell[index].DmaBuf;
pDmaBuf->AllocSize = RX_BUFFER_AGGRESIZE;
pPacket = RTMP_AllocateRxPacketBuffer(
pAd,
pDmaBuf->AllocSize,
FALSE,
&pDmaBuf->AllocVa,
&pDmaBuf->AllocPa);
pAd->RxRing.Cell[index].pNdisPacket = pPacket;
if (pDmaBuf->AllocVa == NULL)
{
ErrorValue = ERRLOG_OUT_OF_SHARED_MEMORY;
DBGPRINT_ERR(("Failed to allocate RxRing's 1st buffer\n"));
Status = NDIS_STATUS_RESOURCES;
break;
}
NdisZeroMemory(pDmaBuf->AllocVa, pDmaBuf->AllocSize);
pRxD = (PRXD_STRUC) pAd->RxRing.Cell[index].AllocVa;
pRxD->SDP0 = RTMP_GetPhysicalAddressLow(pDmaBuf->AllocPa);
pRxD->DDONE = 0;
}
DBGPRINT(RT_DEBUG_TRACE, ("Rx Ring: total %d entry allocated\n", index));
} while (FALSE);
NdisZeroMemory(&pAd->FragFrame, sizeof(FRAGMENT_FRAME));
pAd->FragFrame.pFragPacket = RTMP_AllocateFragPacketBuffer(pAd, RX_BUFFER_NORMSIZE);
if (pAd->FragFrame.pFragPacket == NULL)
{
Status = NDIS_STATUS_RESOURCES;
}
if (Status != NDIS_STATUS_SUCCESS)
{
NdisWriteErrorLogEntry(
pAd->AdapterHandle,
NDIS_ERROR_CODE_OUT_OF_RESOURCES,
1,
ErrorValue);
}
DBGPRINT_S(Status, ("<-- RTMPAllocTxRxRingMemory, Status=%x\n", Status));
return Status;
}
#ifdef RALINK_28xx_QA
if (pAd->ate.bQATxStart == TRUE)
{
pPacket = RTMP_AllocateRxPacketBuffer(pAd, pAd->ate.DLen + 0x100, FALSE, &AllocVa, &AllocPa);
}
else
#endif // RALINK_28xx_QA //
{
pPacket = RTMP_AllocateRxPacketBuffer(pAd, pAd->ate.TxLength, FALSE, &AllocVa, &AllocPa);
}
/*
==========================================================================
Description:
Setup Frame format.
NOTE:
This routine should only be used in ATE mode.
==========================================================================
*/
INT ATESetUpFrame(
IN PRTMP_ADAPTER pAd,
IN UINT32 TxIdx)
{
PATE_INFO pATEInfo = &(pAd->ate);
UINT pos = 0;
TXINFO_STRUC *pTxInfo;
TXD_STRUC *pTxD;
#ifdef RT_BIG_ENDIAN
TXD_STRUC *pDestTxD;
UCHAR tx_hw_info[TXD_SIZE];
#endif /* RT_BIG_ENDIAN */
PNDIS_PACKET pPacket=NULL;
PUCHAR pDest=NULL;
PVOID AllocVa=NULL;
NDIS_PHYSICAL_ADDRESS AllocPa;
HTTRANSMIT_SETTING TxHTPhyMode;
RTMP_TX_RING *pTxRing = &pAd->TxRing[QID_AC_BE];
TXWI_STRUC *pTxWI = (TXWI_STRUC *)pTxRing->Cell[TxIdx].DmaBuf.AllocVa;
PUCHAR pDMAHeaderBufVA = (PUCHAR) pTxRing->Cell[TxIdx].DmaBuf.AllocVa;
UINT8 TXWISize = pAd->chipCap.TXWISize;
#ifdef RALINK_QA
PHEADER_802_11 pHeader80211;
#endif /* RALINK_QA */
UCHAR bw, sgi, stbc, mcs, phy_mode, frag, cfack, ts, ampdu, ack, nseq, bawinsize, pkt_id, txop;
USHORT byte_cnt;
bw = sgi = stbc = mcs = phy_mode = frag = cfack = ts =0;
ampdu = ack = nseq = bawinsize = pkt_id = txop = 0;
byte_cnt = 0;
#ifdef RLT_MAC
if (pAd->chipCap.hif_type == HIF_RLT)
{
bw = pATEInfo->TxWI.TXWI_N.BW;
sgi = pATEInfo->TxWI.TXWI_N.ShortGI;
stbc = pATEInfo->TxWI.TXWI_N.STBC;
mcs = pATEInfo->TxWI.TXWI_N.MCS;
phy_mode = pATEInfo->TxWI.TXWI_N.PHYMODE;
frag = pATEInfo->TxWI.TXWI_N.FRAG;
cfack = pATEInfo->TxWI.TXWI_N.CFACK,
ts = pATEInfo->TxWI.TXWI_N.TS;
ampdu = pATEInfo->TxWI.TXWI_N.AMPDU;
ack = pATEInfo->TxWI.TXWI_N.ACK;
nseq = pATEInfo->TxWI.TXWI_N.NSEQ;
bawinsize =pATEInfo->TxWI.TXWI_N.BAWinSize;
byte_cnt = pATEInfo->TxWI.TXWI_N.MPDUtotalByteCnt;
pkt_id = pATEInfo->TxWI.TXWI_N.TxPktId;
txop = pATEInfo->TxWI.TXWI_N.txop;
cfack = pATEInfo->TxWI.TXWI_N.CFACK;
}
#endif /* RLT_MAC */
/* fill TxWI */
TxHTPhyMode.field.BW = bw;
TxHTPhyMode.field.ShortGI = sgi;
TxHTPhyMode.field.STBC = stbc;
TxHTPhyMode.field.MCS = mcs;
TxHTPhyMode.field.MODE = phy_mode;
if (pATEInfo->bQATxStart == TRUE)
{
/* always use QID_AC_BE and FIFO_EDCA */
ATEWriteTxWI(pAd, pTxWI, frag, cfack,
ts, ampdu, ack,
nseq, bawinsize, 0,
byte_cnt, pkt_id, 0, 0,
txop, cfack,
&TxHTPhyMode);
#ifdef TXBF_SUPPORT
#ifdef RELEASE_EXCLUDE
/* It will affect transmit data rate ??? But QA is tested... */
#endif /* RELEASE_EXCLUDE */
#ifdef RLT_MAC
if (IS_MT76x0(pAd))
{
/* Must copy rsv bits to actual TxWI */
// pTxWI->TXWI_N.rsv = pATEInfo->TxWI.TXWI_N.rsv;
pTxWI->TXWI_N.iTxBF = pATEInfo->TxWI.TXWI_N.iTxBF;
pTxWI->TXWI_N.Sounding = pATEInfo->TxWI.TXWI_N.Sounding;
pTxWI->TXWI_N.eTxBF = pATEInfo->TxWI.TXWI_N.eTxBF;
// pTxWI->TXWI_N.Autofallback = pATEInfo->TxWI.TXWI_N.Autofallback;
pTxWI->TXWI_N.NDPSndBW = pATEInfo->TxWI.TXWI_N.NDPSndBW;
pTxWI->TXWI_N.NDPSndRate = pATEInfo->TxWI.TXWI_N.NDPSndRate;
}
#endif /* RLT_MAC */
#endif /* TXBF_SUPPORT */
}
else
{
ATEWriteTxWI(pAd, pTxWI, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE,
4, 0, pATEInfo->TxLength, 0, 0, 0, IFS_HTTXOP, FALSE, &TxHTPhyMode);
}
/* fill 802.11 header */
#ifdef RALINK_QA
if (pATEInfo->bQATxStart == TRUE)
{
NdisMoveMemory(pDMAHeaderBufVA + TXWISize, pATEInfo->Header, pATEInfo->HLen);
}
else
#endif /* RALINK_QA */
{
pATEInfo->HLen = LENGTH_802_11;
#ifdef TXBF_SUPPORT
TemplateFrame[0] = 0x08; /* Data */
TemplateFrame[1] = 0x00;
if (pATEInfo->bTxBF && pATEInfo->txSoundingMode!=0)
{
/* QoS Data */
pATEInfo->HLen = 32;
TemplateFrame[0] = 0x88;
TemplateFrame[1] = 0x80;
switch (pATEInfo->txSoundingMode)
{
case 1:
/* Data Sounding */
TemplateFrame[28] = pAd->CommonCfg.ETxBfNoncompress? 0x80: 0xc0;
TemplateFrame[29] = 0x00;
break;
case 2:
case 3:
/* 2 or 3 Stream NDP */
TemplateFrame[28] = pAd->CommonCfg.ETxBfNoncompress? 0x80: 0xc0;
TemplateFrame[29] = 0x01; /* NDP Announce */
break;
default:
TemplateFrame[28] = TemplateFrame[29] = 0x0;
}
}
#endif /* TXBF_SUPPORT */
NdisMoveMemory(pDMAHeaderBufVA + TXWISize, TemplateFrame, pATEInfo->HLen);
NdisMoveMemory(pDMAHeaderBufVA + TXWISize + 4, pATEInfo->Addr1, MAC_ADDR_LEN);
NdisMoveMemory(pDMAHeaderBufVA + TXWISize + 10, pATEInfo->Addr2, MAC_ADDR_LEN);
NdisMoveMemory(pDMAHeaderBufVA + TXWISize + 16, pATEInfo->Addr3, MAC_ADDR_LEN);
}
#ifdef RT_BIG_ENDIAN
RTMPFrameEndianChange(pAd, (((PUCHAR)pDMAHeaderBufVA) + TXWISize), DIR_READ, FALSE);
#endif /* RT_BIG_ENDIAN */
/* alloc buffer for payload */
#ifdef RALINK_QA
if ((pATEInfo->bQATxStart == TRUE) && (pATEInfo->DLen != 0))
{
pPacket = RTMP_AllocateRxPacketBuffer(pAd, ((POS_COOKIE)(pAd->OS_Cookie))->pci_dev,
pATEInfo->DLen + 0x100, FALSE, &AllocVa, &AllocPa);
}
else
#endif /* RALINK_QA */
{
pPacket = RTMP_AllocateRxPacketBuffer(pAd, ((POS_COOKIE)(pAd->OS_Cookie))->pci_dev,
pATEInfo->TxLength, FALSE, &AllocVa, &AllocPa);
}
/* error check */
if (pPacket == NULL)
{
pATEInfo->TxCount = 0;
DBGPRINT_ERR(("%s : fail to alloc packet space.\n", __FUNCTION__));
return -1;
}
pTxRing->Cell[TxIdx].pNdisPacket = pPacket;
pDest = (PUCHAR) AllocVa;
#ifdef RALINK_QA
if ((pATEInfo->bQATxStart == TRUE) && (pATEInfo->DLen != 0))
{
GET_OS_PKT_LEN(pPacket) = pATEInfo->DLen;
#ifndef LINUX
GET_OS_PKT_TOTAL_LEN(pPacket) = pATEInfo->DLen;
#endif /* LIMUX */
}
else
#endif /* RALINK_QA */
{
GET_OS_PKT_LEN(pPacket) = pATEInfo->TxLength - pATEInfo->HLen;
#ifndef LINUX
GET_OS_PKT_TOTAL_LEN(pPacket) = pATEInfo->TxLength - pATEInfo->HLen;
#endif /* LINUX */
}
/* prepare frame payload */
#ifdef RALINK_QA
if ((pATEInfo->bQATxStart == TRUE) && (pATEInfo->DLen != 0))
{
/* copy pattern to payload */
if ((pATEInfo->PLen != 0))
{
for (pos = 0; pos < pATEInfo->DLen; pos += pATEInfo->PLen)
{
memcpy(GET_OS_PKT_DATAPTR(pPacket) + pos, pATEInfo->Pattern, pATEInfo->PLen);
}
}
}
else
#endif /* RALINK_QA */
{
for (pos = 0; pos < GET_OS_PKT_LEN(pPacket); pos++)
{
#ifdef RELEASE_EXCLUDE
/* kurtis: 0xAA ATE test EVM will be positive */
#endif /* RELEASE_EXCLUDE */
/* default payload is 0xA5 */
pDest[pos] = pATEInfo->Payload;
}
}
/* build Tx descriptor */
#ifndef RT_BIG_ENDIAN
pTxD = (PTXD_STRUC) pTxRing->Cell[TxIdx].AllocVa;
pTxInfo = (TXINFO_STRUC *)(pTxRing->Cell[TxIdx].AllocVa + sizeof(TXD_STRUC));
#else
pDestTxD = (PTXD_STRUC)pTxRing->Cell[TxIdx].AllocVa;
NdisMoveMemory(&tx_hw_info[0], (UCHAR *)pDestTxD, TXD_SIZE);
pTxD = (TXD_STRUC *)&tx_hw_info[0];
pTxInfo = (TXINFO_STRUC *)(&tx_hw_info[0] + sizeof(TXD_STRUC));
#endif /* !RT_BIG_ENDIAN */
{
/* prepare TxD */
TX_BLK txblk;
txblk.SrcBufLen = GET_OS_PKT_LEN(pPacket);
txblk.pSrcBufData = AllocVa;
NdisZeroMemory(pTxD, TXD_SIZE);
/* build Tx descriptor */
pTxD->SDPtr0 = RTMP_GetPhysicalAddressLow (pTxRing->Cell[TxIdx].DmaBuf.AllocPa);
pTxD->SDLen0 = TXWISize + pATEInfo->HLen;
pTxD->LastSec0 = 0;
pTxD->SDPtr1 = PCI_MAP_SINGLE(pAd, &txblk, 0, 1, RTMP_PCI_DMA_TODEVICE);
pTxD->SDLen1 = GET_OS_PKT_LEN(pPacket);
pTxD->LastSec1 = 1;
ral_write_txd(pAd, pTxD, pTxInfo, FALSE, FIFO_EDCA);
}
#ifdef RALINK_QA
if (pATEInfo->bQATxStart == TRUE)
{
pDest = (PUCHAR)pTxWI;
pDest += TXWISize;
pHeader80211 = (PHEADER_802_11)pDest;
/* modify sequence number... */
if (pATEInfo->TxDoneCount == 0)
pATEInfo->seq = pHeader80211->Sequence;
else
pHeader80211->Sequence = ++pATEInfo->seq;
}
#endif /* RALINK_QA */
#ifdef RT_BIG_ENDIAN
RTMPWIEndianChange(pAd, (PUCHAR)pTxWI, TYPE_TXWI);
RTMPFrameEndianChange(pAd, (((PUCHAR)pDMAHeaderBufVA) + TXWISize), DIR_WRITE, FALSE);
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
WriteBackToDescriptor((PUCHAR)pDestTxD, (PUCHAR)pTxD, FALSE, TYPE_TXD);
#endif /* RT_BIG_ENDIAN */
return 0;
}
/*
========================================================================
Routine Description:
Allocate DMA memory blocks for send, receive
Arguments:
Adapter Pointer to our adapter
Return Value:
NDIS_STATUS_SUCCESS
NDIS_STATUS_FAILURE
NDIS_STATUS_RESOURCES
IRQL = PASSIVE_LEVEL
Note:
========================================================================
*/
NDIS_STATUS RTMPAllocTxRxRingMemory(
IN PRTMP_ADAPTER pAd)
{
NDIS_STATUS Status = NDIS_STATUS_SUCCESS;
ULONG RingBasePaHigh;
ULONG RingBasePaLow;
PVOID RingBaseVa;
INT index, num;
PTXD_STRUC pTxD;
PRXD_STRUC pRxD;
ULONG ErrorValue = 0;
PRTMP_TX_RING pTxRing;
PRTMP_DMABUF pDmaBuf;
PNDIS_PACKET pPacket;
DBGPRINT(RT_DEBUG_TRACE, ("--> RTMPAllocTxRxRingMemory\n"));
do
{
//
// Allocate all ring descriptors, include TxD, RxD, MgmtD.
// Although each size is different, to prevent cacheline and alignment
// issue, I intentional set them all to 64 bytes.
//
for (num=0; num<NUM_OF_TX_RING; num++)
{
ULONG BufBasePaHigh;
ULONG BufBasePaLow;
PVOID BufBaseVa;
//
// Allocate Tx ring descriptor's memory (5 TX rings = 4 ACs + 1 HCCA)
//
pAd->TxDescRing[num].AllocSize = TX_RING_SIZE * TXD_SIZE;
RTMP_AllocateTxDescMemory(
pAd,
num,
pAd->TxDescRing[num].AllocSize,
FALSE,
&pAd->TxDescRing[num].AllocVa,
&pAd->TxDescRing[num].AllocPa);
if (pAd->TxDescRing[num].AllocVa == NULL)
{
ErrorValue = ERRLOG_OUT_OF_SHARED_MEMORY;
DBGPRINT_ERR(("Failed to allocate a big buffer\n"));
Status = NDIS_STATUS_RESOURCES;
break;
}
// Zero init this memory block
NdisZeroMemory(pAd->TxDescRing[num].AllocVa, pAd->TxDescRing[num].AllocSize);
// Save PA & VA for further operation
RingBasePaHigh = RTMP_GetPhysicalAddressHigh(pAd->TxDescRing[num].AllocPa);
RingBasePaLow = RTMP_GetPhysicalAddressLow (pAd->TxDescRing[num].AllocPa);
RingBaseVa = pAd->TxDescRing[num].AllocVa;
//
// Allocate all 1st TXBuf's memory for this TxRing
//
pAd->TxBufSpace[num].AllocSize = TX_RING_SIZE * TX_DMA_1ST_BUFFER_SIZE;
RTMP_AllocateFirstTxBuffer(
pAd,
num,
pAd->TxBufSpace[num].AllocSize,
FALSE,
&pAd->TxBufSpace[num].AllocVa,
&pAd->TxBufSpace[num].AllocPa);
if (pAd->TxBufSpace[num].AllocVa == NULL)
{
ErrorValue = ERRLOG_OUT_OF_SHARED_MEMORY;
DBGPRINT_ERR(("Failed to allocate a big buffer\n"));
Status = NDIS_STATUS_RESOURCES;
break;
}
// Zero init this memory block
NdisZeroMemory(pAd->TxBufSpace[num].AllocVa, pAd->TxBufSpace[num].AllocSize);
// Save PA & VA for further operation
BufBasePaHigh = RTMP_GetPhysicalAddressHigh(pAd->TxBufSpace[num].AllocPa);
BufBasePaLow = RTMP_GetPhysicalAddressLow (pAd->TxBufSpace[num].AllocPa);
BufBaseVa = pAd->TxBufSpace[num].AllocVa;
//
// Initialize Tx Ring Descriptor and associated buffer memory
//
pTxRing = &pAd->TxRing[num];
for (index = 0; index < TX_RING_SIZE; index++)
{
pTxRing->Cell[index].pNdisPacket = NULL;
pTxRing->Cell[index].pNextNdisPacket = NULL;
// Init Tx Ring Size, Va, Pa variables
pTxRing->Cell[index].AllocSize = TXD_SIZE;
pTxRing->Cell[index].AllocVa = RingBaseVa;
RTMP_SetPhysicalAddressHigh(pTxRing->Cell[index].AllocPa, RingBasePaHigh);
RTMP_SetPhysicalAddressLow (pTxRing->Cell[index].AllocPa, RingBasePaLow);
// Setup Tx Buffer size & address. only 802.11 header will store in this space
pDmaBuf = &pTxRing->Cell[index].DmaBuf;
pDmaBuf->AllocSize = TX_DMA_1ST_BUFFER_SIZE;
pDmaBuf->AllocVa = BufBaseVa;
RTMP_SetPhysicalAddressHigh(pDmaBuf->AllocPa, BufBasePaHigh);
RTMP_SetPhysicalAddressLow(pDmaBuf->AllocPa, BufBasePaLow);
// link the pre-allocated TxBuf to TXD
pTxD = (PTXD_STRUC) pTxRing->Cell[index].AllocVa;
pTxD->SDPtr0 = BufBasePaLow;
// advance to next ring descriptor address
pTxD->DMADONE = 1;
RingBasePaLow += TXD_SIZE;
RingBaseVa = (PUCHAR) RingBaseVa + TXD_SIZE;
// advance to next TxBuf address
BufBasePaLow += TX_DMA_1ST_BUFFER_SIZE;
BufBaseVa = (PUCHAR) BufBaseVa + TX_DMA_1ST_BUFFER_SIZE;
}
DBGPRINT(RT_DEBUG_TRACE, ("TxRing[%d]: total %d entry allocated\n", num, index));
}
if (Status == NDIS_STATUS_RESOURCES)
break;
//
// Allocate MGMT ring descriptor's memory except Tx ring which allocated eariler
//
pAd->MgmtDescRing.AllocSize = MGMT_RING_SIZE * TXD_SIZE;
RTMP_AllocateMgmtDescMemory(
pAd,
pAd->MgmtDescRing.AllocSize,
FALSE,
&pAd->MgmtDescRing.AllocVa,
&pAd->MgmtDescRing.AllocPa);
if (pAd->MgmtDescRing.AllocVa == NULL)
{
ErrorValue = ERRLOG_OUT_OF_SHARED_MEMORY;
DBGPRINT_ERR(("Failed to allocate a big buffer\n"));
Status = NDIS_STATUS_RESOURCES;
break;
}
// Zero init this memory block
NdisZeroMemory(pAd->MgmtDescRing.AllocVa, pAd->MgmtDescRing.AllocSize);
// Save PA & VA for further operation
RingBasePaHigh = RTMP_GetPhysicalAddressHigh(pAd->MgmtDescRing.AllocPa);
RingBasePaLow = RTMP_GetPhysicalAddressLow (pAd->MgmtDescRing.AllocPa);
RingBaseVa = pAd->MgmtDescRing.AllocVa;
//
// Initialize MGMT Ring and associated buffer memory
//
for (index = 0; index < MGMT_RING_SIZE; index++)
{
pAd->MgmtRing.Cell[index].pNdisPacket = NULL;
pAd->MgmtRing.Cell[index].pNextNdisPacket = NULL;
// Init MGMT Ring Size, Va, Pa variables
pAd->MgmtRing.Cell[index].AllocSize = TXD_SIZE;
pAd->MgmtRing.Cell[index].AllocVa = RingBaseVa;
RTMP_SetPhysicalAddressHigh(pAd->MgmtRing.Cell[index].AllocPa, RingBasePaHigh);
RTMP_SetPhysicalAddressLow (pAd->MgmtRing.Cell[index].AllocPa, RingBasePaLow);
// Offset to next ring descriptor address
RingBasePaLow += TXD_SIZE;
RingBaseVa = (PUCHAR) RingBaseVa + TXD_SIZE;
// link the pre-allocated TxBuf to TXD
pTxD = (PTXD_STRUC) pAd->MgmtRing.Cell[index].AllocVa;
pTxD->DMADONE = 1;
// no pre-allocated buffer required in MgmtRing for scatter-gather case
}
DBGPRINT(RT_DEBUG_TRACE, ("MGMT Ring: total %d entry allocated\n", index));
//
// Allocate RX ring descriptor's memory except Tx ring which allocated eariler
//
pAd->RxDescRing.AllocSize = RX_RING_SIZE * RXD_SIZE;
RTMP_AllocateRxDescMemory(
pAd,
pAd->RxDescRing.AllocSize,
FALSE,
&pAd->RxDescRing.AllocVa,
&pAd->RxDescRing.AllocPa);
if (pAd->RxDescRing.AllocVa == NULL)
{
ErrorValue = ERRLOG_OUT_OF_SHARED_MEMORY;
DBGPRINT_ERR(("Failed to allocate a big buffer\n"));
Status = NDIS_STATUS_RESOURCES;
break;
}
// Zero init this memory block
NdisZeroMemory(pAd->RxDescRing.AllocVa, pAd->RxDescRing.AllocSize);
printk("RX DESC %p size = %ld\n", pAd->RxDescRing.AllocVa,
pAd->RxDescRing.AllocSize);
// Save PA & VA for further operation
RingBasePaHigh = RTMP_GetPhysicalAddressHigh(pAd->RxDescRing.AllocPa);
RingBasePaLow = RTMP_GetPhysicalAddressLow (pAd->RxDescRing.AllocPa);
RingBaseVa = pAd->RxDescRing.AllocVa;
//
// Initialize Rx Ring and associated buffer memory
//
for (index = 0; index < RX_RING_SIZE; index++)
{
// Init RX Ring Size, Va, Pa variables
pAd->RxRing.Cell[index].AllocSize = RXD_SIZE;
pAd->RxRing.Cell[index].AllocVa = RingBaseVa;
RTMP_SetPhysicalAddressHigh(pAd->RxRing.Cell[index].AllocPa, RingBasePaHigh);
RTMP_SetPhysicalAddressLow (pAd->RxRing.Cell[index].AllocPa, RingBasePaLow);
// Offset to next ring descriptor address
RingBasePaLow += RXD_SIZE;
RingBaseVa = (PUCHAR) RingBaseVa + RXD_SIZE;
// Setup Rx associated Buffer size & allocate share memory
pDmaBuf = &pAd->RxRing.Cell[index].DmaBuf;
pDmaBuf->AllocSize = RX_BUFFER_AGGRESIZE;
pPacket = RTMP_AllocateRxPacketBuffer(
pAd,
pDmaBuf->AllocSize,
FALSE,
&pDmaBuf->AllocVa,
&pDmaBuf->AllocPa);
/* keep allocated rx packet */
pAd->RxRing.Cell[index].pNdisPacket = pPacket;
// Error handling
if (pDmaBuf->AllocVa == NULL)
{
ErrorValue = ERRLOG_OUT_OF_SHARED_MEMORY;
DBGPRINT_ERR(("Failed to allocate RxRing's 1st buffer\n"));
Status = NDIS_STATUS_RESOURCES;
break;
}
// Zero init this memory block
NdisZeroMemory(pDmaBuf->AllocVa, pDmaBuf->AllocSize);
// Write RxD buffer address & allocated buffer length
pRxD = (PRXD_STRUC) pAd->RxRing.Cell[index].AllocVa;
pRxD->SDP0 = RTMP_GetPhysicalAddressLow(pDmaBuf->AllocPa);
pRxD->DDONE = 0;
}
DBGPRINT(RT_DEBUG_TRACE, ("Rx Ring: total %d entry allocated\n", index));
} while (FALSE);
NdisZeroMemory(&pAd->FragFrame, sizeof(FRAGMENT_FRAME));
pAd->FragFrame.pFragPacket = RTMP_AllocateFragPacketBuffer(pAd, RX_BUFFER_NORMSIZE);
if (pAd->FragFrame.pFragPacket == NULL)
{
Status = NDIS_STATUS_RESOURCES;
}
if (Status != NDIS_STATUS_SUCCESS)
{
// Log error inforamtion
NdisWriteErrorLogEntry(
pAd->AdapterHandle,
NDIS_ERROR_CODE_OUT_OF_RESOURCES,
1,
ErrorValue);
}
DBGPRINT_S(Status, ("<-- RTMPAllocTxRxRingMemory, Status=%x\n", Status));
return Status;
}
INT ATESetUpNDPAFrame(
IN PRTMP_ADAPTER pAd,
IN UINT32 TxIdx)
{
PATE_INFO pATEInfo = &(pAd->ate);
UINT pos = 0;
TXINFO_STRUC *pTxInfo;
TXD_STRUC *pTxD;
#ifdef RT_BIG_ENDIAN
TXD_STRUC *pDestTxD;
UCHAR tx_hw_info[TXD_SIZE];
#endif /* RT_BIG_ENDIAN */
PNDIS_PACKET pPacket=NULL;
PUCHAR pDest=NULL;
PVOID AllocVa=NULL;
NDIS_PHYSICAL_ADDRESS AllocPa;
HTTRANSMIT_SETTING TxHTPhyMode;
UCHAR *buf;
VHT_NDPA_FRAME *vht_ndpa;
SNDING_STA_INFO *sta_info;
RTMP_TX_RING *pTxRing = &pAd->TxRing[QID_AC_BE];
TXWI_STRUC *pTxWI = (TXWI_STRUC *)pTxRing->Cell[TxIdx].DmaBuf.AllocVa;
PUCHAR pDMAHeaderBufVA = (PUCHAR) pTxRing->Cell[TxIdx].DmaBuf.AllocVa;
UINT8 TXWISize = pAd->chipCap.TXWISize;
#ifdef RALINK_QA
PHEADER_802_11 pHeader80211;
#endif /* RALINK_QA */
UCHAR bw, sgi, stbc, mcs, phy_mode, frag, cfack, ts, ampdu, ack, nseq, bawinsize, pkt_id, txop;
USHORT byte_cnt;
bw = sgi = stbc = mcs = phy_mode = frag = cfack = ts =0;
ampdu = ack = nseq = bawinsize = pkt_id = txop = 0;
byte_cnt = 0;
#ifdef RLT_MAC
if (pAd->chipCap.hif_type == HIF_RLT) {
bw = pATEInfo->TxWI.TXWI_N.BW;
sgi = pATEInfo->TxWI.TXWI_N.ShortGI;
stbc = pATEInfo->TxWI.TXWI_N.STBC;
mcs = pATEInfo->TxWI.TXWI_N.MCS;
phy_mode = pATEInfo->TxWI.TXWI_N.PHYMODE;
frag = pATEInfo->TxWI.TXWI_N.FRAG;
cfack = pATEInfo->TxWI.TXWI_N.CFACK,
ts = pATEInfo->TxWI.TXWI_N.TS;
ampdu = pATEInfo->TxWI.TXWI_N.AMPDU;
ack = pATEInfo->TxWI.TXWI_N.ACK;
nseq = pATEInfo->TxWI.TXWI_N.NSEQ;
bawinsize =pATEInfo->TxWI.TXWI_N.BAWinSize;
byte_cnt = pATEInfo->TxWI.TXWI_N.MPDUtotalByteCnt;
pkt_id = pATEInfo->TxWI.TXWI_N.TxPktId;
txop = pATEInfo->TxWI.TXWI_N.txop;
cfack = pATEInfo->TxWI.TXWI_N.CFACK;
}
#endif /* RLT_MAC */
#ifdef RTMP_MAC
if (pAd->chipCap.hif_type == HIF_RTMP) {
bw = pATEInfo->TxWI.TXWI_O.BW;
sgi = pATEInfo->TxWI.TXWI_O.ShortGI;
stbc = pATEInfo->TxWI.TXWI_O.STBC;
mcs = pATEInfo->TxWI.TXWI_O.MCS;
phy_mode = pATEInfo->TxWI.TXWI_O.PHYMODE;
frag = pATEInfo->TxWI.TXWI_O.FRAG;
cfack = pATEInfo->TxWI.TXWI_O.CFACK,
ts = pATEInfo->TxWI.TXWI_O.TS;
ampdu = pATEInfo->TxWI.TXWI_O.AMPDU;
ack = pATEInfo->TxWI.TXWI_O.ACK;
nseq = pATEInfo->TxWI.TXWI_O.NSEQ;
bawinsize =pATEInfo->TxWI.TXWI_O.BAWinSize;
byte_cnt = pATEInfo->TxWI.TXWI_O.MPDUtotalByteCnt;
pkt_id = pATEInfo->TxWI.TXWI_O.PacketId;
txop = pATEInfo->TxWI.TXWI_O.txop;
cfack = pATEInfo->TxWI.TXWI_O.CFACK;
}
#endif /* RTMP_MAC */
/* fill TxWI */
TxHTPhyMode.field.BW = bw;
TxHTPhyMode.field.ShortGI = sgi;
TxHTPhyMode.field.STBC = stbc;
TxHTPhyMode.field.MCS = mcs;
TxHTPhyMode.field.MODE = phy_mode;
if (pATEInfo->bQATxStart == TRUE)
{
/* always use QID_AC_BE and FIFO_EDCA */
ATEWriteTxWI(pAd, pTxWI, frag, cfack,
ts, ampdu, ack,
nseq, bawinsize, 0,
byte_cnt, pkt_id, 0, 0,
txop, cfack,
&TxHTPhyMode);
#ifdef TXBF_SUPPORT
#ifdef RTMP_MAC
if (IS_RT2883(pAd) || IS_RT3883(pAd) || IS_RT3593(pAd))
{
/* Must copy rsv bits to actual TxWI */
//pTxWI->TXWI_O.rsv = pATEInfo->TxWI.TXWI_O.rsv;
pTxWI->TXWI_O.iTxBF = pATEInfo->TxWI.TXWI_O.iTxBF;
pTxWI->TXWI_O.Sounding = pATEInfo->TxWI.TXWI_O.Sounding;
pTxWI->TXWI_O.eTxBF = pATEInfo->TxWI.TXWI_O.eTxBF;
pTxWI->TXWI_O.Autofallback = pATEInfo->TxWI.TXWI_O.Autofallback;
pTxWI->TXWI_O.NDPSndBW = pATEInfo->TxWI.TXWI_O.NDPSndBW;
pTxWI->TXWI_O.NDPSndRate = pATEInfo->TxWI.TXWI_O.NDPSndRate;
}
#endif
#ifdef RLT_MAC
if (IS_MT76x2(pAd))
{
/* Must copy rsv bits to actual TxWI */
pTxWI->TXWI_N.Rsv4 = pATEInfo->TxWI.TXWI_N.Rsv4;
pTxWI->TXWI_N.iTxBF = pATEInfo->TxWI.TXWI_N.iTxBF;
pTxWI->TXWI_N.Sounding = pATEInfo->TxWI.TXWI_N.Sounding;
pTxWI->TXWI_N.eTxBF = pATEInfo->TxWI.TXWI_N.eTxBF;
//pTxWI->TXWI_N.Autofallback = pATEInfo->TxWI.TXWI_N.Autofallback;
pTxWI->TXWI_N.NDPSndBW = pATEInfo->TxWI.TXWI_N.NDPSndBW;
pTxWI->TXWI_N.NDPSndRate = pATEInfo->TxWI.TXWI_N.NDPSndRate;
pTxWI->TXWI_N.TXBF_PT_SCA = pATEInfo->TxWI.TXWI_N.TXBF_PT_SCA;
}
#endif
#endif /* TXBF_SUPPORT */
}
else
{
ATEWriteTxWI(pAd, pTxWI, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE,
4, 0, pATEInfo->TxLength, 0, 0, 0, IFS_HTTXOP, FALSE, &TxHTPhyMode);
#ifdef TXBF_SUPPORT
if (pATEInfo->bTxBF == 1)
{
#ifdef RTMP_MAC
if (IS_RT2883(pAd) || IS_RT3883(pAd) || IS_RT3593(pAd))
{
//pTxWI->TXWI_O.rsv = 0;
pTxWI->TXWI_O.iTxBF = pATEInfo->TxWI.TXWI_O.iTxBF;
pTxWI->TXWI_O.Sounding = (pATEInfo->txSoundingMode == 1 ? 1 : 0);
pTxWI->TXWI_O.eTxBF = pATEInfo->TxWI.TXWI_O.eTxBF;
pTxWI->TXWI_O.Autofallback = pATEInfo->TxWI.TXWI_O.Autofallback;
pTxWI->TXWI_O.NDPSndBW = pATEInfo->TxWI.TXWI_O.BW;
if (pATEInfo->txSoundingMode == 3)
pTxWI->TXWI_O.NDPSndRate = 2;
else if (pATEInfo->txSoundingMode == 2)
pTxWI->TXWI_O.NDPSndRate = 1;
else
pTxWI->TXWI_O.NDPSndRate = 0;
}
#endif
#ifdef RLT_MAC
if (IS_MT76x2(pAd))
{
pTxWI->TXWI_N.Rsv4 = 0;
pTxWI->TXWI_N.iTxBF = pATEInfo->TxWI.TXWI_N.iTxBF;
pTxWI->TXWI_N.Sounding = (pATEInfo->txSoundingMode == 1 ? 1 : 0);
pTxWI->TXWI_N.eTxBF = pATEInfo->TxWI.TXWI_N.eTxBF;
//pTxWI->TXWI_N.Autofallback = pATEInfo->TxWI.TXWI_N.Autofallback;
pTxWI->TXWI_N.NDPSndBW = pATEInfo->TxWI.TXWI_N.BW;
if (pATEInfo->txSoundingMode == 3)
pTxWI->TXWI_N.NDPSndRate = 2;
else if (pATEInfo->txSoundingMode == 2)
pTxWI->TXWI_N.NDPSndRate = 1;
else
pTxWI->TXWI_N.NDPSndRate = 0;
pTxWI->TXWI_N.TXBF_PT_SCA = pATEInfo->TxWI.TXWI_N.TXBF_PT_SCA;
}
#endif
}
#endif /* TXBF_SUPPORT */
}
/* fill 802.11 header */
#ifdef RALINK_QA
if (pATEInfo->bQATxStart == TRUE)
{
NdisMoveMemory(pDMAHeaderBufVA + TXWISize, pATEInfo->Header, pATEInfo->HLen);
}
else
#endif /* RALINK_QA */
{
buf = (pDMAHeaderBufVA + TXWISize);
vht_ndpa = (VHT_NDPA_FRAME *)buf;
pATEInfo->HLen = sizeof(VHT_NDPA_FRAME);
vht_ndpa->fc.Type = FC_TYPE_CNTL;
vht_ndpa->fc.SubType = SUBTYPE_VHT_NDPA;
COPY_MAC_ADDR(vht_ndpa->ra, pATEInfo->Addr1);
COPY_MAC_ADDR(vht_ndpa->ta, pATEInfo->Addr3);
hex_dump("NDPA Frame",buf,pATEInfo->HLen);
/* Currnetly we only support 1 STA for a VHT DNPA */
sta_info = vht_ndpa->sta_info;
sta_info->aid12 = 1;
sta_info->fb_type = SNDING_FB_SU;
sta_info->nc_idx = 0;
vht_ndpa->token.token_num = 0;
vht_ndpa->duration = 100;
}
#ifdef RT_BIG_ENDIAN
RTMPFrameEndianChange(pAd, (((PUCHAR)pDMAHeaderBufVA) + TXWISize), DIR_READ, FALSE);
#endif /* RT_BIG_ENDIAN */
/* alloc buffer for payload */
#ifdef RALINK_QA
if ((pATEInfo->bQATxStart == TRUE) && (pATEInfo->DLen != 0))
{
pPacket = RTMP_AllocateRxPacketBuffer(pAd, ((POS_COOKIE)(pAd->OS_Cookie))->pci_dev,
pATEInfo->DLen + 0x100, FALSE, &AllocVa, &AllocPa);
}
else
#endif /* RALINK_QA */
{
pPacket = RTMP_AllocateRxPacketBuffer(pAd, ((POS_COOKIE)(pAd->OS_Cookie))->pci_dev,
pATEInfo->TxLength, FALSE, &AllocVa, &AllocPa);
}
if (pPacket == NULL)
{
pATEInfo->TxCount = 0;
DBGPRINT_ERR(("%s : fail to alloc packet space.\n", __FUNCTION__));
return -1;
}
pTxRing->Cell[TxIdx].pNextNdisPacket = pPacket;
pDest = (PUCHAR) AllocVa;
#ifdef RALINK_QA
if ((pATEInfo->bQATxStart == TRUE) && (pATEInfo->DLen != 0))
{
GET_OS_PKT_LEN(pPacket) = pATEInfo->DLen;
#ifndef LINUX
GET_OS_PKT_TOTAL_LEN(pPacket) = pATEInfo->DLen;
#endif /* LIMUX */
}
else
#endif /* RALINK_QA */
{
GET_OS_PKT_LEN(pPacket) = pATEInfo->TxLength - pATEInfo->HLen;
#ifndef LINUX
GET_OS_PKT_TOTAL_LEN(pPacket) = pATEInfo->TxLength - pATEInfo->HLen;
#endif /* LINUX */
}
/* prepare frame payload */
#ifdef RALINK_QA
if ((pATEInfo->bQATxStart == TRUE) && (pATEInfo->DLen != 0))
{
/* copy pattern to payload */
if ((pATEInfo->PLen != 0))
{
for (pos = 0; pos < pATEInfo->DLen; pos += pATEInfo->PLen)
{
memcpy(GET_OS_PKT_DATAPTR(pPacket) + pos, pATEInfo->Pattern, pATEInfo->PLen);
}
}
}
else
#endif /* RALINK_QA */
{
for (pos = 0; pos < GET_OS_PKT_LEN(pPacket); pos++)
{
pDest[pos] = 0x00;
}
}
/* build Tx descriptor */
#ifndef RT_BIG_ENDIAN
pTxD = (PTXD_STRUC) pTxRing->Cell[TxIdx].AllocVa;
pTxInfo = (TXINFO_STRUC *)(pTxRing->Cell[TxIdx].AllocVa + sizeof(TXD_STRUC));
#else
pDestTxD = (PTXD_STRUC)pTxRing->Cell[TxIdx].AllocVa;
NdisMoveMemory(&tx_hw_info[0], (UCHAR *)pDestTxD, TXD_SIZE);
pTxD = (TXD_STRUC *)&tx_hw_info[0];
pTxInfo = (TXINFO_STRUC *)(&tx_hw_info[0] + sizeof(TXD_STRUC));
#endif /* !RT_BIG_ENDIAN */
#ifdef RALINK_QA
if (pATEInfo->bQATxStart == TRUE)
{
/* prepare TxD */
NdisZeroMemory(pTxD, TXD_SIZE);
/* build Tx descriptor */
pTxD->SDPtr0 = RTMP_GetPhysicalAddressLow(pTxRing->Cell[TxIdx].DmaBuf.AllocPa);
pTxD->SDLen0 = TXWISize + pATEInfo->HLen;
pTxD->SDPtr1 = AllocPa;
pTxD->SDLen1 = GET_OS_PKT_LEN(pPacket);
pTxD->LastSec0 = (pTxD->SDLen1 == 0) ? 1 : 0;
pTxD->LastSec1 = 1;
ral_write_txd(pAd, pTxD, pTxInfo, FALSE, FIFO_EDCA);
pDest = (PUCHAR)pTxWI;
pDest += TXWISize;
pHeader80211 = (PHEADER_802_11)pDest;
/* modify sequence number... */
if (pATEInfo->TxDoneCount == 0)
pATEInfo->seq = pHeader80211->Sequence;
else
pHeader80211->Sequence = ++pATEInfo->seq;
}
else
#endif /* RALINK_QA */
{
TX_BLK txblk;
txblk.SrcBufLen = GET_OS_PKT_LEN(pPacket);
txblk.pSrcBufData = AllocVa;
NdisZeroMemory(pTxD, TXD_SIZE);
/* build Tx descriptor */
pTxD->SDPtr0 = RTMP_GetPhysicalAddressLow (pTxRing->Cell[TxIdx].DmaBuf.AllocPa);
pTxD->SDLen0 = TXWISize + pATEInfo->HLen /* LENGTH_802_11 */;
pTxD->SDPtr1 = PCI_MAP_SINGLE(pAd, &txblk, 0, 1, RTMP_PCI_DMA_TODEVICE);
pTxD->SDLen1 = GET_OS_PKT_LEN(pPacket);
pTxD->LastSec0 = (pTxD->SDLen1 == 0) ? 1 : 0;
pTxD->LastSec1 = 1;
ral_write_txd(pAd, pTxD, pTxInfo, FALSE, FIFO_EDCA);
}
#ifdef RT_BIG_ENDIAN
RTMPWIEndianChange(pAd, (PUCHAR)pTxWI, TYPE_TXWI);
RTMPFrameEndianChange(pAd, (((PUCHAR)pDMAHeaderBufVA) + TXWISize), DIR_WRITE, FALSE);
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
WriteBackToDescriptor((PUCHAR)pDestTxD, (PUCHAR)pTxD, FALSE, TYPE_TXD);
#endif /* RT_BIG_ENDIAN */
return 0;
}
