UIHostComboEditorPrivate::UIHostComboEditorPrivate()
: m_pReleaseTimer(0)
, m_fStartNewSequence(true)
{
/* Configure widget: */
setAttribute(Qt::WA_NativeWindow);
setContextMenuPolicy(Qt::NoContextMenu);
setSizePolicy(QSizePolicy::MinimumExpanding, QSizePolicy::Expanding);
connect(this, SIGNAL(selectionChanged()), this, SLOT(sltDeselect()));
/* Setup release-pending-keys timer: */
m_pReleaseTimer = new QTimer(this);
m_pReleaseTimer->setInterval(200);
connect(m_pReleaseTimer, SIGNAL(timeout()), this, SLOT(sltReleasePendingKeys()));
#ifdef Q_WS_X11
/* Initialize the X keyboard subsystem: */
initMappedX11Keyboard(QX11Info::display(), vboxGlobal().settings().publicProperty("GUI/RemapScancodes"));
#endif /* Q_WS_X11 */
#ifdef Q_WS_MAC
m_uDarwinKeyModifiers = 0;
UICocoaApplication::instance()->registerForNativeEvents(RT_BIT_32(10) | RT_BIT_32(11) | RT_BIT_32(12) /* NSKeyDown | NSKeyUp | | NSFlagsChanged */, UIHostComboEditorPrivate::darwinEventHandlerProc, this);
::DarwinGrabKeyboard(false /* just modifiers */);
#endif /* Q_WS_MAC */
}
UIHostComboEditorPrivate::~UIHostComboEditorPrivate()
{
#ifdef Q_WS_MAC
::DarwinReleaseKeyboard();
UICocoaApplication::instance()->unregisterForNativeEvents(RT_BIT_32(10) | RT_BIT_32(11) | RT_BIT_32(12) /* NSKeyDown | NSKeyUp | | NSFlagsChanged */, UIHostComboEditorPrivate::darwinEventHandlerProc, this);
#endif /* Q_WS_MAC */
}
/**
* Returns the build type for matching components.
*
* @returns Build type value.
*/
uint32_t vmmGetBuildType(void)
{
uint32_t uRet = 0xbeef0000;
#ifdef DEBUG
uRet |= RT_BIT_32(0);
#endif
#ifdef VBOX_WITH_STATISTICS
uRet |= RT_BIT_32(1);
#endif
return uRet;
}
RTDECL(unsigned) ASMBitLastSetU32(uint32_t u32)
{
int32_t iBit = 32;
while (iBit-- > 0)
if (u32 & RT_BIT_32(iBit))
return iBit + 1;
return 0;
}
RTDECL(unsigned) ASMBitFirstSetU32(uint32_t u32)
{
uint32_t iBit;
for (iBit = 0; iBit < 32; iBit++)
if (u32 & RT_BIT_32(iBit))
return iBit + 1;
return 0;
}
/**
* \#DB (Debug event) handler.
*
* @returns VBox status code.
* VINF_SUCCESS means we completely handled this trap,
* other codes are passed execution to host context.
*
* @param pVM The cross context VM structure.
* @param pVCpu The cross context virtual CPU structure.
* @param pRegFrame Pointer to the register frame for the trap.
* @param uDr6 The DR6 hypervisor register value.
* @param fAltStepping Alternative stepping indicator.
*/
VMMRZ_INT_DECL(int) DBGFRZTrap01Handler(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCUINTREG uDr6, bool fAltStepping)
{
#ifdef IN_RC
const bool fInHyper = !(pRegFrame->ss.Sel & X86_SEL_RPL) && !pRegFrame->eflags.Bits.u1VM;
#else
NOREF(pRegFrame);
const bool fInHyper = false;
#endif
/** @todo Intel docs say that X86_DR6_BS has the highest priority... */
/*
* A breakpoint?
*/
if (uDr6 & (X86_DR6_B0 | X86_DR6_B1 | X86_DR6_B2 | X86_DR6_B3))
{
Assert(X86_DR6_B0 == 1 && X86_DR6_B1 == 2 && X86_DR6_B2 == 4 && X86_DR6_B3 == 8);
for (unsigned iBp = 0; iBp < RT_ELEMENTS(pVM->dbgf.s.aHwBreakpoints); iBp++)
{
if ( ((uint32_t)uDr6 & RT_BIT_32(iBp))
&& pVM->dbgf.s.aHwBreakpoints[iBp].enmType == DBGFBPTYPE_REG)
{
pVCpu->dbgf.s.iActiveBp = pVM->dbgf.s.aHwBreakpoints[iBp].iBp;
pVCpu->dbgf.s.fSingleSteppingRaw = false;
LogFlow(("DBGFRZTrap03Handler: hit hw breakpoint %d at %04x:%RGv\n",
pVM->dbgf.s.aHwBreakpoints[iBp].iBp, pRegFrame->cs.Sel, pRegFrame->rip));
return fInHyper ? VINF_EM_DBG_HYPER_BREAKPOINT : VINF_EM_DBG_BREAKPOINT;
}
}
}
/*
* Single step?
* Are we single stepping or is it the guest?
*/
if ( (uDr6 & X86_DR6_BS)
&& (fInHyper || pVCpu->dbgf.s.fSingleSteppingRaw || fAltStepping))
{
pVCpu->dbgf.s.fSingleSteppingRaw = false;
LogFlow(("DBGFRZTrap01Handler: single step at %04x:%RGv\n", pRegFrame->cs.Sel, pRegFrame->rip));
return fInHyper ? VINF_EM_DBG_HYPER_STEPPED : VINF_EM_DBG_STEPPED;
}
/*
* Either an ICEBP in hypervisor code or a guest related debug exception
* of sorts.
*/
if (RT_UNLIKELY(fInHyper))
{
LogFlow(("DBGFRZTrap01Handler: unabled bp at %04x:%RGv\n", pRegFrame->cs.Sel, pRegFrame->rip));
return VERR_DBGF_HYPER_DB_XCPT;
}
LogFlow(("DBGFRZTrap01Handler: guest debug event %#x at %04x:%RGv!\n", (uint32_t)uDr6, pRegFrame->cs.Sel, pRegFrame->rip));
return VINF_EM_RAW_GUEST_TRAP;
}
/**
* \#DB (Debug event) handler.
*
* @returns VBox status code.
* VINF_SUCCESS means we completely handled this trap,
* other codes are passed execution to host context.
*
* @param pVM Pointer to the VM.
* @param pVCpu Pointer to the VMCPU.
* @param pRegFrame Pointer to the register frame for the trap.
* @param uDr6 The DR6 register value.
*/
VMMRZDECL(int) DBGFRZTrap01Handler(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCUINTREG uDr6)
{
#ifdef IN_RC
const bool fInHyper = !(pRegFrame->ss.Sel & X86_SEL_RPL) && !pRegFrame->eflags.Bits.u1VM;
#else
const bool fInHyper = false;
#endif
/** @todo Intel docs say that X86_DR6_BS has the highest priority... */
/*
* A breakpoint?
*/
if (uDr6 & (X86_DR6_B0 | X86_DR6_B1 | X86_DR6_B2 | X86_DR6_B3))
{
Assert(X86_DR6_B0 == 1 && X86_DR6_B1 == 2 && X86_DR6_B2 == 4 && X86_DR6_B3 == 8);
for (unsigned iBp = 0; iBp < RT_ELEMENTS(pVM->dbgf.s.aHwBreakpoints); iBp++)
{
if ( ((uint32_t)uDr6 & RT_BIT_32(iBp))
&& pVM->dbgf.s.aHwBreakpoints[iBp].enmType == DBGFBPTYPE_REG)
{
pVCpu->dbgf.s.iActiveBp = pVM->dbgf.s.aHwBreakpoints[iBp].iBp;
pVCpu->dbgf.s.fSingleSteppingRaw = false;
LogFlow(("DBGFRZTrap03Handler: hit hw breakpoint %d at %04x:%RGv\n",
pVM->dbgf.s.aHwBreakpoints[iBp].iBp, pRegFrame->cs.Sel, pRegFrame->rip));
return fInHyper ? VINF_EM_DBG_HYPER_BREAKPOINT : VINF_EM_DBG_BREAKPOINT;
}
}
}
/*
* Single step?
* Are we single stepping or is it the guest?
*/
if ( (uDr6 & X86_DR6_BS)
&& (fInHyper || pVCpu->dbgf.s.fSingleSteppingRaw))
{
pVCpu->dbgf.s.fSingleSteppingRaw = false;
LogFlow(("DBGFRZTrap01Handler: single step at %04x:%RGv\n", pRegFrame->cs.Sel, pRegFrame->rip));
return fInHyper ? VINF_EM_DBG_HYPER_STEPPED : VINF_EM_DBG_STEPPED;
}
#ifdef IN_RC
/*
* Currently we only implement single stepping in the guest,
* so we'll bitch if this is not a BS event.
*/
AssertMsg(uDr6 & X86_DR6_BS, ("hey! we're not doing guest BPs yet! dr6=%RTreg %04x:%RGv\n",
uDr6, pRegFrame->cs.Sel, pRegFrame->rip));
#endif
LogFlow(("DBGFRZTrap01Handler: guest debug event %RTreg at %04x:%RGv!\n", uDr6, pRegFrame->cs.Sel, pRegFrame->rip));
return fInHyper ? VERR_DBGF_HYPER_DB_XCPT : VINF_EM_RAW_GUEST_TRAP;
}
/**
* UART core IRQ request callback.
*
* @returns nothing.
* @param pDevIns The device instance.
* @param pUart The UART requesting an IRQ update.
* @param iLUN The UART index.
* @param iLvl IRQ level requested.
*/
PDMBOTHCBDECL(void) ox958IrqReq(PPDMDEVINS pDevIns, PUARTCORE pUart, unsigned iLUN, int iLvl)
{
RT_NOREF(pUart);
PDEVOX958 pThis = PDMINS_2_DATA(pDevIns, PDEVOX958);
if (iLvl)
ASMAtomicOrU32(&pThis->u32RegIrqStsGlob, RT_BIT_32(iLUN));
else
ASMAtomicAndU32(&pThis->u32RegIrqStsGlob, ~RT_BIT_32(iLUN));
ox958IrqUpdate(pThis);
}
static char *stringifyAppendUnknownFlags(uint32_t fFlags, char *pszBuf, size_t *pcbBuf, bool fWithSpace)
{
for (unsigned iBit = 0; iBit < 32; iBit++)
if (fFlags & RT_BIT_32(iBit))
{
char szTmp[32]; /* lazy bird */
RTStrPrintf(szTmp, sizeof(szTmp), "BIT(%d)", iBit);
pszBuf = stringifyAppend(pszBuf, pcbBuf, szTmp, fWithSpace);
fWithSpace = true;
}
return pszBuf;
}
/* set irq level. If an edge is detected, then the IRR is set to 1 */
DECLINLINE(void) pic_set_irq1(PPICSTATE pPic, int irq, int level, uint32_t uTagSrc)
{
Log(("pic_set_irq1: irq=%d level=%d\n", irq, level));
int mask = 1 << irq;
if (pPic->elcr & mask)
{
/* level triggered */
if (level)
{
Log2(("pic_set_irq1(ls) irr=%d irrnew=%d\n", pPic->irr, pPic->irr | mask));
pPic->irr |= mask;
pPic->last_irr |= mask;
}
else
{
Log2(("pic_set_irq1(lc) irr=%d irrnew=%d\n", pPic->irr, pPic->irr & ~mask));
pPic->irr &= ~mask;
pPic->last_irr &= ~mask;
}
}
else
{
/* edge triggered */
if (level)
{
if ((pPic->last_irr & mask) == 0)
{
Log2(("pic_set_irq1 irr=%x last_irr=%x\n", pPic->irr | mask, pPic->last_irr));
pPic->irr |= mask;
}
pPic->last_irr |= mask;
}
else
{
pPic->irr &= ~mask;
pPic->last_irr &= ~mask;
}
}
/* Save the tag. */
if (level)
{
if (!pPic->auTags[irq])
pPic->auTags[irq] = uTagSrc;
else
pPic->auTags[irq] |= RT_BIT_32(31);
}
DumpPICState(pPic, "pic_set_irq1");
}
/**
* Issues a command to the SATA controller and waits for completion.
*/
static void ahci_port_cmd_sync(ahci_t __far *ahci, uint8_t val)
{
uint16_t io_base;
uint8_t port;
port = ahci->cur_port;
io_base = ahci->iobase;
if (port != 0xff)
{
/* Prepare the command header. */
ahci->aCmdHdr[0] = ((uint32_t)ahci->cur_prd << 16) | RT_BIT_32(7) | val;
ahci->aCmdHdr[1] = 0;
ahci->aCmdHdr[2] = ahci_addr_to_phys(&ahci->abCmd[0]);
/* Enable Command and FIS receive engine. */
ahci_ctrl_set_bits(io_base, AHCI_PORT_REG(port, AHCI_REG_PORT_CMD),
AHCI_REG_PORT_CMD_FRE | AHCI_REG_PORT_CMD_ST);
/* Queue command. */
VBOXAHCI_PORT_WRITE_REG(io_base, port, AHCI_REG_PORT_CI, 0x1);
/* Wait for a D2H FIS. */
DBG_AHCI("AHCI: Waiting for D2H FIS\n");
while (ahci_ctrl_is_bit_set(io_base, AHCI_PORT_REG(port, AHCI_REG_PORT_IS),
AHCI_REG_PORT_IS_DHRS | AHCI_REG_PORT_IS_TFES) == 0)
{
// This is where we'd need some kind of a yield functionality...
}
ahci_ctrl_set_bits(io_base, AHCI_PORT_REG(port, AHCI_REG_PORT_IS),
AHCI_REG_PORT_IS_DHRS); /* Acknowledge received D2H FIS. */
/* Disable command engine. */
ahci_ctrl_clear_bits(io_base, AHCI_PORT_REG(port, AHCI_REG_PORT_CMD),
AHCI_REG_PORT_CMD_ST);
/** @todo: Examine status. */
}
else
DBG_AHCI("AHCI: Invalid port given\n");
}
RTDECL(void) ASMBitClear(volatile void *pvBitmap, int32_t iBit)
{
uint8_t volatile *pau8Bitmap = (uint8_t volatile *)pvBitmap;
pau8Bitmap[iBit / 8] &= ~((uint8_t)RT_BIT_32(iBit & 7));
}
void darwinUnregisterForUnifiedToolbarContextMenuEvents(QMainWindow *pWindow)
{
UICocoaApplication::instance()->unregisterForNativeEvents(RT_BIT_32(3) /* NSRightMouseDown */, ::darwinUnifiedToolbarEvents, pWindow);
}
/**
* \#DB (Debug event) handler.
*
* @returns VBox status code.
* VINF_SUCCESS means we completely handled this trap,
* other codes are passed execution to host context.
*
* @param pVM The cross context VM structure.
* @param pVCpu The cross context virtual CPU structure.
* @param pRegFrame Pointer to the register frame for the trap.
* @param uDr6 The DR6 hypervisor register value.
* @param fAltStepping Alternative stepping indicator.
*/
VMMRZ_INT_DECL(int) DBGFRZTrap01Handler(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCUINTREG uDr6, bool fAltStepping)
{
#ifdef IN_RC
const bool fInHyper = !(pRegFrame->ss.Sel & X86_SEL_RPL) && !pRegFrame->eflags.Bits.u1VM;
#else
NOREF(pRegFrame);
const bool fInHyper = false;
#endif
/** @todo Intel docs say that X86_DR6_BS has the highest priority... */
/*
* A breakpoint?
*/
AssertCompile(X86_DR6_B0 == 1 && X86_DR6_B1 == 2 && X86_DR6_B2 == 4 && X86_DR6_B3 == 8);
if ( (uDr6 & (X86_DR6_B0 | X86_DR6_B1 | X86_DR6_B2 | X86_DR6_B3))
&& pVM->dbgf.s.cEnabledHwBreakpoints > 0)
{
for (unsigned iBp = 0; iBp < RT_ELEMENTS(pVM->dbgf.s.aHwBreakpoints); iBp++)
{
if ( ((uint32_t)uDr6 & RT_BIT_32(iBp))
&& pVM->dbgf.s.aHwBreakpoints[iBp].enmType == DBGFBPTYPE_REG)
{
pVCpu->dbgf.s.iActiveBp = pVM->dbgf.s.aHwBreakpoints[iBp].iBp;
pVCpu->dbgf.s.fSingleSteppingRaw = false;
LogFlow(("DBGFRZTrap03Handler: hit hw breakpoint %d at %04x:%RGv\n",
pVM->dbgf.s.aHwBreakpoints[iBp].iBp, pRegFrame->cs.Sel, pRegFrame->rip));
return fInHyper ? VINF_EM_DBG_HYPER_BREAKPOINT : VINF_EM_DBG_BREAKPOINT;
}
}
}
/*
* Single step?
* Are we single stepping or is it the guest?
*/
if ( (uDr6 & X86_DR6_BS)
&& (fInHyper || pVCpu->dbgf.s.fSingleSteppingRaw || fAltStepping))
{
pVCpu->dbgf.s.fSingleSteppingRaw = false;
LogFlow(("DBGFRZTrap01Handler: single step at %04x:%RGv\n", pRegFrame->cs.Sel, pRegFrame->rip));
return fInHyper ? VINF_EM_DBG_HYPER_STEPPED : VINF_EM_DBG_STEPPED;
}
#ifdef IN_RC
/*
* Either an ICEBP in hypervisor code or a guest related debug exception
* of sorts.
*/
if (RT_UNLIKELY(fInHyper))
{
/*
* Is this a guest debug event that was delayed past a ring transition?
*
* Since we do no allow sysenter/syscall in raw-mode, the only
* non-trap/fault type transitions that can occur are thru interrupt gates.
* Of those, only INT3 (#BP) has a DPL other than 0 with a CS.RPL of 0.
* See bugref:9171 and bs3-cpu-weird-1 for more details.
*
* We need to reconstruct the guest register state from the hypervisor one
* here, so here is the layout of the IRET frame on the stack:
* 20:[8] GS (V86 only)
* 1C:[7] FS (V86 only)
* 18:[6] DS (V86 only)
* 14:[5] ES (V86 only)
* 10:[4] SS
* 0c:[3] ESP
* 08:[2] EFLAGS
* 04:[1] CS
* 00:[0] EIP
*/
if (pRegFrame->rip == (uintptr_t)TRPMRCHandlerAsmTrap03)
{
uint32_t const *pu32Stack = (uint32_t const *)pRegFrame->esp;
if ( (pu32Stack[2] & X86_EFL_VM)
|| (pu32Stack[1] & X86_SEL_RPL))
{
LogFlow(("DBGFRZTrap01Handler: Detected guest #DB delayed past ring transition %04x:%RX32 %#x\n",
pu32Stack[1] & 0xffff, pu32Stack[0], pu32Stack[2]));
PCPUMCTX pGstCtx = CPUMQueryGuestCtxPtr(pVCpu);
pGstCtx->rip = pu32Stack[0];
pGstCtx->cs.Sel = pu32Stack[1];
pGstCtx->eflags.u = pu32Stack[2];
pGstCtx->rsp = pu32Stack[3];
pGstCtx->ss.Sel = pu32Stack[4];
if (pu32Stack[2] & X86_EFL_VM)
{
pGstCtx->es.Sel = pu32Stack[5];
pGstCtx->ds.Sel = pu32Stack[6];
pGstCtx->fs.Sel = pu32Stack[7];
pGstCtx->gs.Sel = pu32Stack[8];
}
else
{
pGstCtx->es.Sel = pRegFrame->es.Sel;
pGstCtx->ds.Sel = pRegFrame->ds.Sel;
pGstCtx->fs.Sel = pRegFrame->fs.Sel;
pGstCtx->gs.Sel = pRegFrame->gs.Sel;
}
pGstCtx->rax = pRegFrame->rax;
pGstCtx->rcx = pRegFrame->rcx;
pGstCtx->rdx = pRegFrame->rdx;
pGstCtx->rbx = pRegFrame->rbx;
pGstCtx->rsi = pRegFrame->rsi;
pGstCtx->rdi = pRegFrame->rdi;
pGstCtx->rbp = pRegFrame->rbp;
/*
* We should assert a #BP followed by a #DB here, but TRPM cannot
* do that. So, we'll just assert the #BP and ignore the #DB, even
* if that isn't strictly correct.
*/
TRPMResetTrap(pVCpu);
TRPMAssertTrap(pVCpu, X86_XCPT_BP, TRPM_SOFTWARE_INT);
return VINF_EM_RAW_GUEST_TRAP;
}
}
LogFlow(("DBGFRZTrap01Handler: Unknown bp at %04x:%RGv\n", pRegFrame->cs.Sel, pRegFrame->rip));
return VERR_DBGF_HYPER_DB_XCPT;
}
#endif
LogFlow(("DBGFRZTrap01Handler: guest debug event %#x at %04x:%RGv!\n", (uint32_t)uDr6, pRegFrame->cs.Sel, pRegFrame->rip));
return VINF_EM_RAW_GUEST_TRAP;
}
void darwinMouseRelease(QWidget *pWidget)
{
UICocoaApplication::instance()->unregisterForNativeEvents(RT_BIT_32(1) | /* NSLeftMouseDown */
RT_BIT_32(2) | /* NSLeftMouseUp */
RT_BIT_32(3) | /* NSRightMouseDown */
RT_BIT_32(4) | /* NSRightMouseUp */
RT_BIT_32(5) | /* NSMouseMoved */
RT_BIT_32(6) | /* NSLeftMouseDragged */
RT_BIT_32(7) | /* NSRightMouseDragged */
RT_BIT_32(25) | /* NSOtherMouseDown */
RT_BIT_32(26) | /* NSOtherMouseUp */
RT_BIT_32(27) | /* NSOtherMouseDragged */
RT_BIT_32(22), /* NSScrollWheel */
::darwinMouseGrabEvents, pWidget);
CGAssociateMouseAndMouseCursorPosition(true);
}
void darwinSendMouseGrabEvents(QWidget *pWidget, int type, int button, int buttons, int x, int y)
{
QEvent::Type qtType = QEvent::None;
Qt::MouseButtons qtButtons = Qt::NoButton;
Qt::MouseButton qtButton = Qt::NoButton;
Qt::MouseButton qtExtraButton = Qt::NoButton;
Qt::Orientation qtOrientation = Qt::Horizontal;
int wheelDelta = 0;
/* Which button is used in the NSOtherMouse... cases? */
if (button == 0)
qtExtraButton = Qt::LeftButton;
else if (button == 1)
qtExtraButton = Qt::RightButton;
else if (button == 2)
qtExtraButton = Qt::MidButton;
else if (button == 3)
qtExtraButton = Qt::XButton1;
else if (button == 4)
qtExtraButton = Qt::XButton2;
/* Map the NSEvent to a QEvent and define the Qt::Buttons when necessary. */
switch(type)
{
case 1: /* NSLeftMouseDown */
{
qtType = QEvent::MouseButtonPress;
qtButton = Qt::LeftButton;
break;
}
case 2: /* NSLeftMouseUp */
{
qtType = QEvent::MouseButtonRelease;
qtButton = Qt::LeftButton;
break;
}
case 3: /* NSRightMouseDown */
{
qtType = QEvent::MouseButtonPress;
qtButton = Qt::RightButton;
break;
}
case 4: /* NSRightMouseUp */
{
qtType = QEvent::MouseButtonRelease;
qtButton = Qt::RightButton;
break;
}
case 5: /* NSMouseMoved */
{
qtType = QEvent::MouseMove;
break;
}
case 6: /* NSLeftMouseDragged */
{
qtType = QEvent::MouseMove;
qtButton = Qt::LeftButton;
break;
}
case 7: /* NSRightMouseDragged */
{
qtType = QEvent::MouseMove;
qtButton = Qt::RightButton;
break;
}
case 22: /* NSScrollWheel */
{
qtType = QEvent::Wheel;
if (y != 0)
{
wheelDelta = y;
qtOrientation = Qt::Vertical;
}
else if (x != 0)
{
wheelDelta = x;
qtOrientation = Qt::Horizontal;
}
x = y = 0;
break;
}
case 25: /* NSOtherMouseDown */
{
qtType = QEvent::MouseButtonPress;
qtButton = qtExtraButton;
break;
}
case 26: /* NSOtherMouseUp */
{
qtType = QEvent::MouseButtonRelease;
qtButton = qtExtraButton;
break;
}
case 27: /* NSOtherMouseDragged */
{
qtType = QEvent::MouseMove;
qtButton = qtExtraButton;
break;
}
default: return;
}
/* Create a Qt::MouseButtons Mask. */
if ((buttons & RT_BIT_32(0)) == RT_BIT_32(0))
qtButtons |= Qt::LeftButton;
if ((buttons & RT_BIT_32(1)) == RT_BIT_32(1))
qtButtons |= Qt::RightButton;
if ((buttons & RT_BIT_32(2)) == RT_BIT_32(2))
qtButtons |= Qt::MidButton;
if ((buttons & RT_BIT_32(3)) == RT_BIT_32(3))
qtButtons |= Qt::XButton1;
if ((buttons & RT_BIT_32(4)) == RT_BIT_32(4))
qtButtons |= Qt::XButton2;
/* Create a new mouse delta event and send it to the widget. */
UIGrabMouseEvent *pEvent = new UIGrabMouseEvent(qtType, qtButton, qtButtons, x, y, wheelDelta, qtOrientation);
qApp->sendEvent(pWidget, pEvent);
}
uint16_t n_sect = bios_dsk->drqp.nsect;
uint16_t sectsz = bios_dsk->drqp.sect_sz;
uint16_t prdt_idx;
_fmemset(&ahci->abCmd[0], 0, sizeof(ahci->abCmd));
/* Prepare the FIS. */
ahci->abCmd[0] = 0x27; /* FIS type H2D. */
ahci->abCmd[1] = 1 << 7; /* Command update. */
ahci->abCmd[2] = cmd;
ahci->abCmd[3] = 0;
ahci->abCmd[4] = bios_dsk->drqp.lba & 0xff;
ahci->abCmd[5] = (bios_dsk->drqp.lba >> 8) & 0xff;
ahci->abCmd[6] = (bios_dsk->drqp.lba >> 16) & 0xff;
ahci->abCmd[7] = RT_BIT_32(6); /* LBA access. */
ahci->abCmd[8] = (bios_dsk->drqp.lba >> 24) & 0xff;
ahci->abCmd[9] = 0;
ahci->abCmd[10] = 0;
ahci->abCmd[11] = 0;
ahci->abCmd[12] = (uint8_t)(n_sect & 0xff);
ahci->abCmd[13] = (uint8_t)((n_sect >> 8) & 0xff);
/* Lock memory needed for DMA. */
ahci->edds.num_avail = NUM_EDDS_SG;
DBG_AHCI("AHCI: S/G list for %lu bytes (skip %u)\n",
(uint32_t)n_sect * sectsz, bios_dsk->drqp.skip_a);
vds_build_sg_list(&ahci->edds, bios_dsk->drqp.buffer, (uint32_t)n_sect * sectsz);
RTDECL(bool) ASMBitTest(const volatile void *pvBitmap, int32_t iBit)
{
uint32_t volatile *pau32Bitmap = (uint32_t volatile *)pvBitmap;
return pau32Bitmap[iBit / 32] & RT_BIT_32(iBit & 31) ? true : false;
}
RTDECL(bool) ASMBitTest(const volatile void *pvBitmap, int32_t iBit)
{
uint8_t volatile *pau8Bitmap = (uint8_t volatile *)pvBitmap;
return pau8Bitmap[iBit / 8] & (uint8_t)RT_BIT_32(iBit & 7) ? true : false;
}
RTDECL(void) ASMBitToggle(volatile void *pvBitmap, int32_t iBit)
{
uint8_t volatile *pau8Bitmap = (uint8_t volatile *)pvBitmap;
pau8Bitmap[iBit / 8] ^= (uint8_t)RT_BIT_32(iBit & 7);
}
RTDECL(void) ASMBitToggle(volatile void *pvBitmap, int32_t iBit)
{
uint32_t volatile *pau32Bitmap = (uint32_t volatile *)pvBitmap;
pau32Bitmap[iBit / 32] ^= RT_BIT_32(iBit & 31);
}