static int setup_processor() { CleanAndInvalidateCPUDataCache(); ClearCPUInstructionCache(); WriteControlRegisterConfigData(ReadControlRegisterConfigData() & ~(ARM11_Control_INSTRUCTIONCACHE)); // Disable instruction cache WriteControlRegisterConfigData(ReadControlRegisterConfigData() & ~(ARM11_Control_DATACACHE)); // Disable data cache GiveFullAccessCP10CP11(); EnableVFP(); // Map the peripheral port of size 128 MB to 0x38000000 WritePeripheralPortMemoryRemapRegister(PeripheralPort | ARM11_PeripheralPortSize128MB); InvalidateCPUDataCache(); ClearCPUInstructionCache(); WriteControlRegisterConfigData(ReadControlRegisterConfigData() | ARM11_Control_INSTRUCTIONCACHE); // Enable instruction cache WriteControlRegisterConfigData(ReadControlRegisterConfigData() | ARM11_Control_DATACACHE); // Enable data cache WriteControlRegisterConfigData((ReadControlRegisterConfigData() & ~(ARM11_Control_STRICTALIGNMENTCHECKING)) // Disable strict alignment fault checking | ARM11_Control_UNALIGNEDDATAACCESS); // Enable unaligned data access operations WriteControlRegisterConfigData(ReadControlRegisterConfigData() | ARM11_Control_BRANCHPREDICTION); // Enable branch prediction // Enable return stack, dynamic branch prediction, static branch prediction WriteAuxiliaryControlRegister(ReadAuxiliaryControlRegister() | ARM11_AuxControl_RETURNSTACK | ARM11_AuxControl_DYNAMICBRANCHPREDICTION | ARM11_AuxControl_STATICBRANCHPREDICTION); return 0; }
void mmu_disable() { WriteControlRegisterConfigData(ReadControlRegisterConfigData() & ~0x4); WriteControlRegisterConfigData(ReadControlRegisterConfigData() & ~0x1); }
void mmu_enable() { WriteControlRegisterConfigData(ReadControlRegisterConfigData() | 0x1); }
void arm_disable_caches() { CleanAndInvalidateCPUDataCache(); ClearCPUInstructionCache(); WriteControlRegisterConfigData(ReadControlRegisterConfigData() & ~ARM11_Control_INSTRUCTIONCACHE); // Disable instruction cache WriteControlRegisterConfigData(ReadControlRegisterConfigData() & ~ARM11_Control_DATACACHE); // Disable data cache }