int32_t PpeGetAGCnt(struct hwnat_ac_args * opt3)
{
opt3->ag_pkt_cnt = RegRead(AC_BASE + opt3->ag_index * 8); /* Low bytes */
opt3->ag_byte_cnt = RegRead(AC_BASE + opt3->ag_index * 8 + 4); /* High bytes */
return HWNAT_SUCCESS;
}
int PpeGetAGCnt(struct hwnat_ac_args * opt3)
{
#if defined (CONFIG_RALINK_MT7620)
opt3->ag_byte_cnt = RegRead(AC_BASE + opt3->ag_index * 8); /* Low bytes */
opt3->ag_pkt_cnt = RegRead(AC_BASE + opt3->ag_index * 8 + 4); /* High bytes */
#elif defined (CONFIG_RALINK_MT7621)
opt3->ag_byte_cnt = RegRead(AC_BASE + opt3->ag_index * 16); /* 64bit bytes cnt */
opt3->ag_byte_cnt |= ((unsigned long long)(RegRead(AC_BASE + opt3->ag_index * 16 + 4)) << 32);
opt3->ag_pkt_cnt = RegRead(AC_BASE + opt3->ag_index * 16 + 8); /* 32bites packet cnt */
#endif
return HWNAT_SUCCESS;
}
int PpeSetAllowIPv6(uint8_t allow_ipv6)
{
#if defined (CONFIG_RA_HW_NAT_IPV6)
uint32_t PpeFlowSet = RegRead(PPE_FLOW_SET);
if (allow_ipv6) {
ipv6_offload = 1;
#if defined (CONFIG_HNAT_V2)
PpeFlowSet |= (BIT_IPV4_DSL_EN | BIT_IPV6_6RD_EN | BIT_IPV6_3T_ROUTE_EN | BIT_IPV6_5T_ROUTE_EN);
// PpeFlowSet |= (BIT_IPV6_HASH_FLAB); // flow label
PpeFlowSet |= (BIT_IPV6_HASH_GREK);
#else
PpeFlowSet |= (BIT_IPV6_FOE_EN);
#endif
} else {
ipv6_offload = 0;
#if defined (CONFIG_HNAT_V2)
PpeFlowSet &= ~(BIT_IPV4_DSL_EN | BIT_IPV6_6RD_EN | BIT_IPV6_3T_ROUTE_EN | BIT_IPV6_5T_ROUTE_EN);
PpeFlowSet &= ~(BIT_IPV6_HASH_FLAB);
PpeFlowSet &= ~(BIT_IPV6_HASH_GREK);
#else
PpeFlowSet &= ~(BIT_IPV6_FOE_EN);
#endif
}
RegWrite(PPE_FLOW_SET, PpeFlowSet);
return HWNAT_SUCCESS;
#else
return HWNAT_FAIL;
#endif
}
/******************************************************************************
*
* ae531x_ReadDmaReg - read AE DMA register
*
* RETURNS: register value
*/
UINT32
ae531x_ReadDmaReg(ae531x_MAC_t *MACInfo, UINT32 reg)
{
UINT32 addr = MACInfo->dmaBase+reg;
UINT32 data = RegRead(addr);
return data;
}
/******************************************************************************
*
* ae531x_ReadMacReg - read AE MAC register
*
* RETURNS: register value
*/
UINT32
ae531x_ReadMacReg(ae531x_MAC_t *MACInfo, UINT32 reg)
{
UINT32 addr = MACInfo->macBase+reg;
UINT32 data;
data = RegRead(addr);
return data;
}
/******************************************************************************
*
* ae531x_ReadMiiReg - read PHY registers via AE MAC Mii addr/data registers
*
* RETURNS: register value
*/
UINT32
ae531x_ReadMiiReg(UINT32 phyBase, UINT32 reg)
{
UINT32 data;
UINT32 addr = phyBase+reg;
data = RegRead(addr);
return data;
}
/******************************************************************************
*
* ae531x_ClearDmaReg - clear bits in an AE DMA register
*
* RETURNS: N/A
*/
void
ae531x_ClearDmaReg(ae531x_MAC_t *MACInfo, UINT32 reg, UINT32 val)
{
UINT32 addr = MACInfo->dmaBase+reg;
UINT32 data = RegRead(addr);
data &= ~val;
RegWrite(data, addr);
}
/******************************************************************************
*
* ae531x_SetMacReg - set bits in AE MAC register
*
* RETURNS: N/A
*/
void
ae531x_SetMacReg(ae531x_MAC_t *MACInfo, UINT32 reg, UINT32 val)
{
UINT32 addr = MACInfo->macBase+reg;
UINT32 data = RegRead(addr);
data |= val;
RegWrite(data, addr);
}
int FoeUnBindEntry(struct hwnat_args *opt)
{
struct FoeEntry *entry;
entry = &PpeFoeBase[opt->entry_num];
entry->ipv4_hnapt.udib1.state = UNBIND;
entry->ipv4_hnapt.udib1.time_stamp = RegRead(FOE_TS) & 0xFF;
return HWNAT_SUCCESS;
}
int FoeBindEntry(struct hwnat_args *opt)
{
struct FoeEntry *entry;
entry = &PpeFoeBase[opt->entry_num];
//restore right information block1
entry->bfib1.time_stamp = RegRead(FOE_TS) & 0xFFFF;
entry->bfib1.state = BIND;
return HWNAT_SUCCESS;
}
int fpga_reset_test( int fd_mem, void *mapped_base_slcr )
{
static unsigned int u32_call_num=0;
volatile unsigned int u32_loop=0;
volatile unsigned int u32_int_type;
volatile unsigned int u32_rst_num_raw;
volatile unsigned int u32_rst_num_overflow=0;
volatile unsigned int u32_rst_num;
//volatile unsigned int *p_gpio_emio_input = (unsigned int *)0xe000a068;
//volatile unsigned int *p_fpga_reset_output = (unsigned int *)0xF8000240;
void *mapped_base_gpio;
u32_call_num++;
printf("%s runs No.%d time\n\r", __func__, u32_call_num );
/* Map GPIO register space into user space */
mapped_base_gpio = mmap(0, SIZE_GPIO, PROT_READ | PROT_WRITE,
MAP_SHARED, fd_mem, BASE_ADDR_GPIO & ~MAP_MASK);
if (mapped_base_gpio == (void *) -1)
{
printf("Can't map GPIO registers to user space.\n");
return -200;
}
printf("Mapped GPIO at virtual address %p.\n", mapped_base_gpio);
u32_int_type = RegRead(mapped_base_gpio, OFFSET_GPIO_INT_TYPE2);
if( 0xffffffff != u32_int_type )
{
printf("u32_int_type 2:0x%08x,GPIO access has problem.\n\r",
u32_int_type );
/* SLCR unlock */
RegWrite(mapped_base_slcr, OFFSET_SLCR_UNLOCK, SLCR_UNLOCK_VAL );
// Caution:
// Set GPIO clock.
RegWrite(mapped_base_slcr, 0x12c, 0x00e44405 );
/* SLCR lock */
RegWrite(mapped_base_slcr, OFFSET_SLCR_LOCK, SLCR_LOCK_VAL );
}
else
{
printf("u32_int_type 2:0x%08x,GPIO access works well.\n\r",
u32_int_type );
}
u32_int_type = RegRead(mapped_base_gpio, OFFSET_GPIO_INT_TYPE3);
if( 0xffffffff != u32_int_type )
{
printf("u32_int_type 3:0x%08x,GPIO access has problem.\n\r",
u32_int_type );
/* SLCR unlock */
RegWrite(mapped_base_slcr, OFFSET_SLCR_UNLOCK, SLCR_UNLOCK_VAL );
// Caution:
// Set GPIO clock.
RegWrite(mapped_base_slcr, 0x12c, 0x00e44405 );
/* SLCR lock */
RegWrite(mapped_base_slcr, OFFSET_SLCR_LOCK, SLCR_LOCK_VAL );
}
else
{
printf("u32_int_type 3:0x%08x,GPIO access works well.\n\r",
u32_int_type );
}
/* SLCR unlock */
RegWrite(mapped_base_slcr, OFFSET_SLCR_UNLOCK, SLCR_UNLOCK_VAL );
//for( u32_loop =0; u32_loop<10000000; u32_loop++ )
//for( u32_loop =0; u32_loop<1000; u32_loop++ )
{
// 0xF8000240
RegWrite(mapped_base_slcr, OFFSET_SLCR_FPGA_RESET, 0x0 );
usleep(1);
RegWrite(mapped_base_slcr, OFFSET_SLCR_FPGA_RESET, 0xf );
usleep(1);
RegWrite(mapped_base_slcr, OFFSET_SLCR_FPGA_RESET, 0x0 );
usleep(1);
u32_rst_num_raw = RegRead(mapped_base_gpio, OFFSET_GPIO_INPUT3);
u32_rst_num = (u32_rst_num_raw&0xffff0000)>>16;
if( 0 == (u32_loop%10000) )
{
printf("Reset num raw:0x%08x, reset num:%d-%d at No.%d loop.\n\r",
u32_rst_num_raw, u32_rst_num, u32_rst_num_overflow*0x10000+u32_rst_num, u32_loop );
}
if( u32_rst_num >=65535 )
{
printf("Reset num raw:0x%08x, reset num:%d-%d at No.%d loop.\n\r",
u32_rst_num_raw, u32_rst_num, u32_rst_num_overflow*0x10000+u32_rst_num, u32_loop );
u32_rst_num_overflow++;
}
}
printf("Reset num raw:0x%08x, reset num:%d-%d at No.%d loop.\n\r",
u32_rst_num_raw, u32_rst_num, u32_rst_num_overflow*0x10000+u32_rst_num, u32_loop );
/* SLCR lock */
RegWrite(mapped_base_slcr, OFFSET_SLCR_LOCK, SLCR_LOCK_VAL );
if (munmap(mapped_base_gpio, SIZE_GPIO) == -1) {
printf("Can't unmap GPIO from user space.\n");
return -200;
}
return 0;
}
int __fastcall _clio_Poke(unsigned int addr, unsigned int val)
{
int base;
int i;
//if(addr==0x200 || addr==0x204 || addr==0x208 || addr==0x20c || (addr>=0x100 && addr<=0x17c) || addr==0x220)io_interface(EXT_DEBUG_PRINT,(void*)str.print("CLIO Write[0x%X] = 0x%8.8X",addr,val).CStr());
//if(addr==0x34 || addr==0x30)io_interface(EXT_DEBUG_PRINT,(void*)str.print("CLIO Write[0x%X] = 0x%8.8X",addr,val).CStr());
if( (addr& ~0x2C) == 0x40 ) // 0x40..0x4C, 0x60..0x6C case
{
if(addr==0x40)
{
cregs[0x40]|=val;
if(cregs[0x60]) cregs[0x40]|=0x80000000;
//if(cregs[0x40]&cregs[0x48]) _arm_SetFIQ();
return 0;
}
else if(addr==0x44)
{
cregs[0x40]&=~val;
if(!cregs[0x60]) cregs[0x40]&=~0x80000000;
return 0;
}
else if(addr==0x48)
{
cregs[0x48]|=val;
//if(cregs[0x40]&cregs[0x48]) _arm_SetFIQ();
return 0;
}
else if(addr==0x4c)
{
cregs[0x48]&=~val;
cregs[0x48]|=0x80000000; // always one for irq31
return 0;
}
/*else if(addr==0x50)
{
cregs[0x50]|=val&0x3fff0000;
return 0;
}
else if(addr==0x54)
{
cregs[0x50]&=~val;
return 0;
} */
else if(addr==0x60)
{
cregs[0x60]|=val;
if(cregs[0x60]) cregs[0x40]|=0x80000000;
//if(cregs[0x60]&cregs[0x68]) _arm_SetFIQ();
return 0;
}
else if(addr==0x64)
{
cregs[0x60]&=~val;
if(!cregs[0x60]) cregs[0x40]&=~0x80000000;
return 0;
}
else if(addr==0x68)
{
cregs[0x68]|=val;
//if(cregs[0x60]&cregs[0x68]) _arm_SetFIQ();
return 0;
}
else if(addr==0x6c)
{
cregs[0x68]&=~val;
return 0;
}
}
else if(addr==0x84)
{
//temp=val&0xf0;
//temp=temp>>4;
//val&=0x0f;
//cregs[0x84]&=~temp;
//cregs[0x84]|=val;
cregs[0x84]=val&0xf;
SelectROM((val&4)? 1:0 );
return 0;
}else if(addr==0x300)
{ //clear down the fifos and stop them
base=0;
cregs[0x304]&=~val;
for(i=0;i<13;i++)
{
if(val&(1<<i))
{
base=0x400+(i<<4);
RLDADR=CURADR=0;
RLDLEN=CURLEN=0;
_clio_SetFIFO(base,0);
_clio_SetFIFO(base+4,0);
_clio_SetFIFO(base+8,0);
_clio_SetFIFO(base+0xc,0);
val&=~(1<<i);
PTRI[i]=0;
}
}
{
for(i=0;i<4;i++)
{
if(val&(1<<(i+16)))
{
base=0x500+(i<<4);
RLDADR=CURADR=0;
RLDLEN=CURLEN=0;
_clio_SetFIFO(base,0);
_clio_SetFIFO(base+4,0);
_clio_SetFIFO(base+8,0);
_clio_SetFIFO(base+0xc,0);
val&=~(1<<(i+16));
PTRO[i]=0;
}
}
}
return 0;
}
else if(addr==0x304) // Dma Starter!!!!! P/A !!!! need to create Handler.
{
//if(val&0x00100000)
//{
HandleDMA(val);
// cregs[0x304]&=~0x00100000;
//}
return 0;
}
else if(addr==0x308) //Dma Stopper!!!!
{
cregs[0x304]&=~val;
return 0;
}
else if(addr==0x400) //XBUS direction
{
if(val&0x800)
return 0;
else
{
cregs[0x400]=val;
return 0;
}
}
else if((addr>=0x500) && (addr<0x540))
{
_xbus_SetSEL(val);
return 0;
}
else if((addr>=0x540) && (addr<0x580))
{
#ifdef DBGXBUS
sprintf(str,"XBPC : 0x%8.8x :",RegRead(15));
CDebug::DPrint(str);
#endif
_xbus_SetPoll(val);
return 0;
}
else if((addr>=0x580) && (addr<0x5c0))
{
_xbus_SetCommandFIFO(val); // on FIFO Filled execute the command
return 0;
}
else if((addr>=0x5c0) && (addr<0x600))
{
_xbus_SetDataFIFO(val); // on FIFO Filled execute the command
return 0;
}
else if(addr==0x28)
{
cregs[addr]=val;
if(val==0x30)
return 1;
else
return 0;
}else if((addr>=0x1800)&&(addr<=0x1fff))//0x0340 1800 … 0x0340 1BFF && 0x0340 1C00 … 0x0340 1FFF
{
addr&=~0x400; //mirrors
DSPW1=val>>16;
DSPW2=val&0xffff;
DSPA=(addr-0x1800)>>1;
//sprintf(str,"0x%8.8X : 2x1NWRITE 0x%3.3X 0x%4.4X\n",GetPC(),DSPA,DSPW1);
//CDebug::DPrint(str);
//sprintf(str,"0x%8.8X : 2x2NWRITE 0x%3.3X 0x%4.4X\n",GetPC(),DSPA+1,DSPW2);
//CDebug::DPrint(str);
_dsp_WriteMemory(DSPA,DSPW1);
_dsp_WriteMemory(DSPA+1,DSPW2);
return 0;
//DSPNRAMWrite 2 DSPW per 1ARMW
}else if((addr>=0x2000)&&(addr<=0x2fff))
static void ExecuteCmd(const char const *input, const u32 base)
{
SendStr("\r\n", base);
// Tokenize the command
#define MAX_CMD_WORDS 4
char *token[MAX_CMD_WORDS];
char *cmd = (char *)input;
u8 numTokens = 0;
while (1)
{
// Skip leading whitespace.
while ((*cmd) && isspace(*cmd))
cmd++;
// If we get here and we are at the end of the string, then the last
// token must have had trailing white spaces. Let's ignore them
if (!(*cmd))
break;
// If we have exceeded the maximum number of allowable tokens, then
// return as error
if (numTokens >= MAX_CMD_WORDS)
{
SendStr(NO_ANSWER, base);
return;
}
// Store the token.
token[numTokens] = cmd;
numTokens++;
// Everything that isn't a whitespace is part of the token. Let's make
// sure it is in UPPER CASE
while ((*cmd) && (!isspace(*cmd)))
{
*cmd = toupper(*cmd);
cmd++;
}
// When we get here, we are just past the current token, either because
// it ended on a whitespace or because it is the end of the user input.
// If the former, then let's force a null termination for that token. If
// the latter, then we are done tokenizing.
if (!(*cmd))
break;
*cmd = '\0';
cmd++;
}
if (0 == numTokens)
{
SendStr(NO_ANSWER, base);
return;
}
// Process the command
switch (token[0][0])
{
case 'R':
{
if (2 != numTokens)
SendStr(NO_ANSWER, base);
else
{
u32 regAddr;
u32 regValue;
if (StrToU32(token[1], ®Addr) && RegRead(regAddr, ®Value))
{
SendStr("Y ", base);
char regValStr[9];
U32ToStr(regValue, regValStr);
SendStr(regValStr, base);
SendStr("\r\n", base);
}
else
SendStr(NO_ANSWER, base);
}
break;
}
case 'W':
{
if (3 != numTokens)
SendStr(NO_ANSWER, base);
else
{
u32 regAddr;
u32 regValue;
if (StrToU32(token[1], ®Addr) && StrToU32(token[2], ®Value) && RegWrite(regAddr, regValue))
SendStr(YES_ANSWER, base);
else
SendStr(NO_ANSWER, base);
}
break;
}
case 'V':
{
SendStr("FPGA=0x", base);
char versionStr[9];
FpgaRegisters * FPGARegs = (FpgaRegisters *)(REGISTER_BASE | BYPASS_DCACHE_MASK);
U32ToStr(FPGARegs->fpgaVersion, versionStr);
SendStr(versionStr, base);
SendStr(" NIOS=0x", base);
U32ToStr(NIOS_VERSION, versionStr);
SendStr(versionStr, base);
SendStr("\r\n", base);
break;
}
case 'F':
{
if (4 != numTokens)
SendStr(NO_ANSWER, base);
else
{
u32 startAddr;
u32 length;
u32 checksum;
StrToU32(token[1], &startAddr);
StrToU32(token[2], &length);
StrToU32(token[3], &checksum);
// Transfer two chunks to get a full sector worth
#define FLASH_SECTOR_SIZE (64*1024)
#define TRANSFER_SIZE (4*1024)
u8 buffer[FLASH_SECTOR_SIZE];
// Validate the requested transfer size
if (length != TRANSFER_SIZE)
SendStr(NO_ANSWER, base);
else
{
u32 bufferIndex = startAddr % FLASH_SECTOR_SIZE;
u32 runningSum = 0;
u32 numBytesReceived = 0;
// Clear the input buffer
FlushRx(base);
// Acknowledge that the command is good. This will tell the
// sender to actually send the specified number of bytes
SendStr(YES_ANSWER, base);
// We must receive the correct number of bytes
while (true)
{
while (IORD_FIFOED_AVALON_UART_STATUS(base) & FIFOED_AVALON_UART_CONTROL_RRDY_MSK)
{
// Read the Uart
u8 rx = IORD_FIFOED_AVALON_UART_RXDATA(base);
runningSum += rx;
buffer[bufferIndex++] = rx;
numBytesReceived++;
if (numBytesReceived >= length)
break;
}
if (numBytesReceived >= length)
break;
}
// check the checksum
if (runningSum != checksum)
SendStr(NO_ANSWER, base);
else
{
// If we don't have a full sector worth of data, then ACK and wait for more
if (bufferIndex != FLASH_SECTOR_SIZE)
SendStr(YES_ANSWER, base);
else
{
u32 totalWriteBufferChecksum = 0;
int i;
for (i=0; i<sizeof(buffer); i++)
{
totalWriteBufferChecksum += buffer[i];
}
alt_flash_fd* fd = alt_flash_open_dev(SERIAL_FLASH_NAME);
if (NULL == fd)
SendStr(NO_ANSWER, base);
else
{
u32 sectorStartAddr = (startAddr / FLASH_SECTOR_SIZE) * FLASH_SECTOR_SIZE;
if (0 == alt_write_flash(fd, sectorStartAddr, buffer, length))
{
memset(buffer, 0x99, sizeof(buffer));
if (0 == alt_read_flash(fd, sectorStartAddr, buffer, sizeof(buffer)))
{
u32 totalReadBufferChecksum = 0;
for (i=0; i<sizeof(buffer); i++)
{
totalReadBufferChecksum += buffer[i];
}
if (totalReadBufferChecksum == totalWriteBufferChecksum)
SendStr(YES_ANSWER, base);
else
SendStr(NO_ANSWER, base);
}
else
SendStr(NO_ANSWER, base);
}
else
SendStr(NO_ANSWER, base);
alt_flash_close_dev(fd);
}
}
}
}
}
break;
}
default:
SendStr(NO_ANSWER, base);
break;
}
return;
}