void s5p6450_setup_mshci_cfg_gpio(struct platform_device *dev, int width)
{
unsigned int gpio;
/* Set all the necessary GPG[7:8] pins to special-function 2 */
for (gpio = S5P6450_GPG(7); gpio < S5P6450_GPG(9); gpio++) {
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
}
switch(width) {
case 8:
/* Data pin GPQ[6:9] to special-function 3 */
for (gpio = S5P6450_GPQ(6); gpio <= S5P6450_GPQ(9); gpio++) {
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
}
case 4:
/* Data pin GPG[9:12] to special-function 2 */
for (gpio = S5P6450_GPG(9); gpio <= S5P6450_GPG(12); gpio++) {
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
}
}
/* GPG[13] special-funtion 2 : MMC3 CDn */
s3c_gpio_cfgpin(S5P6450_GPG(13), S3C_GPIO_SFN(2));
s3c_gpio_setpull(S5P6450_GPG(13), S3C_GPIO_PULL_UP);
}
void s3c_fimc0_cfg_gpio(struct platform_device *pdev)
{
int i = 0;
/* CAM A port(b0010) : PCLK, VSYNC, HREF, DATA[0-4] */
for (i=0; i < 14; i++) {
s3c_gpio_cfgpin(S5P6450_GPQ(i), S3C_GPIO_SFN(2));
s3c_gpio_setpull(S5P6450_GPQ(i), S3C_GPIO_PULL_NONE);
}
/* note : driver strength to max is unnecessary */
}
.ngpio = S5P6450_GPIO_N_NR,
.label = "GPN",
},
}, {
.base = S5P64X0_GPP_BASE,
.config = &s5p64x0_gpio_cfgs[5],
.chip = {
.base = S5P6450_GPP(0),
.ngpio = S5P6450_GPIO_P_NR,
.label = "GPP",
},
}, {
.base = S5P6450_GPQ_BASE,
.config = &s5p64x0_gpio_cfgs[4],
.chip = {
.base = S5P6450_GPQ(0),
.ngpio = S5P6450_GPIO_Q_NR,
.label = "GPQ",
},
}, {
.base = S5P6450_GPS_BASE,
.config = &s5p64x0_gpio_cfgs[5],
.chip = {
.base = S5P6450_GPS(0),
.ngpio = S5P6450_GPIO_S_NR,
.label = "GPS",
},
},
};
void __init s5p64x0_gpiolib_set_cfg(struct s3c_gpio_cfg *chipcfg, int nr_chips)
