static int gpio_configure(void) { int ret; printk("%s()\n", __func__); ret = gpio_request(S5PC1XX_GPH1(1), "GPH1"); if (ret) { printk("%s: gpio(GPH1(2) request error: %d\n", __func__, ret); } else { s3c_gpio_cfgpin(S5PC1XX_GPH1(1), S5PC1XX_GPH1_2_WAKEUP_INT_10); s3c_gpio_setpull(S5PC1XX_GPH1(1), S3C_GPIO_PULL_NONE); } ret = gpio_request(S5PC1XX_GPH3(7), "GPH3"); if (ret) { printk("%s: gpio(GPH3(7) request error: %d\n", __func__, ret); } else { s3c_gpio_cfgpin(S5PC1XX_GPH3(7), S5PC1XX_GPH3_7_WAKEUP_INT_31); s3c_gpio_setpull(S5PC1XX_GPH3(7), S3C_GPIO_PULL_NONE); } ret = gpio_request(S5PC1XX_GPG1(0), "GPG1"); if (ret) { printk("%s: gpio(GPG1(0) request error: %d\n", __func__, ret); } else { s3c_gpio_cfgpin(S5PC1XX_GPG1(0), S5PC1XX_GPG1_0_GPIO_INT12_0); s3c_gpio_setpull(S5PC1XX_GPG1(0), S3C_GPIO_PULL_NONE); } ret = gpio_request(S5PC1XX_GPA1(1), "GPA1"); if (ret) { printk("%s: gpio(GPA1(1) request error: %d\n", __func__, ret); } else { s3c_gpio_cfgpin(S5PC1XX_GPA1(1), S5PC1XX_GPA1_1_GPIO_INT1_1); s3c_gpio_setpull(S5PC1XX_GPA1(1), S3C_GPIO_PULL_NONE); } ret = gpio_request(S5PC1XX_GPA1(0), "GPA1"); if (ret) { printk("%s: gpio(GPA1(0) request error: %d\n", __func__, ret); } else { s3c_gpio_cfgpin(S5PC1XX_GPA1(0), S5PC1XX_GPA1_0_GPIO_INT1_0); s3c_gpio_setpull(S5PC1XX_GPA1(0), S3C_GPIO_PULL_NONE); } ret = gpio_request(S5PC1XX_GPB(0), "GPB0"); if (ret) { printk("%s: gpio(GPB0(0) request error: %d\n", __func__, ret); } else { s3c_gpio_cfgpin(S5PC1XX_GPB(0), S5PC1XX_GPB0_GPIO_INT2_0); s3c_gpio_setpull(S5PC1XX_GPB(0), S3C_GPIO_PULL_NONE); } return 0; }
static void camera_cfg_gpio(struct platform_device *pdev) { int i; s3c_gpio_cfgpin(CAM_EN, S3C_GPIO_OUTPUT); s3c_gpio_cfgpin(CAM1_3M_EN, S3C_GPIO_OUTPUT); s3c_gpio_cfgpin(VGA_CAM_nSTBY, S3C_GPIO_OUTPUT); s3c_gpio_cfgpin(VGA_CAM_nRST, S3C_GPIO_OUTPUT); /* Following pins are C100 dedicated */ s3c_gpio_cfgpin(S5PC1XX_GPE0(0), S5PC1XX_GPE0_0_CAM_A_PCLK); s3c_gpio_cfgpin(S5PC1XX_GPE0(1), S5PC1XX_GPE0_1_CAM_A_VSYNC); s3c_gpio_cfgpin(S5PC1XX_GPE0(2), S5PC1XX_GPE0_2_CAM_A_HREF); s3c_gpio_cfgpin(S5PC1XX_GPE0(3), S5PC1XX_GPE0_3_CAM_A_DATA_0); s3c_gpio_cfgpin(S5PC1XX_GPE0(4), S5PC1XX_GPE0_4_CAM_A_DATA_1); s3c_gpio_cfgpin(S5PC1XX_GPE0(5), S5PC1XX_GPE0_5_CAM_A_DATA_2); s3c_gpio_cfgpin(S5PC1XX_GPE0(6), S5PC1XX_GPE0_6_CAM_A_DATA_3); s3c_gpio_cfgpin(S5PC1XX_GPE0(7), S5PC1XX_GPE0_7_CAM_A_DATA_4); s3c_gpio_cfgpin(S5PC1XX_GPE1(0), S5PC1XX_GPE1_0_CAM_A_DATA_5); s3c_gpio_cfgpin(S5PC1XX_GPE1(1), S5PC1XX_GPE1_1_CAM_A_DATA_6); s3c_gpio_cfgpin(S5PC1XX_GPE1(2), S5PC1XX_GPE1_2_CAM_A_DATA_7); s3c_gpio_cfgpin(S5PC1XX_GPE1(3), S5PC1XX_GPE1_3_CAM_A_CLKOUT); s3c_gpio_cfgpin(S5PC1XX_GPE1(4), S5PC1XX_GPE1_4_CAM_A_RESET); s3c_gpio_cfgpin(S5PC1XX_GPE1(5), S5PC1XX_GPE1_5_CAM_A_FIELD); for (i = 0; i < 8; i++) s3c_gpio_setpull(S5PC1XX_GPE0(i), S3C_GPIO_PULL_UP); for (i = 0; i < 6; i++) s3c_gpio_setpull(S5PC1XX_GPE1(i), S3C_GPIO_PULL_UP); s3c_gpio_cfgpin(S5PC1XX_GPH2(0), S5PC1XX_GPH2_0_CAM_B_DATA_0); s3c_gpio_cfgpin(S5PC1XX_GPH2(1), S5PC1XX_GPH2_1_CAM_B_DATA_1); s3c_gpio_cfgpin(S5PC1XX_GPH2(2), S5PC1XX_GPH2_2_CAM_B_DATA_2); s3c_gpio_cfgpin(S5PC1XX_GPH2(3), S5PC1XX_GPH2_3_CAM_B_DATA_3); s3c_gpio_cfgpin(S5PC1XX_GPH2(4), S5PC1XX_GPH2_4_CAM_B_DATA_4); s3c_gpio_cfgpin(S5PC1XX_GPH2(5), S5PC1XX_GPH2_5_CAM_B_DATA_5); s3c_gpio_cfgpin(S5PC1XX_GPH2(6), S5PC1XX_GPH2_6_CAM_B_DATA_6); s3c_gpio_cfgpin(S5PC1XX_GPH2(7), S5PC1XX_GPH2_7_CAM_B_DATA_7); s3c_gpio_cfgpin(S5PC1XX_GPH3(0), S5PC1XX_GPH3_0_CAM_B_PCLK); s3c_gpio_cfgpin(S5PC1XX_GPH3(1), S5PC1XX_GPH3_1_CAM_B_VSYNC); s3c_gpio_cfgpin(S5PC1XX_GPH3(2), S5PC1XX_GPH3_2_CAM_B_HREF); s3c_gpio_cfgpin(S5PC1XX_GPH3(3), S5PC1XX_GPH3_3_CAM_B_FIELD); s3c_gpio_cfgpin(S5PC1XX_GPE1(3), S5PC1XX_GPE1_3_CAM_A_CLKOUT); for (i = 0; i < 8; i++) s3c_gpio_setpull(S5PC1XX_GPH2(i), S3C_GPIO_PULL_UP); for (i = 0; i < 4; i++) s3c_gpio_setpull(S5PC1XX_GPH3(i), S3C_GPIO_PULL_UP); }
void s3c_fimc0_cfg_gpio(struct platform_device *dev) { int i; s3c_gpio_cfgpin(S5PC1XX_GPE0(0), S5PC1XX_GPE0_0_CAM_A_PCLK); s3c_gpio_cfgpin(S5PC1XX_GPE0(1), S5PC1XX_GPE0_1_CAM_A_VSYNC); s3c_gpio_cfgpin(S5PC1XX_GPE0(2), S5PC1XX_GPE0_2_CAM_A_HREF); s3c_gpio_cfgpin(S5PC1XX_GPE0(3), S5PC1XX_GPE0_3_CAM_A_DATA_0); s3c_gpio_cfgpin(S5PC1XX_GPE0(4), S5PC1XX_GPE0_4_CAM_A_DATA_1); s3c_gpio_cfgpin(S5PC1XX_GPE0(5), S5PC1XX_GPE0_5_CAM_A_DATA_2); s3c_gpio_cfgpin(S5PC1XX_GPE0(6), S5PC1XX_GPE0_6_CAM_A_DATA_3); s3c_gpio_cfgpin(S5PC1XX_GPE0(7), S5PC1XX_GPE0_7_CAM_A_DATA_4); s3c_gpio_cfgpin(S5PC1XX_GPE1(0), S5PC1XX_GPE1_0_CAM_A_DATA_5); s3c_gpio_cfgpin(S5PC1XX_GPE1(1), S5PC1XX_GPE1_1_CAM_A_DATA_6); s3c_gpio_cfgpin(S5PC1XX_GPE1(2), S5PC1XX_GPE1_2_CAM_A_DATA_7); s3c_gpio_cfgpin(S5PC1XX_GPE1(3), S5PC1XX_GPE1_3_CAM_A_CLKOUT); s3c_gpio_cfgpin(S5PC1XX_GPE1(4), S5PC1XX_GPE1_4_CAM_A_RESET); s3c_gpio_cfgpin(S5PC1XX_GPE1(5), S5PC1XX_GPE1_5_CAM_A_FIELD); for (i = 0; i < 8; i++) s3c_gpio_setpull(S5PC1XX_GPE0(i), S3C_GPIO_PULL_UP); for (i = 0; i < 6; i++) s3c_gpio_setpull(S5PC1XX_GPE1(i), S3C_GPIO_PULL_UP); s3c_gpio_cfgpin(S5PC1XX_GPH2(0), S5PC1XX_GPH2_0_CAM_B_DATA_0); s3c_gpio_cfgpin(S5PC1XX_GPH2(1), S5PC1XX_GPH2_1_CAM_B_DATA_1); s3c_gpio_cfgpin(S5PC1XX_GPH2(2), S5PC1XX_GPH2_2_CAM_B_DATA_2); s3c_gpio_cfgpin(S5PC1XX_GPH2(3), S5PC1XX_GPH2_3_CAM_B_DATA_3); s3c_gpio_cfgpin(S5PC1XX_GPH2(4), S5PC1XX_GPH2_4_CAM_B_DATA_4); s3c_gpio_cfgpin(S5PC1XX_GPH2(5), S5PC1XX_GPH2_5_CAM_B_DATA_5); s3c_gpio_cfgpin(S5PC1XX_GPH2(6), S5PC1XX_GPH2_6_CAM_B_DATA_6); s3c_gpio_cfgpin(S5PC1XX_GPH2(7), S5PC1XX_GPH2_7_CAM_B_DATA_7); s3c_gpio_cfgpin(S5PC1XX_GPH3(0), S5PC1XX_GPH3_0_CAM_B_PCLK); s3c_gpio_cfgpin(S5PC1XX_GPH3(1), S5PC1XX_GPH3_1_CAM_B_VSYNC); s3c_gpio_cfgpin(S5PC1XX_GPH3(2), S5PC1XX_GPH3_2_CAM_B_HREF); s3c_gpio_cfgpin(S5PC1XX_GPH3(3), S5PC1XX_GPH3_3_CAM_B_FIELD); s3c_gpio_cfgpin(S5PC1XX_GPE1(3), S5PC1XX_GPE1_3_CAM_A_CLKOUT); for (i = 0; i < 8; i++) s3c_gpio_setpull(S5PC1XX_GPH2(i), S3C_GPIO_PULL_UP); for (i = 0; i < 4; i++) s3c_gpio_setpull(S5PC1XX_GPH3(i), S3C_GPIO_PULL_UP); }
void s3c_setup_keypad_cfg_gpio(int rows, int columns) { unsigned int gpio; unsigned int end; end = S5PC1XX_GPH3(rows); /* Set all the necessary GPH2 pins to special-function 0 */ for (gpio = S5PC1XX_GPH3(0); gpio < end; gpio++) { s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3)); s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); } end = S5PC1XX_GPH2(columns); /* Set all the necessary GPK pins to special-function 0 */ for (gpio = S5PC1XX_GPH2(0); gpio < end; gpio++) { s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3)); s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); } }
static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type) { int offs = eint_offset(irq); int shift; u32 ctrl, mask; u32 newvalue = 0; switch (type) { case IRQ_TYPE_NONE: printk(KERN_WARNING "No edge setting!\n"); break; case IRQ_TYPE_EDGE_RISING: newvalue = S3C2410_EXTINT_RISEEDGE; break; case IRQ_TYPE_EDGE_FALLING: newvalue = S3C2410_EXTINT_FALLEDGE; break; case IRQ_TYPE_EDGE_BOTH: newvalue = S3C2410_EXTINT_BOTHEDGE; break; case IRQ_TYPE_LEVEL_LOW: newvalue = S3C2410_EXTINT_LOWLEV; break; case IRQ_TYPE_LEVEL_HIGH: newvalue = S3C2410_EXTINT_HILEV; break; default: printk(KERN_ERR "No such irq type %d", type); return -1; } shift = (offs & 0x7) * 4; mask = 0x7 << shift; #if 0 int flt_shift; int target_offset; flt_shift = (offs & 0x7)*8; target_offset = flt_shift/32; flt_shift = flt_shift%32; ctrl = __raw_readl((S5PC1XX_EINT30FLTCON0+target_offset)); ctrl &= ~(0xff<<flt_shift); ctrl |= (0x80 | 0x40 | 0x1) << flt_shift; //0x80:filter enable, 0x40:digital filter, 0x1: delay clocks __raw_writel(ctrl, (S5PC1XX_EINT30FLTCON0+target_offset)); #endif ctrl = __raw_readl(S5PC1XX_EINTCON(eint_conf_reg(irq))); ctrl &= ~mask; ctrl |= newvalue << shift; __raw_writel(ctrl, S5PC1XX_EINTCON(eint_conf_reg(irq))); #if defined(CONFIG_CPU_S5PC100) if((0 <= offs) && (offs < 8)) s3c_gpio_cfgpin(S5PC1XX_GPH0(offs&0x7), 0x2<<((offs&0x7)*4)); else if((8 <= offs) && (offs < 16)) s3c_gpio_cfgpin(S5PC1XX_GPH1(offs&0x7), 0x2<<((offs&0x7)*4)); else if((16 <= offs) && (offs < 24)) s3c_gpio_cfgpin(S5PC1XX_GPH2(offs&0x7), 0x2<<((offs&0x7)*4)); else if((24 <= offs) && (offs < 32)) s3c_gpio_cfgpin(S5PC1XX_GPH3(offs&0x7), 0x2<<((offs&0x7)*4)); else printk(KERN_ERR "No such irq number %d", offs); #elif defined(CONFIG_CPU_S5PC110) if((0 <= offs) && (offs < 8)) s3c_gpio_cfgpin(S5PC1XX_GPH0(offs&0x7), 0xf<<((offs&0x7)*4)); else if((8 <= offs) && (offs < 16)) s3c_gpio_cfgpin(S5PC1XX_GPH1(offs&0x7), 0xf<<((offs&0x7)*4)); else if((16 <= offs) && (offs < 24)) s3c_gpio_cfgpin(S5PC1XX_GPH2(offs&0x7), 0xf<<((offs&0x7)*4)); else if((24 <= offs) && (offs < 32)) s3c_gpio_cfgpin(S5PC1XX_GPH3(offs&0x7), 0xf<<((offs&0x7)*4)); else printk(KERN_ERR "No such irq number %d", offs); #endif return 0; }