/* * SMC Bank 1 for PB206X I2C controller */ static int smc_configure(void) { unsigned long v; printk("%s()\n", __func__); v = __raw_readl(S5PC1XX_SROM_BW); v &= ~(0xf << 4); /* v |= (0 << 4) | // data width 8bit (0 << 5) | // address mode (ignored when data width 8bit) (0 << 6) | // disabled WAIT (1 << 7); // Using UB/LB */ __raw_writel(v, S5PC1XX_SROM_BW); printk("%s: S5PC1XX_SROM_BW (%x : %x)\n", __func__, v, __raw_readl(S5PC1XX_SROM_BW)); v = S5PC1XX_SROM_BCn_PMC_NORMAL | S5PC1XX_SROM_BCn_TACP(6) | // acp: 6 clock S5PC1XX_SROM_BCn_TCAH(4) | // cah: 4 clock S5PC1XX_SROM_BCn_TCOH(1) | // coh: 1 clock S5PC1XX_SROM_BCn_TACC(0xe) | // acc: 14 clock S5PC1XX_SROM_BCn_TCOS(4) | // cos: 4 clock S5PC1XX_SROM_BCn_TACS(0); // acs: 0 clock __raw_writel(v, S5PC1XX_SROM_BC1); // bank1 printk("%s: S5PC1XX_SROM_BC1(%x : %x)\n", __func__, v, __raw_readl(S5PC1XX_SROM_BC1)); return 0; }
static void __init smdkc100_smc911x_set(void) { unsigned int tmp; tmp = __raw_readl(S5PC1XX_GPK0CON); tmp &=~S5PC1XX_GPK0_3_MASK; tmp |=(S5PC1XX_GPK0_3_SROM_CSn3); __raw_writel(tmp, S5PC1XX_GPK0CON); tmp = __raw_readl(S5PC1XX_SROM_BW); tmp &= ~(S5PC1XX_SROM_BW_BYTE_ENABLE3_MASK | S5PC1XX_SROM_BW_WAIT_ENABLE3_MASK | S5PC1XX_SROM_BW_ADDR_MODE3_MASK | S5PC1XX_SROM_BW_DATA_WIDTH3_MASK); tmp |= S5PC1XX_SROM_BW_DATA_WIDTH3_16BIT; __raw_writel(tmp, S5PC1XX_SROM_BW); __raw_writel((0x0<<28)|(0x4<<24)|(0xd<<16)|(0x1<<12)|(0x4<<8)|(0x6<<4)|(0x0<<0), S5PC1XX_SROM_BC3); __raw_writel(S5PC1XX_SROM_BCn_TACS(1) | S5PC1XX_SROM_BCn_TCOS(0) | S5PC1XX_SROM_BCn_TACC(27) | S5PC1XX_SROM_BCn_TCOH(0) | S5PC1XX_SROM_BCn_TCAH(2) | S5PC1XX_SROM_BCn_TACP(0) | S5PC1XX_SROM_BCn_PMC_NORMAL, S5PC1XX_SROM_BC3); }