int __init exynos4_init(void) { unsigned int value; unsigned int tmp; unsigned int i; printk(KERN_INFO "EXYNOS4: Initializing architecture\n"); /* set idle function */ pm_idle = exynos4_idle; /* * on exynos4x12, CMU reset system power register should to be set 0x0 */ if (!soc_is_exynos4210()) { for (i = 0; i < ARRAY_SIZE(exynos4_pmu_init_zero); i++) __raw_writel(0x0, exynos4_pmu_init_zero[i]); } /* set sw_reset function */ s5p_reset_hook = exynos4_sw_reset; /* Disable auto wakeup from power off mode */ for (i = 0; i < num_possible_cpus(); i++) { tmp = __raw_readl(S5P_ARM_CORE_OPTION(i)); tmp &= ~S5P_CORE_OPTION_DIS; __raw_writel(tmp, S5P_ARM_CORE_OPTION(i)); } if (soc_is_exynos4212() || soc_is_exynos4412()) { value = __raw_readl(S5P_AUTOMATIC_WDT_RESET_DISABLE); value &= ~S5P_SYS_WDTRESET; __raw_writel(value, S5P_AUTOMATIC_WDT_RESET_DISABLE); value = __raw_readl(S5P_MASK_WDT_RESET_REQUEST); value &= ~S5P_SYS_WDTRESET; //__raw_writel(value, S5P_MASK_WDT_RESET_REQUEST); //Temperory ignore ISP reset, for ISP test. Jiangshanbin120405 __raw_writel((value | (1<< 26)), S5P_MASK_WDT_RESET_REQUEST); } return sysdev_register(&exynos4_sysdev); }
static void exynos4_pm_resume(void) { unsigned long tmp; void __iomem *inform1; /* If PMU failed while entering sleep mode, WFI will be * ignored by PMU and then exiting cpu_do_idle(). * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically * in this situation. */ tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) { tmp |= S5P_CENTRAL_LOWPWR_CFG; __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); /* No need to perform below restore code */ pr_info("%s: early_wakeup\n", __func__); goto early_wakeup; } /* For release retention */ __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION); __raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION); __raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION); __raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION); __raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION); __raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION); __raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION); s3c_pm_do_restore(exynos4_regs_save, ARRAY_SIZE(exynos4_regs_save)); if (soc_is_exynos4210()) s3c_pm_do_restore(exynos4210_regs_save, ARRAY_SIZE(exynos4210_regs_save)); else s3c_pm_do_restore(exynos4x12_regs_save, ARRAY_SIZE(exynos4x12_regs_save)); if (!exynos4_is_c2c_use()) s3c_pm_do_restore_core(exynos4_core_save, ARRAY_SIZE(exynos4_core_save)); else { if (!soc_is_exynos4210()) { /* Gating CLK_SSS */ tmp = __raw_readl(EXYNOS4_CLKGATE_IP_DMC); tmp &= ~(0x1 << 4); __raw_writel(tmp, EXYNOS4_CLKGATE_IP_DMC); } } tmp = __raw_readl(S5P_WAKEUP_STAT); if (WARN_ON(!tmp) && soc_is_exynos4412()) { __raw_writel(__raw_readl(S5P_EINT_PEND(0)), S5P_EINT_PEND(0)); __raw_writel(__raw_readl(S5P_EINT_PEND(1)), S5P_EINT_PEND(1)); __raw_writel(__raw_readl(S5P_EINT_PEND(2)), S5P_EINT_PEND(2)); __raw_writel(__raw_readl(S5P_EINT_PEND(3)), S5P_EINT_PEND(3)); __raw_writel(0x01010001, S5P_ARM_CORE_OPTION(0)); __raw_writel(0x00000001, S5P_ARM_CORE_OPTION(1)); __raw_writel(0x00000001, S5P_ARM_CORE_OPTION(2)); __raw_writel(0x00000001, S5P_ARM_CORE_OPTION(3)); } #ifdef CONFIG_HAVE_ARM_SCU scu_enable(S5P_VA_SCU); #endif #ifdef CONFIG_CACHE_L2X0 if (trustzone_on()) { /* * Restore for Outer cache */ exynos_smc(SMC_CMD_L2X0SETUP1, exynos4_l2cc_save[0].val, exynos4_l2cc_save[1].val, exynos4_l2cc_save[2].val); exynos_smc(SMC_CMD_L2X0SETUP2, L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN, 0x7C470001, 0xC200FFFF); exynos_smc(SMC_CMD_L2X0INVALL, 0, 0, 0); exynos_smc(SMC_CMD_L2X0CTRL, 1, 0, 0); } else { s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save)); outer_inv_all(); /* enable L2X0*/ writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL); } #endif early_wakeup: if (!soc_is_exynos4210()) exynos4_reset_assert_ctrl(1); #ifdef CONFIG_CACHE_L2X0 /* Enable the full line of zero */ enable_cache_foz(); #endif if (trustzone_on()) { inform1 = S5P_VA_SYSRAM_NS + 0xC; } else { inform1 = S5P_INFORM1; } /* Clear Check mode */ __raw_writel(0x0, inform1); return; }
static void exynos4_pm_resume(void) { unsigned long tmp; /* If PMU failed while entering sleep mode, WFI will be * ignored by PMU and then exiting cpu_do_idle(). * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically * in this situation. */ tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) { tmp |= S5P_CENTRAL_LOWPWR_CFG; __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); /* No need to perform below restore code */ pr_info("%s: early_wakeup\n", __func__); goto early_wakeup; } /* For release retention */ __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION); __raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION); __raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION); __raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION); __raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION); __raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION); __raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION); s3c_pm_do_restore(exynos4_regs_save, ARRAY_SIZE(exynos4_regs_save)); if (soc_is_exynos4210()) s3c_pm_do_restore(exynos4210_regs_save, ARRAY_SIZE(exynos4210_regs_save)); else s3c_pm_do_restore(exynos4x12_regs_save, ARRAY_SIZE(exynos4x12_regs_save)); #if defined(CONFIG_MACH_M0_CTC) { if (max7693_muic_cp_usb_state()) { if (system_rev < 11) { gpio_direction_output(GPIO_USB_BOOT_EN, 1); } else if (system_rev == 11) { gpio_direction_output(GPIO_USB_BOOT_EN, 1); gpio_direction_output(GPIO_USB_BOOT_EN_REV06, 1); } else { gpio_direction_output(GPIO_USB_BOOT_EN_REV06, 1); } } } #endif CHECK_POINT; if (!exynos4_is_c2c_use()) s3c_pm_do_restore_core(exynos4_core_save, ARRAY_SIZE(exynos4_core_save)); else { if (!soc_is_exynos4210()) { /* Gating CLK_SSS */ tmp = __raw_readl(EXYNOS4_CLKGATE_IP_DMC); tmp &= ~(0x1 << 4); __raw_writel(tmp, EXYNOS4_CLKGATE_IP_DMC); } } /* For the suspend-again to check the value */ s3c_suspend_wakeup_stat = __raw_readl(S5P_WAKEUP_STAT); CHECK_POINT; if ((__raw_readl(S5P_WAKEUP_STAT) == 0) && soc_is_exynos4412()) { __raw_writel(__raw_readl(S5P_EINT_PEND(0)), S5P_EINT_PEND(0)); __raw_writel(__raw_readl(S5P_EINT_PEND(1)), S5P_EINT_PEND(1)); __raw_writel(__raw_readl(S5P_EINT_PEND(2)), S5P_EINT_PEND(2)); __raw_writel(__raw_readl(S5P_EINT_PEND(3)), S5P_EINT_PEND(3)); __raw_writel(0x01010001, S5P_ARM_CORE_OPTION(0)); __raw_writel(0x00000001, S5P_ARM_CORE_OPTION(1)); __raw_writel(0x00000001, S5P_ARM_CORE_OPTION(2)); __raw_writel(0x00000001, S5P_ARM_CORE_OPTION(3)); } scu_enable(S5P_VA_SCU); CHECK_POINT; #ifdef CONFIG_CACHE_L2X0 #ifdef CONFIG_ARM_TRUSTZONE /* * Restore for Outer cache */ exynos_smc(SMC_CMD_L2X0SETUP1, exynos4_l2cc_save[0].val, exynos4_l2cc_save[1].val, exynos4_l2cc_save[2].val); CHECK_POINT; exynos_smc(SMC_CMD_L2X0SETUP2, L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN, 0x7C470001, 0xC200FFFF); CHECK_POINT; exynos_smc(SMC_CMD_L2X0INVALL, 0, 0, 0); CHECK_POINT; exynos_smc(SMC_CMD_L2X0CTRL, 1, 0, 0); #else s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save)); outer_inv_all(); /* enable L2X0*/ writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL); #endif #endif CHECK_POINT; early_wakeup: if (!soc_is_exynos4210()) exynos4_reset_assert_ctrl(1); #ifdef CONFIG_CACHE_L2X0 /* Enable the full line of zero */ enable_cache_foz(); #endif CHECK_POINT; /* Clear Check mode */ __raw_writel(0x0, REG_INFORM1); return; }