int config_board_mux(int ctrl_type) { u8 reg12, reg14; reg12 = QIXIS_READ(brdcfg[12]); reg14 = QIXIS_READ(brdcfg[14]); switch (ctrl_type) { case MUX_TYPE_CAN: config_etseccm_source(GE2_CLK125); reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN); break; case MUX_TYPE_IIC2: reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_IIC2); break; case MUX_TYPE_RGMII: reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII); break; case MUX_TYPE_SAI: config_etseccm_source(GE2_CLK125); reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI); break; case MUX_TYPE_SDHC: reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_SDHC); break; case MUX_TYPE_SD_PCI4: reg12 = 0x38; break; case MUX_TYPE_SD_PC_SA_SG_SG: reg12 = 0x01; break; case MUX_TYPE_SD_PC_SA_PC_SG: reg12 = 0x01; break; case MUX_TYPE_SD_PC_SG_SG: reg12 = 0x21; break; default: printf("Wrong mux interface type\n"); return -1; } QIXIS_WRITE(brdcfg[12], reg12); QIXIS_WRITE(brdcfg[14], reg14); return 0; }
int config_board_mux(int ctrl_type) { u8 reg5; reg5 = QIXIS_READ(brdcfg[5]); switch (ctrl_type) { case MUX_TYPE_SDHC: reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC); break; case MUX_TYPE_DSPI: reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI); break; default: printf("Wrong mux interface type\n"); return -1; } QIXIS_WRITE(brdcfg[5], reg5); return 0; }