//============================================================================== // Configuration Functions //============================================================================== void TIMER_enter_default_mode_from_reset(void) { // // Setup Timer0 with split mode SI32_TIMER_A_select_split_timer_mode(SI32_TIMER_0); SI32_TIMER_A_set_clock_divider_counter(SI32_TIMER_0, 256 - APBCLK / TIMER0_BASE_FREQ); SI32_TIMER_A_set_clock_divider_reload(SI32_TIMER_0, 256 - APBCLK / TIMER0_BASE_FREQ); SI32_TIMER_A_select_low_clock_source_timer_clock_divider(SI32_TIMER_0); SI32_TIMER_A_select_high_clock_source_timer_clock_divider(SI32_TIMER_0); SI32_TIMER_A_enable_low_overflow_interrupt(SI32_TIMER_0); SI32_TIMER_A_enable_high_overflow_interrupt(SI32_TIMER_0); NVIC_ClearPendingIRQ(TIMER0L_IRQn); NVIC_SetPriority(TIMER0L_IRQn, TIMER0L_InterruptPriority); NVIC_EnableIRQ(TIMER0L_IRQn); NVIC_ClearPendingIRQ(TIMER0H_IRQn); NVIC_SetPriority(TIMER0H_IRQn, TIMER0H_InterruptPriority); NVIC_EnableIRQ(TIMER0H_IRQn); // Setup Timer1 with split mode SI32_TIMER_A_select_split_timer_mode(SI32_TIMER_1); SI32_TIMER_A_set_clock_divider_counter(SI32_TIMER_1, 256 - APBCLK / TIMER1_BASE_FREQ); SI32_TIMER_A_set_clock_divider_reload(SI32_TIMER_1, 256 - APBCLK / TIMER1_BASE_FREQ); SI32_TIMER_A_select_low_clock_source_timer_clock_divider(SI32_TIMER_1); SI32_TIMER_A_select_high_clock_source_timer_clock_divider(SI32_TIMER_1); SI32_TIMER_A_enable_low_overflow_interrupt(SI32_TIMER_1); SI32_TIMER_A_enable_high_overflow_interrupt(SI32_TIMER_1); NVIC_ClearPendingIRQ(TIMER1L_IRQn); NVIC_SetPriority(TIMER1L_IRQn, TIMER1L_InterruptPriority); NVIC_EnableIRQ(TIMER1L_IRQn); NVIC_ClearPendingIRQ(TIMER1H_IRQn); NVIC_SetPriority(TIMER1H_IRQn, TIMER1H_InterruptPriority); NVIC_EnableIRQ(TIMER1H_IRQn); }
void wave_125k_init(void) { SI32_TIMER_A_Type* SI32_TIMER = SI32_TIMER_1; uint16_t reload_value = get_wave_reload_value(WAVE_125K); SI32_CLKCTRL_A_enable_apb_to_modules_0(SI32_CLKCTRL_0, SI32_CLKCTRL_A_APBCLKG0_TIMER1); SI32_TIMER_A_select_square_wave_output_mode(SI32_TIMER); SI32_TIMER_A_disable_high_overflow_interrupt(SI32_TIMER); SI32_TIMER_A_disable_high_extra_interrupt(SI32_TIMER); SI32_TIMER_A_enable_stall_in_debug_mode(SI32_TIMER); SI32_TIMER_A_select_high_clock_source_apb_clock(SI32_TIMER); SI32_TIMER_A_select_split_timer_mode(SI32_TIMER); SI32_TIMER_A_set_high_count(SI32_TIMER,reload_value); SI32_TIMER_A_set_high_reload(SI32_TIMER,reload_value); SI32_TIMER_A_clear_high_overflow_interrupt(SI32_TIMER); SI32_PBCFG_A_enable_xbar0_peripherals(SI32_PBCFG_0, SI32_PBCFG_A_XBAR0_TMR1EXEN); SI32_PBSTD_A_set_pins_push_pull_output(SI32_PBSTD_0, 0x0100); }