/*****************************************************************************
* @name MCG_Init
*
* @brief: Initialization of the Multiple Clock Generator.
*
* @param : None
*
* @return : None
*****************************************************************************
* Provides clocking options for the device, including a phase-locked
* loop(PLL) and frequency-locked loop (FLL) for multiplying slower reference
* clock sources
****************************************************************************/
static void MCG_Init()
{
/* Select MCGOUT */
SIM_CLKOUT = SIM_CLKOUT_CLKOUTDIV(0)|SIM_CLKOUT_CS(3);
/* configure the Trim values for internal RC (slow) to get MCGOUT at 50MHz */
MCG_C3 = 0x30;
/* configure the DRS=1 */
MCG_C4 = 0xB0;
SIM_SOPT3 |= SIM_SOPT3_RWE_MASK;
SIM_SOPT1 |= SIM_SOPT1_REGE_MASK;
SIM_SOPT7 |= 0x80;
// PLL/FLL selected as CLK source
SIM_CLKDIV1 = 0x01;
}
void showClocks(void) {
// Put SYSTEM_MCGOUTCLK_CLOCK on PTA5
SIM_SCGC6 |= SIM_SCGC6_PORTA_MASK;
MXC_PTAPF2 = (MXC_PTAPF2&~MXC_PTAPF2_A5_MASK)|MXC_PTAPF2_A5(6);
/*
* 0 Disabled (reset value)
* 1 OSC1ERCLK (from OSC1)
* 2 OSC2ERCLK (from OSC2)
* 3 MCGOUTCLK
* 4 CPUCLK/SYSCLK
* 5 BUSCLK
* 6 LPO
* 7 LPTMR0 prescaler clock output
*/
SIM_CLKOUT = SIM_CLKOUT_CS(5)|SIM_CLKOUT_CLKOUTDIV(0);
}