/*lint -esym(765,Cpu_Interrupt) Disable MISRA rule (8.10) checking for symbols (Cpu_Interrupt). */
void __init_hardware(void)
{
/*** !!! Here you can place your own code before PE initialization using property "User code before PE initialization" on the build options tab. !!! ***/
/*** ### MKL25Z128VLK4 "Cpu" init code ... ***/
/*** PE initialization code after reset ***/
SCB_VTOR = (uint32_t)(&__vect_table); /* Set the interrupt vector table position */
/* Disable the WDOG module */
/* SIM_COPC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,COPT=0,COPCLKS=0,COPW=0 */
SIM_COPC = SIM_COPC_COPT(0x00);
/* System clock initialization */
/* SIM_CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=3,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
SIM_CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x03)); /* Set the system prescalers to safe value */
/* SIM_SCGC5: PORTD=1,PORTB=1,PORTA=1 */
SIM_SCGC5 |= SIM_SCGC5_PORTD_MASK |
SIM_SCGC5_PORTB_MASK |
SIM_SCGC5_PORTA_MASK; /* Enable clock gate for ports to enable pin routing */
if ((PMC_REGSC & PMC_REGSC_ACKISO_MASK) != 0x0U) {
/* PMC_REGSC: ACKISO=1 */
PMC_REGSC |= PMC_REGSC_ACKISO_MASK; /* Release IO pads after wakeup from VLLS mode. */
}
/* SIM_CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
SIM_CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x00)); /* Update system prescalers */
/* SIM_SOPT2: PLLFLLSEL=0 */
SIM_SOPT2 &= (uint32_t)~(uint32_t)(SIM_SOPT2_PLLFLLSEL_MASK); /* Select FLL as a clock source for various peripherals */
/* SIM_SOPT1: OSC32KSEL=3 */
SIM_SOPT1 |= SIM_SOPT1_OSC32KSEL(0x03); /* LPO 1kHz oscillator drives 32 kHz clock for various peripherals */
/* SIM_SOPT2: TPMSRC=1 */
SIM_SOPT2 = (uint32_t)((SIM_SOPT2 & (uint32_t)~(uint32_t)(
SIM_SOPT2_TPMSRC(0x02)
)) | (uint32_t)(
SIM_SOPT2_TPMSRC(0x01)
)); /* Set the TPM clock */
/* Switch to FEI Mode */
/* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
MCG_C1 = MCG_C1_CLKS(0x00) |
MCG_C1_FRDIV(0x00) |
MCG_C1_IREFS_MASK |
MCG_C1_IRCLKEN_MASK;
/* MCG_C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
MCG_C2 = MCG_C2_RANGE0(0x00);
/* MCG_C4: DMX32=0,DRST_DRS=0 */
MCG_C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03)));
/* OSC0_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
OSC0_CR = OSC_CR_ERCLKEN_MASK;
/* MCG_C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
MCG_C5 = MCG_C5_PRDIV0(0x00);
/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
MCG_C6 = MCG_C6_VDIV0(0x00);
while((MCG_S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
}
while((MCG_S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */
}
/*** End of PE initialization code after reset ***/
/*** !!! Here you can place your own code after PE initialization using property "User code after PE initialization" on the build options tab. !!! ***/
}
static void SetSIMRegisters()
{
// TODO
SIM->COPC = SIM_COPC_COPT(0);//disable watchdog immediately
//do the rest in order listed in data sheet
SIM->SOPT2 = SIM_SOPT2_UART0SRC(0)|SIM_SOPT2_TPMSRC(0);//no clocks enabled for
// uart0 or TPM counterClock
SIM->SOPT4 = ((0 << SIM_SOPT4_TPM1CLKSEL_SHIFT)&SIM_SOPT4_TPM1CLKSEL_MASK)|((0 << SIM_SOPT4_TPM0CLKSEL_SHIFT)&SIM_SOPT4_TPM0CLKSEL_MASK)|((0<<SIM_SOPT4_TPM1CH0SRC_SHIFT)&SIM_SOPT4_TPM1CH0SRC_MASK);//don't care settings
SIM->SOPT5 = ((0<<SIM_SOPT5_UART0ODE_SHIFT)&SIM_SOPT5_UART0ODE_MASK)|((0<<SIM_SOPT5_UART0RXSRC_SHIFT)&SIM_SOPT5_UART0RXSRC_MASK)|((0<<SIM_SOPT5_UART0TXSRC_SHIFT)&SIM_SOPT5_UART0TXSRC_MASK);//don't cares
SIM->SOPT7 = ((0<<SIM_SOPT7_ADC0ALTTRGEN_SHIFT)&SIM_SOPT7_ADC0ALTTRGEN_MASK)|((0<<SIM_SOPT7_ADC0PRETRGSEL_SHIFT)&SIM_SOPT7_ADC0PRETRGSEL_MASK)|((0<<SIM_SOPT7_ADC0TRGSEL_SHIFT)&SIM_SOPT7_ADC0TRGSEL_MASK);//don't cares
SIM->SCGC4 = ((1<<SIM_SCGC4_SPI0_SHIFT)&SIM_SCGC4_SPI0_MASK)|((0<<SIM_SCGC4_CMP_SHIFT)&SIM_SCGC4_CMP_MASK)|((0<<SIM_SCGC4_UART0_SHIFT)&SIM_SCGC4_UART0_MASK)|((1<<SIM_SCGC4_I2C1_SHIFT)&SIM_SCGC4_I2C1_MASK)|((1<<SIM_SCGC4_I2C0_SHIFT)&SIM_SCGC4_I2C0_MASK);//enable the I2C module
SIM->SCGC5 = ((1<<SIM_SCGC5_PORTB_SHIFT)&SIM_SCGC5_PORTB_MASK)|((1<<SIM_SCGC5_PORTA_SHIFT)&SIM_SCGC5_PORTA_MASK)|((0<<SIM_SCGC5_LPTMR_SHIFT)&SIM_SCGC5_LPTMR_MASK);//enable both ports
SIM->SCGC6 = ((0<<SIM_SCGC6_ADC0_SHIFT)&SIM_SCGC6_ADC0_MASK)|((0<<SIM_SCGC6_TPM1_SHIFT)&SIM_SCGC6_TPM1_MASK)|((0<<SIM_SCGC6_TPM0_SHIFT)&SIM_SCGC6_TPM0_MASK)|((0<<SIM_SCGC6_FTF_SHIFT)&SIM_SCGC6_FTF_MASK);//don't cares
SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0)|SIM_CLKDIV1_OUTDIV4(4);//clk configured for 4MHz core, .8 MHz Bus Clk (fastest allowable in BLPI mode)
//this is unchanged from default, do not alter. If we need to save power we can turn off flash, but this has caused hard faults. we need to move the interrupt vectors out of flash to do this SIM_FCFG1 = ((0<<SIM_FCFG1_FLASHDOZE_SHIFT)&SIM_FCFG1_FLASHDOZE_MASK)|((0<<SIM_FCFG1_FLASHDIS_SHIFT)&SIM_FCFG1_FLASHDIS_MASK);//flash disabled to conserve power, other settings are don't cares, TODO:verify flash size setting is unimportant
//SIM_FCFG2 = SIM_FCFG2 only has maxaddr0, which is read only.
//SIM_SRVCOP, we do not need to reset timer, it is disabled already.
return;
}
/*---------------------------------------------------------------------------*/
void
watchdog_init(void)
{
#if PLATFORM_CONF_ENABLE_WATCHDOG
/* SIM_COPC: ??=0,??=0,??=0,??=0,COPT=3,COPCLKS=0,COPW=0 */
SIM_COPC = (uint32_t) ((SIM_COPC
& (uint32_t) ~(uint32_t) (SIM_COPC_COPCLKS_MASK | SIM_COPC_COPW_MASK
| 0xF0U)) | (uint32_t) (SIM_COPC_COPT(0x03))); /* Set control register */
watchdog_stop();
#endif /* PLATFORM_CONF_ENABLE_WATCHDOG */
}
/**
**===========================================================================
** Reset handler
**===========================================================================
*/
void __init_hardware(void) {
/* This is a cleaned up output of Processor Expert generated code */
/* Set the interrupt vector table position */
SCB_VTOR = (uint32_t)__vector_table;
#if 0
/* Disable the WDOG module */
SIM_COPC = SIM_COPC_COPT(0x00);
#endif
/* System clock initialization */
/* Enable clock gate for ports to enable pin routing */
SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
/* Update system prescalers */
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x01);
/* Select FLL as a clock source for various peripherals */
SIM_SOPT2 &= ~SIM_SOPT2_PLLFLLSEL_MASK;
/* LPO 1kHz oscillator drives 32 kHz clock for various peripherals */
SIM_SOPT1 |= SIM_SOPT1_OSC32KSEL(0x03);
/* Set the TPM clock */
SIM_SOPT2 &= ~SIM_SOPT2_TPMSRC(0x01);
SIM_SOPT2 |= SIM_SOPT2_TPMSRC(0x02);
/* Enable XTAL IO pins */
PORTA_PCR18 = PORT_PCR_MUX(0);
PORTA_PCR19 = PORT_PCR_MUX(0);
/* Switch to FBE Mode */
MCG_C2 = MCG_C2_RANGE0(0x02) | MCG_C2_EREFS0_MASK;
OSC0_CR = OSC_CR_ERCLKEN_MASK;
MCG_C1 = MCG_C1_CLKS(0x02) | MCG_C1_FRDIV(0x03) | MCG_C1_IRCLKEN_MASK;
MCG_C4 &= ~MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03);
MCG_C5 = MCG_C5_PRDIV0(0x03);
MCG_C6 = MCG_C6_VDIV0(0x00);
/* Check that the source of the FLL reference clock is the external reference clock. */
while((MCG_S & MCG_S_IREFST_MASK) != 0x00U);
/* Wait until external reference clock is selected as MCG output */
while((MCG_S & 0x0CU) != 0x08U);
/* Switch to PBE Mode */
MCG_C6 = (MCG_C6_PLLS_MASK | MCG_C6_VDIV0(0x00));
/* Wait until external reference clock is selected as MCG output */
while((MCG_S & 0x0CU) != 0x08U);
/* Wait until locked */
while((MCG_S & MCG_S_LOCK0_MASK) == 0x00U);
/* Switch to PEE Mode */
MCG_C1 = MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x03) | MCG_C1_IRCLKEN_MASK;
/* Wait until output of the PLL is selected */
while((MCG_S & 0x0CU) != 0x0CU);
}
/*lint -esym(765,Cpu_Interrupt) Disable MISRA rule (8.10) checking for symbols (Cpu_Interrupt). */
void __init_hardware(void)
{
/*** !!! Here you can place your own code before PE initialization using property "User code before PE initialization" on the build options tab. !!! ***/
/*** ### MKL46Z256VMC4 "Cpu" init code ... ***/
/*** PE initialization code after reset ***/
SCB_VTOR = (uint32_t)(&__vect_table); /* Set the interrupt vector table position */
/* Disable the WDOG module */
/* SIM_COPC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,COPT=0,COPCLKS=0,COPW=0 */
SIM_COPC = SIM_COPC_COPT(0x00);
/* System clock initialization */
/* SIM_SCGC5: PORTE=1,PORTC=1,PORTB=1,PORTA=1 */
SIM_SCGC5 |= SIM_SCGC5_PORTE_MASK |
SIM_SCGC5_PORTC_MASK |
SIM_SCGC5_PORTB_MASK |
SIM_SCGC5_PORTA_MASK; /* Enable clock gate for ports to enable pin routing */
/* SIM_CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
SIM_CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x01)); /* Update system prescalers */
/* SIM_SOPT2: PLLFLLSEL=1 */
SIM_SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK; /* Select PLL as a clock source for various peripherals */
/* SIM_SOPT1: OSC32KSEL=2 */
SIM_SOPT1 = (uint32_t)((SIM_SOPT1 & (uint32_t)~(uint32_t)(
SIM_SOPT1_OSC32KSEL(0x01)
)) | (uint32_t)(
SIM_SOPT1_OSC32KSEL(0x02)
)); /* System oscillator drives 32 kHz clock for various peripherals */
/* SIM_SOPT2: TPMSRC=1 */
SIM_SOPT2 = (uint32_t)((SIM_SOPT2 & (uint32_t)~(uint32_t)(
SIM_SOPT2_TPMSRC(0x02)
)) | (uint32_t)(
SIM_SOPT2_TPMSRC(0x01)
)); /* Set the TPM clock */
/* PORTA_PCR18: ISF=0,MUX=0 */
PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
/* PORTA_PCR19: ISF=0,MUX=0 */
PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
/* Switch to FBE Mode */
/* MCG_C2: LOCRE0=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
MCG_C2 = (uint8_t)((MCG_C2 & (uint8_t)~(uint8_t)(
MCG_C2_LOCRE0_MASK |
MCG_C2_RANGE0(0x01) |
MCG_C2_HGO0_MASK |
MCG_C2_LP_MASK |
MCG_C2_IRCS_MASK
)) | (uint8_t)(
MCG_C2_RANGE0(0x02) |
MCG_C2_EREFS0_MASK
));
/* OSC0_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
OSC0_CR = OSC_CR_ERCLKEN_MASK;
/* MCG_C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
MCG_C1 = (MCG_C1_CLKS(0x02) | MCG_C1_FRDIV(0x03) | MCG_C1_IRCLKEN_MASK);
/* MCG_C4: DMX32=0,DRST_DRS=0 */
MCG_C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03)));
/* MCG_C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=3 */
MCG_C5 = MCG_C5_PRDIV0(0x03);
/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
MCG_C6 = MCG_C6_VDIV0(0x00);
while((MCG_S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
}
while((MCG_S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
}
/* Switch to PBE Mode */
/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0 */
MCG_C6 = (MCG_C6_PLLS_MASK | MCG_C6_VDIV0(0x00));
while((MCG_S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
}
while((MCG_S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until locked */
}
/* Switch to PEE Mode */
/* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
MCG_C1 = (MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x03) | MCG_C1_IRCLKEN_MASK);
while((MCG_S & 0x0CU) != 0x0CU) { /* Wait until output of the PLL is selected */
}
/* Initialization of the RTC_CLKIN pin */
/* PORTC_PCR1: ISF=0,MUX=1 */
PORTC_PCR1 = (uint32_t)((PORTC_PCR1 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x06)
)) | (uint32_t)(
PORT_PCR_MUX(0x01)
));
/*** End of PE initialization code after reset ***/
/*** !!! Here you can place your own code after PE initialization using property "User code after PE initialization" on the build options tab. !!! ***/
}
/**
* @brief Low-level initialize the system
*
* Low level setup of the microcontroller system. \n
* Called very early in the initialisation. \n
* May NOT use globals etc (as will be overwritten by BSS initialization)
*/
void SystemInitLowLevel(void) {
/*
* This is generic initialization code
* It may not be correct for a specific target
*/
#ifdef __VTOR_PRESENT
/* Set the interrupt vector table position */
SCB->VTOR = (uint32_t)__vector_table;
#endif
#ifdef SCB_CCR_DIV_0_TRP_Msk
/* Enable trapping of divide by zero */
SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk;
#endif
#ifdef RCM_MR_BOOTROM
// Clear Boot ROM flag
RCM->MR = RCM_MR_BOOTROM(3);
#endif
#if defined(SIM_COPC_COPT_MASK)
// Disable watch-dog
SIM->COPC = SIM_COPC_COPT(0);
#endif
#ifdef WDOG_CS_UPDATE
/* Unlocking Watchdog word */
#define WDOG_UPDATE_KEY (0xD928C520U)
// Disable watch-dog
WDOG->CNT = WDOG_UPDATE_KEY; // Write the unlock word
WDOG->TOVAL = -1; // Setting time-out value
WDOG->CS =
WDOG_CS_CLK(1) | // Setting 1-kHz clock source
WDOG_CS_UPDATE(1); // Allow future update
#endif
#ifdef WDOG_CS1_UPDATE_MASK
/* Unlocking Watchdog sequence words*/
#define WDOG_KEY1 (0x20C5)
#define WDOG_KEY2 (0x28D9)
/* Disable watch-dog */
WDOG->CNT = WDOG_KEY1; // Write the 1st unlock word
WDOG->CNT = WDOG_KEY2; // Write the 2nd unlock word
WDOG->TOVAL = -1; // Setting time-out value
WDOG->CS2 = WDOG_CS2_CLK(1); // Setting 1-kHz clock source
WDOG->CS1 = WDOG_CS1_UPDATE(1); // Disable watchdog and allow future changes
#endif
#ifdef WDOG_UNLOCK_WDOGUNLOCK_MASK
/* Unlocking Watchdog sequence words*/
#define WDOG_KEY1 (0xC520)
#define WDOG_KEY2 (0xD928)
/* Disable watch-dog */
WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(WDOG_KEY1);
WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(WDOG_KEY2);
__DSB();
WDOG->STCTRLH =
WDOG_STCTRLH_WDOGEN(0)| // Disable WDOG
WDOG_STCTRLH_ALLOWUPDATE(1)| // Allow future updates
WDOG_STCTRLH_CLKSRC(0); // WDOG clk=LPO
#endif
}
