int larb_clock_off(int larb_id, const char *mod_name) { larb_on_count--; //SMIDBG("larb_clock_off, %s, %d \n", mod_name, larb_on_count); #ifndef CONFIG_EARLY_LINUX_PORTING switch(larb_id) { case 0: // disable_clock(MT_CG_SMI_COMMON_SW_CG, mod_name); // disable_clock(MT_CG_SMI_LARB0_SW_CG, mod_name); break; default: SMIERR("larb_clock_off: larb_id %s error\n", mod_name); break; } #endif return 0; }
/***************************************************************************** * FUNCTION * smi_init * DESCRIPTION * Call platform_driver_register to register SMI driver * PARAMETERS * None. * RETURNS * Type: Integer. zero mean success and others mean fail. ****************************************************************************/ static int __init smi_init(void) { if(platform_driver_register(&smiDrv)){ SMIERR("failed to register MAU driver"); return -ENODEV; } return 0; }
static int __init smi_init(void) { spin_lock_init(&g_SMIInfo.SMI_lock); memset(g_SMIInfo.pu4ConcurrencyTable , 0 , SMI_BWC_SCEN_CNT*sizeof(unsigned long)); if(platform_driver_register(&smiDrv)){ SMIERR("failed to register MAU driver"); return -ENODEV; } return 0; }
int mau_init(void) { int i; if(request_irq(MT_SMI_LARB0_IRQ_ID , (irq_handler_t)mau_isr, IRQF_TRIGGER_LOW, "MAU0" , NULL)) { SMIERR("request MAU0 IRQ line failed"); return -ENODEV; } if(request_irq(MT_SMI_LARB1_IRQ_ID , (irq_handler_t)mau_isr, IRQF_TRIGGER_LOW, "MAU1" , NULL)) { SMIERR("request MAU1 IRQ line failed"); return -ENODEV; } if(request_irq(MT_SMI_LARB2_IRQ_ID , (irq_handler_t)mau_isr, IRQF_TRIGGER_LOW, "MAU2" , NULL)) { SMIERR("request MAU2 IRQ line failed"); return -ENODEV; } if(request_irq(MT_SMI_LARB3_IRQ_ID , (irq_handler_t)mau_isr, IRQF_TRIGGER_LOW, "MAU3" , NULL)) { SMIERR("request MAU3 IRQ line failed"); return -ENODEV; } if(request_irq(MT_SMI_LARB4_IRQ_ID , (irq_handler_t)mau_isr, IRQF_TRIGGER_LOW, "MAU4" , NULL)) { SMIERR("request MAU4 IRQ line failed"); return -ENODEV; } for(i=0; i<SMI_LARB_NR; i++) { larb_clock_on(i); mau_enable_interrupt(i); larb_clock_off(i); } return 0; }
int larb_reg_restore(int larb) { unsigned int regval,regval1,regval2; unsigned int larb_base = gLarbBaseAddr[larb]; /* unsigned int* pReg = pLarbRegBackUp[larb]; int i; //warning: larb_con is controlled by set/clr regval = *(pReg++); M4U_WriteReg32(larb_base, SMI_LARB_CON_CLR, ~(regval)); M4U_WriteReg32(larb_base, SMI_LARB_CON_SET, (regval)); M4U_WriteReg32(larb_base, SMI_SHARE_EN, *(pReg++) ); M4U_WriteReg32(larb_base, SMI_ROUTE_SEL, *(pReg++) ); for(i=0; i<3; i++) { M4U_WriteReg32(larb_base, SMI_MAU_ENTR_START(i), *(pReg++)); M4U_WriteReg32(larb_base, SMI_MAU_ENTR_END(i), *(pReg++)); M4U_WriteReg32(larb_base, SMI_MAU_ENTR_GID(i), *(pReg++)); } */ //Clock manager enable LARB clock before call back restore already, it will be disabled after restore call back returns //Got to enable OSTD before engine starts regval = M4U_ReadReg32(larb_base , SMI_LARB_STAT); regval1 = M4U_ReadReg32(larb_base , SMI_LARB_MON_BUS_REQ0); regval2 = M4U_ReadReg32(larb_base , SMI_LARB_MON_BUS_REQ1); if(0 == regval) { M4U_WriteReg32(larb_base , SMI_LARB_OSTD_CTRL_EN , 0xffffffff); } else { SMIMSG("Larb%d is busy : 0x%x , port:0x%x,0x%x ,fail to set OSTD\n" , larb , regval , regval1 , regval2); smi_dumpDebugMsg(); SMIERR("DISP_MDP LARB%d OSTD cannot be set:0x%x,port:0x%x,0x%x\n" , larb , regval , regval1 , regval2); } if(0 == g_bInited) { initSetting(); g_bInited = 1; SMIMSG("SMI init\n"); } return 0; }
/***************************************************************************** * FUNCTION * smi_common_init * DESCRIPTION * Allocate register backup memory. * PARAMETERS * None. * RETURNS * Type: Integer. always zero. ****************************************************************************/ int smi_common_init(void) { int i; for(i=0; i<SMI_LARB_NR; i++) { pLarbRegBackUp[i] = (unsigned int*)kmalloc(LARB_BACKUP_REG_SIZE, GFP_KERNEL|__GFP_ZERO); if(pLarbRegBackUp[i]==NULL) { SMIERR("pLarbRegBackUp kmalloc fail %d \n", i); } } register_larb_monitor(&larb_monitor_handler); return 0; }
/***************************************************************************** * FUNCTION * mau_isr * DESCRIPTION * 1. Print MAU status, such as port ID. * 2. Clear interrupt status. * PARAMETERS * param1 : [IN] int irq * irq number. * param2 : [IN] void *dev_id * No use in this function. * RETURNS * Type: irqreturn_t. IRQ_HANDLED mean success. ****************************************************************************/ static irqreturn_t mau_isr(int irq, void *dev_id) { int larb,i; unsigned int larb_base; unsigned int regval; switch(irq) { case MT_SMI_LARB0_IRQ_ID: larb = 0; break; default : larb=0; SMIERR("unkown irq(%d)\n",irq); } larb_clock_on(larb, "MAU"); larb_base = gLarbBaseAddr[larb]; //dump interrupt debug infomation for(i=0; i<MAU_ENTRY_NR; i++) { regval = M4U_ReadReg32(larb_base, SMI_MAU_ENTR_STAT(i)); if(F_MAU_STAT_ASSERT(regval)) { //violation happens in this entry int port = F_MAU_STAT_ID(regval); SMIMSG("[MAU] larb=%d, entry=%d, port=%d\n",larb,i,port); regval = M4U_ReadReg32(larb_base, SMI_MAU_ENTR_START(i)); SMIMSG("start_addr=0x%x, read_en=%d, write_en=%d\n", F_MAU_START_ADDR_VAL(regval), F_MAU_START_IS_RD(regval), F_MAU_START_IS_WR(regval)); regval = M4U_ReadReg32(larb_base, SMI_MAU_ENTR_END(i)); SMIMSG("end_addr=0x%x, virtual=%d\n", F_MAU_END_ADDR_VAL(regval), F_MAU_END_IS_VIR(regval)); smi_aee_print("violation by %s\n",smi_port_name[port]); } //clear interrupt status regval = M4U_ReadReg32(larb_base, SMI_MAU_ENTR_STAT(i)); M4U_WriteReg32(larb_base, SMI_MAU_ENTR_STAT(i), regval); } larb_clock_off(larb, "MAU"); return IRQ_HANDLED; }
/***************************************************************************** * FUNCTION * smi_ioctl * DESCRIPTION * File operations - unlocked_ioctl * 1. call copy_from_user to get user space parameter * 2. call internal function by operation. * PARAMETERS * param1 : [IN] struct file * pFile * file structure*. * param2 : [IN] unsigned int cmd * operation command. * param3 : [IN] unsigned long param * parameter of ioctl. * RETURNS * Type: Integer. zero means success and others mean error. ****************************************************************************/ static long smi_ioctl(struct file * pFile, unsigned int cmd, unsigned long param) { int ret = 0; switch (cmd) { case MTK_CONFIG_MM_MAU: { MTK_MAU_CONFIG b; if(copy_from_user(&b, (void __user *)param, sizeof(b))) { SMIERR("copy_from_user failed!"); ret = -EFAULT; } else { mau_config(&b); } return ret; } case MTK_IOC_SMI_BWC_CONFIG: { MTK_SMI_BWC_CONFIG cfg; ret = copy_from_user(&cfg, (void*)param , sizeof(MTK_SMI_BWC_CONFIG)); if(ret) { SMIMSG(" SMI_BWC_CONFIG, copy_from_user failed: %d\n", ret); return -EFAULT; } smi_bwc_config( &cfg ); } break; default: return -1; } return ret; }
static void process_dbg_opt(const char *opt) { //m4u log if (0 == strncmp(opt, "m4u_log:", 8)) { if (0 == strncmp(opt + 8, "on", 2)) m4u_log_on(); else if (0 == strncmp(opt + 8, "off", 3)) m4u_log_off(); else goto Error; } //m4u debug if (0 == strncmp(opt, "m4u_debug:", 10)) { unsigned int command; char *p = (char *)opt + 10; command = (unsigned int) simple_strtoul(p, &p, 10); SMIMSG("m4u_debug_command, command=%d ", command); m4u_debug_command(command); } //mau dump if (0 == strncmp(opt, "mau_stat:", 9)) { char *p = (char *)opt + 9; unsigned int larb=(unsigned int)simple_strtoul(p, &p, 16); if(larb>SMI_LARB_NR) SMIERR("debug error: larb=%d\n", larb); mau_dump_status(larb); } if (0 == strncmp(opt, "mau_config:", 11 )) { MTK_MAU_CONFIG MauConf; unsigned int larb,entry, rd, wt, vir, start, end, port_msk; char *p = (char *)opt + 11; larb = (unsigned int) simple_strtoul(p, &p, 16); p++; entry = (unsigned int) simple_strtoul(p, &p, 16); p++; rd = (unsigned int) simple_strtoul(p, &p, 16); p++; wt = (unsigned int) simple_strtoul(p, &p, 16); p++; vir = (unsigned int) simple_strtoul(p, &p, 16); p++; start = (unsigned int) simple_strtoul(p, &p, 16); p++; end = (unsigned int) simple_strtoul(p, &p, 16); p++; port_msk = (unsigned int) simple_strtoul(p, &p, 16); SMIMSG("larb=%d,entry=%d,rd=%d wt=%d vir=%d \n" "start=0x%x end=0x%x msk=0x%x \n", larb, entry, rd, wt, vir, start, end, port_msk); MauConf.larb = larb; MauConf.entry = entry; MauConf.monitor_read = rd; MauConf.monitor_write = wt; MauConf.virt = vir; MauConf.start = start; MauConf.end = end; MauConf.port_msk = port_msk; mau_config(&MauConf); } if (0 == strncmp(opt, "spc_config:", 11 )) { MTK_SPC_CONFIG pCfg; char *p = (char *)opt + 11; SMIMSG("%s", p); //0-no protect; 1-sec rw; 2-sec_rw nonsec_r; 3-no access pCfg.domain_0_prot = (unsigned int) simple_strtoul(p, &p, 16); SMIMSG("%d,%s", pCfg.domain_0_prot, p); p++; pCfg.domain_1_prot = (unsigned int) simple_strtoul(p, &p, 16); p++; SMIMSG("%d", pCfg.domain_1_prot); pCfg.domain_2_prot = (unsigned int) simple_strtoul(p, &p, 16); p++; SMIMSG("%d", pCfg.domain_2_prot); pCfg.domain_3_prot = (unsigned int) simple_strtoul(p, &p, 16); p++; SMIMSG("%d", pCfg.domain_3_prot); pCfg.start = (unsigned int) simple_strtoul(p, &p, 16); p++; SMIMSG("%d", pCfg.domain_0_prot); pCfg.end = (unsigned int) simple_strtoul(p, &p, 16); SMIMSG("prot=(%d,%d,%d,%d), start=0x%x, end=0x%x\n", pCfg.domain_0_prot,pCfg.domain_1_prot, pCfg.domain_2_prot,pCfg.domain_3_prot, pCfg.start,pCfg.end); spc_config(&pCfg); } if (0 == strncmp(opt, "spc_status", 10 )) { spc_status_check(); } if (0 == strncmp(opt, "spc_dump_reg", 12 )) { spc_dump_reg(); } if (0 == strncmp(opt, "touch_sysram", 10 )) { volatile unsigned int *va; unsigned int i; //va = ioremap_nocache(0x1200C000, 1024*80); va=(volatile unsigned int *)0xf2000000; for(i=0; i<1024*80/4; i++) { va[i] = i; } SMIMSG("cpu read sysram: 0x%x,0x%x,0x%x,0x%x,0x%x,0x%x,0x%x", va[0],va[1],va[2],va[3],va[100],va[222],va[444]); } if (0 == strncmp(opt, "set_reg:", 8 )) { unsigned int addr, val; char *p = (char *)opt + 8; addr = (unsigned int) simple_strtoul(p, &p, 16); p++; val = (unsigned int) simple_strtoul(p, &p, 16); SMIMSG("set register: 0x%x = 0x%x\n", addr, val); COM_WriteReg32(addr, val); } if (0 == strncmp(opt, "get_reg:", 8 )) { unsigned int addr; char *p = (char *)opt + 8; addr = (unsigned int) simple_strtoul(p, &p, 16); SMIMSG("get register: 0x%x = 0x%x \n", addr, COM_ReadReg32(addr)); } return; Error: SMIERR("parse command error!\n"); SMIMSG("%s", STR_HELP); }
static int smi_probe(struct platform_device *pdev) { struct device* smiDevice = NULL; if (NULL == pdev) { SMIERR("platform data missed"); return -ENXIO; } if (smi_register()) { dev_err(&pdev->dev,"register char failed\n"); return -EAGAIN; } pSmiClass = class_create(THIS_MODULE, "MTK_SMI"); if (IS_ERR(pSmiClass)) { int ret = PTR_ERR(pSmiClass); SMIERR("Unable to create class, err = %d", ret); return ret; } smiDevice = device_create(pSmiClass, NULL, smiDevNo, NULL, "MTK_SMI"); smi_common_init(); #ifdef __MAU_SPC_ENABLE__ mau_init(); MTK_SPC_Init(&(pdev->dev)); #endif SMI_DBG_Init(); #ifdef __MAU_SPC_ENABLE__ //init mau to monitor mva 0~0x2ffff & 0x40000000~0xffffffff #if 0 { MTK_MAU_CONFIG cfg; int i; for( i=0 ; i < SMI_LARB_NR ; i++) { cfg.larb = i; cfg.entry = 0; cfg.port_msk = 0xffffffff; cfg.virt = 1; cfg.monitor_read = 1; cfg.monitor_write = 1; cfg.start = 0; cfg.end = 0x2ffff; mau_config(&cfg); cfg.entry = 1; cfg.start = 0x40000000; cfg.end = 0xffffffff; mau_config(&cfg); } } #endif #endif return 0; }
static long smi_ioctl( struct file * pFile, unsigned int cmd, unsigned long param) { int ret = 0; // unsigned long * pu4Cnt = (unsigned long *)pFile->private_data; switch (cmd) { #ifdef __MAU_SPC_ENABLE__ case MTK_CONFIG_MM_MAU: { MTK_MAU_CONFIG b; if(copy_from_user(&b, (void __user *)param, sizeof(b))) { SMIERR("copy_from_user failed!"); ret = -EFAULT; } else { mau_config(&b); } return ret; } case MTK_IOC_SPC_CONFIG : { MTK_SPC_CONFIG cfg; ret = copy_from_user(&cfg, (void*)param , sizeof(MTK_SPC_CONFIG)); if(ret) { SMIMSG(" SPC_CONFIG, copy_from_user failed: %d\n", ret); return -EFAULT; } spc_config(&cfg); } break; case MTK_IOC_SPC_DUMP_REG : spc_dump_reg(); break; case MTK_IOC_SPC_DUMP_STA : spc_status_check(); break; case MTK_IOC_SPC_CMD : spc_test(param); break; #endif case MTK_IOC_SMI_BWC_CONFIG: { MTK_SMI_BWC_CONFIG cfg; ret = copy_from_user(&cfg, (void*)param , sizeof(MTK_SMI_BWC_CONFIG)); if(ret) { SMIMSG(" SMI_BWC_CONFIG, copy_from_user failed: %d\n", ret); return -EFAULT; } // ret = smi_bwc_config( &cfg , pu4Cnt); ret = smi_bwc_config( &cfg , NULL); } break; // GMP start case MTK_IOC_SMI_BWC_INFO_SET: { MTK_SMI_BWC_INFO_SET cfg; SMIMSG("Handle MTK_IOC_SMI_BWC_INFO_SET request... start"); ret = copy_from_user(&cfg, (void*)param , sizeof(MTK_SMI_BWC_INFO_SET)); if(ret) { SMIMSG(" MTK_IOC_SMI_BWC_INFO_SET, copy_to_user failed: %d\n", ret); return -EFAULT; } // Set the address to the value assigned by user space program smi_bwc_mm_info_set(cfg.property, cfg.value1, cfg.value2); SMIMSG("Handle MTK_IOC_SMI_BWC_INFO_SET request... finish"); break; } case MTK_IOC_SMI_BWC_INFO_GET: { MTK_SMI_BWC_INFO_GET cfg; MTK_SMI_BWC_MM_INFO * return_address = NULL; SMIMSG("Handle MTK_IOC_SMI_BWC_INFO_GET request... start"); ret = copy_from_user(&cfg, (void*)param , sizeof(MTK_SMI_BWC_INFO_GET)); if(ret) { SMIMSG(" MTK_IOC_SMI_BWC_INFO_GET, copy_to_user failed: %d\n", ret); return -EFAULT; } return_address = (MTK_SMI_BWC_MM_INFO *)cfg.return_address; if( return_address != NULL){ ret = copy_to_user((void*) return_address, (void*)&g_smi_bwc_mm_info, sizeof(MTK_SMI_BWC_MM_INFO)); if(ret) { SMIMSG(" MTK_IOC_SMI_BWC_INFO_GET, copy_to_user failed: %d\n", ret); return -EFAULT; } } SMIMSG("Handle MTK_IOC_SMI_BWC_INFO_GET request... finish"); break; } // GMP end default: return -1; } return ret; }
static int smi_bwc_config( MTK_SMI_BWC_CONFIG* p_conf , unsigned long * pu4LocalCnt) { int i; unsigned long u4Concurrency = 0; MTK_SMI_BWC_SCEN eFinalScen; static MTK_SMI_BWC_SCEN ePreviousFinalScen = SMI_BWC_SCEN_CNT; if((SMI_BWC_SCEN_CNT <= p_conf->scenario) || (0 > p_conf->scenario)) { SMIERR("Incorrect SMI BWC config : 0x%x, how could this be...\n" , p_conf->scenario); return -1; } //Debug - S //SMIMSG("SMI setTo%d,%s,%d\n" , p_conf->scenario , (p_conf->b_on_off ? "on" : "off") , ePreviousFinalScen); //Debug - E spin_lock(&g_SMIInfo.SMI_lock); if(p_conf->b_on_off) { //turn on certain scenario g_SMIInfo.pu4ConcurrencyTable[p_conf->scenario] += 1; if(NULL != pu4LocalCnt) { pu4LocalCnt[p_conf->scenario] += 1; } } else { //turn off certain scenario if(0 == g_SMIInfo.pu4ConcurrencyTable[p_conf->scenario]) { SMIMSG("Too many turning off for global SMI profile:%d,%d\n" , p_conf->scenario , g_SMIInfo.pu4ConcurrencyTable[p_conf->scenario]); } else { g_SMIInfo.pu4ConcurrencyTable[p_conf->scenario] -= 1; } if(NULL != pu4LocalCnt) { if(0 == pu4LocalCnt[p_conf->scenario]) { SMIMSG("Process : %s did too many turning off for local SMI profile:%d,%d\n" , current->comm ,p_conf->scenario , pu4LocalCnt[p_conf->scenario]); } else { pu4LocalCnt[p_conf->scenario] -= 1; } } } for(i=0 ; i < SMI_BWC_SCEN_CNT ; i++) { if(g_SMIInfo.pu4ConcurrencyTable[i]) { u4Concurrency |= (1 << i); } } if((1 << SMI_BWC_SCEN_VR) & u4Concurrency) { eFinalScen = SMI_BWC_SCEN_VR; } else if((1 << SMI_BWC_SCEN_VP) & u4Concurrency) { eFinalScen = SMI_BWC_SCEN_VP; } else { eFinalScen = SMI_BWC_SCEN_NORMAL; } if(ePreviousFinalScen == eFinalScen) { SMIMSG("Scen equal%d,don't change\n" , eFinalScen); spin_unlock(&g_SMIInfo.SMI_lock); return 0; } else { ePreviousFinalScen = eFinalScen; } /*turn on larb clock*/ for( i=0 ; i < SMI_LARB_NR ; i++){ larb_clock_on(i); } /*Bandwidth Limiter*/ switch( eFinalScen ) { case SMI_BWC_SCEN_VP: SMIMSG( "[SMI_PROFILE] : %s\n", "SMI_BWC_VP"); #if 1 M4U_WriteReg32(REG_SMI_M4U_TH , 0 , ((0x2 << 15) + (0x3 << 10) + (0x4 << 5) + 0x5));// 2 non-ultra write, 3 write command , 4 non-ultra read , 5 ultra read M4U_WriteReg32(REG_SMI_L1LEN , 0 , 0xB);//Level 1 LARB, apply new outstanding control method, 1/4 bandwidth limiter overshoot control , enable warb channel M4U_WriteReg32(REG_SMI_READ_FIFO_TH , 0 , 0xC8F);//total 8 commnads between smi common to M4U, 12 non ultra commands between smi common to M4U, 1 commnads can in write AXI slice for all LARBs M4U_WriteReg32(REG_SMI_L1ARB0 , 0 , 0xC57);//1111/4096 maximum grant counts, soft limiter M4U_WriteReg32(REG_SMI_L1ARB1 , 0 , 0x9F7);//503/4096 maximum grant counts, soft limiter M4U_WriteReg32(REG_SMI_L1ARB2 , 0 , 0x961);//353/4096 maximum grant counts, soft limiter M4U_WriteReg32(REG_SMI_L1ARB3 , 0 , 0x885A25);//549/4096 maximum grant counts, hard limiter, 2 read 2 write outstanding limit M4U_WriteReg32(LARB0_BASE , 0x200 , 0x8);//OVL M4U_WriteReg32(LARB0_BASE , 0x204 , 0x8);//RDMA M4U_WriteReg32(LARB0_BASE , 0x208 , 0x3);//WDMA M4U_WriteReg32(LARB0_BASE , 0x20C , 0x1);//CMDQ M4U_WriteReg32(LARB0_BASE , 0x210 , 0x2);//MDP_RDMA M4U_WriteReg32(LARB0_BASE , 0x214 , 0x1);//MDP_WDMA M4U_WriteReg32(LARB0_BASE , 0x218 , 0x4);//MDP_ROTO M4U_WriteReg32(LARB0_BASE , 0x21C , 0x2);//MDP_ROTCO M4U_WriteReg32(LARB0_BASE , 0x220 , 0x2);//MDP_ROTVO M4U_WriteReg32(LARB1_BASE , 0x200 , 0x6);//MC M4U_WriteReg32(LARB1_BASE , 0x204 , 0x2);//PP M4U_WriteReg32(LARB1_BASE , 0x208 , 0x1);//AVC MV M4U_WriteReg32(LARB1_BASE , 0x20C , 0x3);//RD M4U_WriteReg32(LARB1_BASE , 0x210 , 0x3);//WR M4U_WriteReg32(LARB1_BASE , 0x214 , 0x1);//VLD M4U_WriteReg32(LARB1_BASE , 0x218 , 0x1);//PPWRAP M4U_WriteReg32(LARB2_BASE , 0x200 , 0x1);//IMGO M4U_WriteReg32(LARB2_BASE , 0x204 , 0x1);//IMG2O M4U_WriteReg32(LARB2_BASE , 0x208 , 0x1);//LSCI M4U_WriteReg32(LARB2_BASE , 0x20C , 0x1);//IMGI M4U_WriteReg32(LARB2_BASE , 0x210 , 0x1);//ESFKO M4U_WriteReg32(LARB2_BASE , 0x214 , 0x1);//AAO M4U_WriteReg32(LARB2_BASE , 0x218 , 0x1);//JPG_RDMA M4U_WriteReg32(LARB2_BASE , 0x21C , 0x1);//JPG_BSDMA M4U_WriteReg32(LARB2_BASE , 0x220 , 0x2);//VENC_RD_COMV M4U_WriteReg32(LARB2_BASE , 0x224 , 0x1);//VENC_SV_COMV M4U_WriteReg32(LARB2_BASE , 0x228 , 0x4);//VENC_RCPU M4U_WriteReg32(LARB2_BASE , 0x22C , 0x2);//VENC_REC_FRM M4U_WriteReg32(LARB2_BASE , 0x230 , 0x2);//VENC_REF_LUMA M4U_WriteReg32(LARB2_BASE , 0x234 , 0x1);//VENC_REF_CHROMA M4U_WriteReg32(LARB2_BASE , 0x238 , 0x1);//VENC_BSDMA M4U_WriteReg32(LARB2_BASE , 0x23C , 0x1);//VENC_CUR_LUMA M4U_WriteReg32(LARB2_BASE , 0x240 , 0x1);//VENC_CUR_CHROMA #endif break; case SMI_BWC_SCEN_VR: SMIMSG( "[SMI_PROFILE] : %s\n", "SMI_BWC_VR"); #if 1 M4U_WriteReg32(REG_SMI_M4U_TH , 0 , ((0x2 << 15) + (0x3 << 10) + (0x4 << 5) + 0x5));// 2 non-ultra write, 3 write command , 4 non-ultra read , 5 ultra read M4U_WriteReg32(REG_SMI_L1LEN , 0 , 0xB);//Level 1 LARB, apply new outstanding control method, 1/4 bandwidth limiter overshoot control , enable warb channel M4U_WriteReg32(REG_SMI_READ_FIFO_TH , 0 , 0xC8F);//total 8 commnads between smi common to M4U, 12 non ultra commands between smi common to M4U, 1 commnads can in write AXI slice for all LARBs M4U_WriteReg32(REG_SMI_L1ARB0 , 0 , 0xC57);//1111/4096 maximum grant counts, soft limiter M4U_WriteReg32(REG_SMI_L1ARB1 , 0 , 0x9F7);//503/4096 maximum grant counts, soft limiter M4U_WriteReg32(REG_SMI_L1ARB2 , 0 , 0xD4F);//1359/4096 maximum grant counts, soft limiter M4U_WriteReg32(REG_SMI_L1ARB3 , 0 , 0x884912);// 274/4096 maximum grant counts, soft limiter, 2 read 2 write outstanding limit M4U_WriteReg32(LARB0_BASE , 0x200 , 0x8);//OVL M4U_WriteReg32(LARB0_BASE , 0x204 , 0x8);//RDMA M4U_WriteReg32(LARB0_BASE , 0x208 , 0x1);//WDMA M4U_WriteReg32(LARB0_BASE , 0x20C , 0x1);//CMDQ M4U_WriteReg32(LARB0_BASE , 0x210 , 0x2);//MDP_RDMA M4U_WriteReg32(LARB0_BASE , 0x214 , 0x2);//MDP_WDMA M4U_WriteReg32(LARB0_BASE , 0x218 , 0x2);//MDP_ROTO M4U_WriteReg32(LARB0_BASE , 0x21C , 0x4);//MDP_ROTCO M4U_WriteReg32(LARB0_BASE , 0x220 , 0x1);//MDP_ROTVO M4U_WriteReg32(LARB1_BASE , 0x200 , 0x1);//MC M4U_WriteReg32(LARB1_BASE , 0x204 , 0x1);//PP M4U_WriteReg32(LARB1_BASE , 0x208 , 0x1);//AVC MV M4U_WriteReg32(LARB1_BASE , 0x20C , 0x1);//RD M4U_WriteReg32(LARB1_BASE , 0x210 , 0x1);//WR M4U_WriteReg32(LARB1_BASE , 0x214 , 0x1);//VLD M4U_WriteReg32(LARB1_BASE , 0x218 , 0x1);//PPWRAP M4U_WriteReg32(LARB2_BASE , 0x200 , 0x6);//IMGO M4U_WriteReg32(LARB2_BASE , 0x204 , 0x1);//IMG2O M4U_WriteReg32(LARB2_BASE , 0x208 , 0x1);//LSCI M4U_WriteReg32(LARB2_BASE , 0x20C , 0x4);//IMGI M4U_WriteReg32(LARB2_BASE , 0x210 , 0x1);//ESFKO M4U_WriteReg32(LARB2_BASE , 0x214 , 0x1);//AAO M4U_WriteReg32(LARB2_BASE , 0x218 , 0x1);//JPG_RDMA M4U_WriteReg32(LARB2_BASE , 0x21C , 0x1);//JPG_BSDMA M4U_WriteReg32(LARB2_BASE , 0x220 , 0x1);//VENC_RD_COMV M4U_WriteReg32(LARB2_BASE , 0x224 , 0x1);//VENC_SV_COMV M4U_WriteReg32(LARB2_BASE , 0x228 , 0x1);//VENC_RCPU M4U_WriteReg32(LARB2_BASE , 0x22C , 0x2);//VENC_REC_FRM M4U_WriteReg32(LARB2_BASE , 0x230 , 0x4);//VENC_REF_LUMA M4U_WriteReg32(LARB2_BASE , 0x234 , 0x2);//VENC_REF_CHROMA M4U_WriteReg32(LARB2_BASE , 0x238 , 0x1);//VENC_BSDMA M4U_WriteReg32(LARB2_BASE , 0x23C , 0x2);//VENC_CUR_LUMA M4U_WriteReg32(LARB2_BASE , 0x240 , 0x1);//VENC_CUR_CHROMA #endif break; case SMI_BWC_SCEN_NORMAL: SMIMSG( "[SMI_PROFILE] : %s\n", "SMI_BWC_SCEN_NORMAL"); initSetting(); default: break; } /*turn off larb clock*/ for(i = 0 ; i < SMI_LARB_NR ; i++){ larb_clock_off(i); } spin_unlock(&g_SMIInfo.SMI_lock); SMIMSG("ScenTo:%d,turn %s,Curr Scen:%d,%d,%d,%d\n" , p_conf->scenario , (p_conf->b_on_off ? "on" : "off") , eFinalScen , g_SMIInfo.pu4ConcurrencyTable[SMI_BWC_SCEN_NORMAL] , g_SMIInfo.pu4ConcurrencyTable[SMI_BWC_SCEN_VR] , g_SMIInfo.pu4ConcurrencyTable[SMI_BWC_SCEN_VP]); //Debug usage - S //smi_dumpDebugMsg(); //SMIMSG("Config:%d,%d,%d\n" , eFinalScen , g_SMIInfo.pu4ConcurrencyTable[SMI_BWC_SCEN_NORMAL] , (NULL == pu4LocalCnt ? (-1) : pu4LocalCnt[p_conf->scenario])); //Debug usage - E return 0; }
static long smi_ioctl( struct file * pFile, unsigned int cmd, unsigned long param) { int ret = 0; // unsigned long * pu4Cnt = (unsigned long *)pFile->private_data; switch (cmd) { #ifdef __MAU_SPC_ENABLE__ case MTK_CONFIG_MM_MAU: { MTK_MAU_CONFIG b; if(copy_from_user(&b, (void __user *)param, sizeof(b))) { SMIERR("copy_from_user failed!"); ret = -EFAULT; } else { mau_config(&b); } return ret; } case MTK_IOC_SPC_CONFIG : { MTK_SPC_CONFIG cfg; ret = copy_from_user(&cfg, (void*)param , sizeof(MTK_SPC_CONFIG)); if(ret) { SMIMSG(" SPC_CONFIG, copy_from_user failed: %d\n", ret); return -EFAULT; } spc_config(&cfg); } break; case MTK_IOC_SPC_DUMP_REG : spc_dump_reg(); break; case MTK_IOC_SPC_DUMP_STA : spc_status_check(); break; case MTK_IOC_SPC_CMD : spc_test(param); break; #endif case MTK_IOC_SMI_BWC_CONFIG: { MTK_SMI_BWC_CONFIG cfg; ret = copy_from_user(&cfg, (void*)param , sizeof(MTK_SMI_BWC_CONFIG)); if(ret) { SMIMSG(" SMI_BWC_CONFIG, copy_from_user failed: %d\n", ret); return -EFAULT; } // ret = smi_bwc_config( &cfg , pu4Cnt); ret = smi_bwc_config( &cfg , NULL); } break; default: return -1; } return ret; }
int larb_reg_restore(int larb) { unsigned int regval,regval1,regval2; unsigned int larb_base = gLarbBaseAddr[larb]; /* unsigned int* pReg = pLarbRegBackUp[larb]; int i; //warning: larb_con is controlled by set/clr regval = *(pReg++); M4U_WriteReg32(larb_base, SMI_LARB_CON_CLR, ~(regval)); M4U_WriteReg32(larb_base, SMI_LARB_CON_SET, (regval)); M4U_WriteReg32(larb_base, SMI_SHARE_EN, *(pReg++) ); M4U_WriteReg32(larb_base, SMI_ROUTE_SEL, *(pReg++) ); for(i=0; i<3; i++) { M4U_WriteReg32(larb_base, SMI_MAU_ENTR_START(i), *(pReg++)); M4U_WriteReg32(larb_base, SMI_MAU_ENTR_END(i), *(pReg++)); M4U_WriteReg32(larb_base, SMI_MAU_ENTR_GID(i), *(pReg++)); } */ //Clock manager enable LARB clock before call back restore already, it will be disabled after restore call back returns //Got to enable OSTD before engine starts regval = M4U_ReadReg32(larb_base , SMI_LARB_STAT); regval1 = M4U_ReadReg32(larb_base , SMI_LARB_MON_BUS_REQ0); regval2 = M4U_ReadReg32(larb_base , SMI_LARB_MON_BUS_REQ1); if(0 == regval) { int retry_count = 0; SMIMSG("Init OSTD for larb_base: 0x%x\n" , larb_base); // Write 0x60 = 0xFFFF_FFFF, enable BW limiter M4U_WriteReg32(larb_base , 0x60 , 0xffffffff); // Polling 0x600 = 0xaaaa for(retry_count= 0; retry_count<64; retry_count++) { if(M4U_ReadReg32(larb_base , 0x600) == 0xaaaa) { //Step3. Once it is found 0x600 == 0xaaaa, we can start to enable outstanding limiter and set outstanding limit break; } SMIMSG("Larb: 0x%x busy : waiting for idle\n" , larb_base); udelay(500); } // Write 0x60 = 0x0, disable BW limiter M4U_WriteReg32(larb_base , 0x60 , 0x0); // enable ISTD M4U_WriteReg32(larb_base , SMI_LARB_OSTD_CTRL_EN , 0xffffffff); } else { SMIMSG("Larb%d is busy : 0x%x , port:0x%x,0x%x ,fail to set OSTD\n" , larb , regval , regval1 , regval2); smi_dumpDebugMsg(); SMIERR("DISP_MDP LARB%d OSTD cannot be set:0x%x,port:0x%x,0x%x\n" , larb , regval , regval1 , regval2); } if(0 == g_bInited) { initSetting(); g_bInited = 1; SMIMSG("SMI init\n"); } // Show SMI always on register when larb 0 is enable if(larb == 0){ SMIMSG("===SMI always on reg dump===\n"); SMIMSG("[0x5C0,0x5C4,0x5C8]=[0x%x,0x%x,0x%x]\n" ,M4U_ReadReg32(SMI_COMMON_AO_BASE , 0x5C0),M4U_ReadReg32(SMI_COMMON_AO_BASE , 0x5C4),M4U_ReadReg32(SMI_COMMON_AO_BASE , 0x5C8)); SMIMSG("[0x5CC,0x5D0]=[0x%x,0x%x]\n" ,M4U_ReadReg32(SMI_COMMON_AO_BASE , 0x5CC),M4U_ReadReg32(SMI_COMMON_AO_BASE , 0x5D0)); } return 0; }