/**
* @brief SPC56ELxx early initialization.
* @note All the involved constants come from the file @p board.h and
* @p hal_lld.h
* @note This function must be invoked only after the system reset.
*
* @special
*/
void spc_clock_init(void) {
/* Waiting for IRC stabilization before attempting anything else.*/
while (!MC_ME.GS.B.S_IRC)
;
#if !SPC5_NO_INIT
#if SPC5_DISABLE_WATCHDOG
/* SWTs disabled.*/
SWT_0.SR.R = 0xC520;
SWT_0.SR.R = 0xD928;
SWT_0.CR.R = 0xFF000002;
SWT_1.SR.R = 0xC520;
SWT_1.SR.R = 0xD928;
SWT_1.CR.R = 0xFF000002;
SWT_2.SR.R = 0xC520;
SWT_2.SR.R = 0xD928;
SWT_2.CR.R = 0xFF000002;
SWT_3.SR.R = 0xC520;
SWT_3.SR.R = 0xD928;
SWT_3.CR.R = 0xFF000002;
#endif
/* SSCM initialization from configuration data.*/
SSCM.ERROR.R = SPC5_SSCM_ERROR_INIT;
/* RGM errors clearing.*/
MC_RGM.FES.R = 0xFFFF;
MC_RGM.DES.R = 0xFFFF;
/* The system must be in DRUN mode on entry, if this is not the case then
it is considered a serious anomaly.*/
if (MC_ME.GS.B.S_CURRENT_MODE != SPC5_RUNMODE_DRUN) {
SPC5_CLOCK_FAILURE_HOOK();
}
#if defined(SPC5_OSC_BYPASS)
/* If the board is equipped with an oscillator instead of a crystal then the
bypass must be activated.*/
XOSC.CTL.B.OSCBYP = TRUE;
#endif /* SPC5_OSC_BYPASS */
/* Setting the system dividers to their final values.*/
MC_CGM.SC_DC0.R = SPC5_CGM_SC_DC0_BITS;
MC_CGM.SC_DC1.R = SPC5_CGM_SC_DC1_BITS;
MC_CGM.SC_DC2.R = SPC5_CGM_SC_DC2_BITS;
MC_CGM.SC_DC3.R = SPC5_CGM_SC_DC3_BITS;
#if !defined(_SPC58NE84C3_CUT1_)
MC_CGM.SC_DC4.R = SPC5_CGM_SC_DC4_BITS;
#endif
/* Setting the auxiliary dividers to their final values.*/
MC_CGM.AC0_DC0.R = SPC5_CGM_AC0_DC0_BITS;
MC_CGM.AC0_DC1.R = SPC5_CGM_AC0_DC1_BITS;
MC_CGM.AC0_DC2.R = SPC5_CGM_AC0_DC2_BITS;
MC_CGM.AC0_DC3.R = SPC5_CGM_AC0_DC3_BITS;
#if defined(_SPC58NE84C3_CUT1_)
MC_CGM.AC0_DC4.R = SPC5_CGM_AC0_DC4_BITS;
#endif
MC_CGM.AC6_DC0.R = SPC5_CGM_AC6_DC0_BITS;
MC_CGM.AC7_DC0.R = SPC5_CGM_AC7_DC0_BITS;
MC_CGM.AC12_DC0.R = SPC5_CGM_AC12_DC0_BITS;
MC_CGM.AC12_DC1.R = SPC5_CGM_AC12_DC1_BITS;
MC_CGM.AC12_DC2.R = SPC5_CGM_AC12_DC2_BITS;
MC_CGM.AC12_DC3.R = SPC5_CGM_AC12_DC3_BITS;
MC_CGM.AC12_DC4.R = SPC5_CGM_AC12_DC4_BITS;
/* Setting the clock selectors to their final sources.*/
MC_CGM.AC0_SC.R = SPC5_CGM_AC0_SC_BITS;
MC_CGM.AC3_SC.R = SPC5_CGM_AC3_SC_BITS;
MC_CGM.AC4_SC.R = SPC5_CGM_AC4_SC_BITS;
MC_CGM.AC6_SC.R = SPC5_CGM_AC6_SC_BITS;
MC_CGM.AC7_SC.R = SPC5_CGM_AC7_SC_BITS;
MC_CGM.AC12_SC.R = SPC5_CGM_AC12_SC_BITS;
/* Enables the XOSC in order to check its functionality before proceeding
with the initialization.*/
MC_ME.DRUN_MC.R = SPC5_ME_MC_SYSCLK_IRC | SPC5_ME_MC_IRCON |
SPC5_ME_MC_XOSC0ON | SPC5_ME_MC_FLAON_NORMAL |
SPC5_ME_MC_MVRON;
if (halSPCSetRunMode(SPC5_RUNMODE_DRUN) == OSAL_FAILED) {
SPC5_CLOCK_FAILURE_HOOK();
}
/* PLLs initialization, the changes will have effect on mode switch.*/
PLLDIG.PLL0CR.R = 0;
PLLDIG.PLL0DV.R = SPC5_PLL0_DV_RFDPHI1(SPC5_PLL0_RFDPHI1_VALUE) |
SPC5_PLL0_DV_RFDPHI(SPC5_PLL0_RFDPHI_VALUE) |
SPC5_PLL0_DV_PREDIV(SPC5_PLL0_PREDIV_VALUE) |
SPC5_PLL0_DV_MFD(SPC5_PLL0_MFD_VALUE);
PLLDIG.PLL1CR.R = 0;
PLLDIG.PLL1DV.R = SPC5_PLL1_DV_RFDPHI(SPC5_PLL1_RFDPHI_VALUE) |
SPC5_PLL1_DV_MFD(SPC5_PLL1_MFD_VALUE);
/* Run modes initialization, note writes to the MC registers are verified
by a protection mechanism, the operation success is verified at the
end of the sequence.*/
MC_ME.IS.R = 8; /* Resetting I_ICONF status.*/
MC_ME.ME.R = SPC5_ME_ME_BITS;
MC_ME.SAFE_MC.R = SPC5_ME_SAFE_MC_BITS;
MC_ME.DRUN_MC.R = SPC5_ME_DRUN_MC_BITS;
MC_ME.RUN_MC[0].R = SPC5_ME_RUN0_MC_BITS;
MC_ME.RUN_MC[1].R = SPC5_ME_RUN1_MC_BITS;
MC_ME.RUN_MC[2].R = SPC5_ME_RUN2_MC_BITS;
MC_ME.RUN_MC[3].R = SPC5_ME_RUN3_MC_BITS;
MC_ME.HALT0_MC.R = SPC5_ME_HALT0_MC_BITS;
MC_ME.STOP0_MC.R = SPC5_ME_STOP0_MC_BITS;
if (MC_ME.IS.B.I_ICONF) {
/* Configuration rejected.*/
SPC5_CLOCK_FAILURE_HOOK();
}
/* Peripherals run and low power modes initialization.*/
MC_ME.RUN_PC[0].R = SPC5_ME_RUN_PC0_BITS;
MC_ME.RUN_PC[1].R = SPC5_ME_RUN_PC1_BITS;
MC_ME.RUN_PC[2].R = SPC5_ME_RUN_PC2_BITS;
MC_ME.RUN_PC[3].R = SPC5_ME_RUN_PC3_BITS;
MC_ME.RUN_PC[4].R = SPC5_ME_RUN_PC4_BITS;
MC_ME.RUN_PC[5].R = SPC5_ME_RUN_PC5_BITS;
MC_ME.RUN_PC[6].R = SPC5_ME_RUN_PC6_BITS;
MC_ME.RUN_PC[7].R = SPC5_ME_RUN_PC7_BITS;
MC_ME.LP_PC[0].R = SPC5_ME_LP_PC0_BITS;
MC_ME.LP_PC[1].R = SPC5_ME_LP_PC1_BITS;
MC_ME.LP_PC[2].R = SPC5_ME_LP_PC2_BITS;
MC_ME.LP_PC[3].R = SPC5_ME_LP_PC3_BITS;
MC_ME.LP_PC[4].R = SPC5_ME_LP_PC4_BITS;
MC_ME.LP_PC[5].R = SPC5_ME_LP_PC5_BITS;
MC_ME.LP_PC[6].R = SPC5_ME_LP_PC6_BITS;
MC_ME.LP_PC[7].R = SPC5_ME_LP_PC7_BITS;
/* TODO: PFLASH settings initialized for a maximum clock of 200MHz.*/
/* PFLASH.PFCR0.B.B02_APC = 3;
PFLASH.PFCR0.B.B02_WWSC = 3;
PFLASH.PFCR0.B.B02_RWSC = 3;*/
/* Switches again to DRUN mode (current mode) in order to update the
settings.*/
if (halSPCSetRunMode(SPC5_RUNMODE_DRUN) == OSAL_FAILED) {
SPC5_CLOCK_FAILURE_HOOK();
}
#endif /* !SPC5_NO_INIT */
}
/**
* @brief SPC56ELxx early initialization.
* @note All the involved constants come from the file @p board.h and
* @p hal_lld.h
* @note This function must be invoked only after the system reset.
*
* @special
*/
void spc_clock_init(void) {
/* Waiting for IRC stabilization before attempting anything else.*/
while (!MC_ME.GS.B.S_IRC)
;
#if !SPC5_NO_INIT
#if SPC5_HSM_HANDSHAKE == 1
/* Waits until the HSM notifies it is ready to accept a clock change.*/
while (HSM2HTF != 1)
;
/* Notifies the HSM an acknowledge.*/
HT2HSMF = 1;
#endif
#if SPC5_HSM_HANDSHAKE == 2
/* This protocol does not ensure the Z4 will wait for HSM prescaler will be
* set before changing clock settings --> We may overclock the HSM.
*
* But there are waiting loops that ensure that HSM will have time to
* set it on time. The rationale is that with this protocol, priority
* is given to application core. If the HSM did not start, the goal is
* to not lock the full platfrom.
*/
{
uint32_t counter = 0;
/* If set, clear bit telling that HSML started, may speed up
the HSM startup process.*/
if ((HSM2HTF & WF_GO) == WF_GO)
HSM2HTF = WF_GO;
/* Wait for HSM notification that it changed its prescaler divider and
we can change PLL settings, but for a limited time (4000 loops).*/
counter = 0;
do {
if ((HSM2HTF & CLK_CHG_RDY) == CLK_CHG_RDY)
break;
counter ++;
}
while (counter < 4000);
}
#endif
#if SPC5_DISABLE_WATCHDOG
/* SWTs disabled.*/
SWT_0.SR.R = 0xC520;
SWT_0.SR.R = 0xD928;
SWT_0.CR.R = 0xFF000002;
SWT_1.SR.R = 0xC520;
SWT_1.SR.R = 0xD928;
SWT_1.CR.R = 0xFF000002;
SWT_2.SR.R = 0xC520;
SWT_2.SR.R = 0xD928;
SWT_2.CR.R = 0xFF000002;
SWT_3.SR.R = 0xC520;
SWT_3.SR.R = 0xD928;
SWT_3.CR.R = 0xFF000002;
#endif
/* SSCM initialization from configuration data.*/
SSCM.ERROR.R = SPC5_SSCM_ERROR_INIT;
/* RGM errors clearing.*/
MC_RGM.FES.R = 0xFFFF;
MC_RGM.DES.R = 0xFFFF;
/* The system must be in DRUN mode on entry, if this is not the case then
it is considered a serious anomaly.*/
if (MC_ME.GS.B.S_CURRENT_MODE != SPC5_RUNMODE_DRUN) {
SPC5_CLOCK_FAILURE_HOOK();
}
#if defined(SPC5_OSC_BYPASS)
/* If the board is equipped with an oscillator instead of a crystal then the
bypass must be activated.*/
XOSC.CTL.B.OSCBYP = TRUE;
#endif /* SPC5_OSC_BYPASS */
/* Setting the system dividers to their final values.*/
MC_CGM.SC_DC0.R = SPC5_CGM_SC_DC0_BITS;
MC_CGM.SC_DC1.R = SPC5_CGM_SC_DC1_BITS;
MC_CGM.SC_DC2.R = SPC5_CGM_SC_DC2_BITS;
MC_CGM.SC_DC3.R = SPC5_CGM_SC_DC3_BITS;
/* Setting the auxiliary dividers to their final values.*/
MC_CGM.AC0_DC0.R = SPC5_CGM_AC0_DC0_BITS;
MC_CGM.AC0_DC1.R = SPC5_CGM_AC0_DC1_BITS;
MC_CGM.AC0_DC2.R = SPC5_CGM_AC0_DC2_BITS;
MC_CGM.AC0_DC3.R = SPC5_CGM_AC0_DC3_BITS;
MC_CGM.AC0_DC4.R = SPC5_CGM_AC0_DC4_BITS;
MC_CGM.AC6_DC0.R = SPC5_CGM_AC6_DC0_BITS;
MC_CGM.AC7_DC0.R = SPC5_CGM_AC7_DC0_BITS;
MC_CGM.AC12_DC0.R = SPC5_CGM_AC12_DC0_BITS;
MC_CGM.AC12_DC1.R = SPC5_CGM_AC12_DC1_BITS;
MC_CGM.AC12_DC2.R = SPC5_CGM_AC12_DC2_BITS;
MC_CGM.AC12_DC3.R = SPC5_CGM_AC12_DC3_BITS;
MC_CGM.AC12_DC4.R = SPC5_CGM_AC12_DC4_BITS;
/* Setting the clock selectors to their final sources.*/
MC_CGM.AC0_SC.R = SPC5_CGM_AC0_SC_BITS;
MC_CGM.AC3_SC.R = SPC5_CGM_AC3_SC_BITS;
MC_CGM.AC4_SC.R = SPC5_CGM_AC4_SC_BITS;
MC_CGM.AC6_SC.R = SPC5_CGM_AC6_SC_BITS;
MC_CGM.AC7_SC.R = SPC5_CGM_AC7_SC_BITS;
MC_CGM.AC12_SC.R = SPC5_CGM_AC12_SC_BITS;
/* Enables the XOSC in order to check its functionality before proceeding
with the initialization.*/
MC_ME.DRUN_MC.R = SPC5_ME_MC_SYSCLK_IRC | SPC5_ME_MC_IRCON |
SPC5_ME_MC_XOSC0ON | SPC5_ME_MC_FLAON_NORMAL |
SPC5_ME_MC_MVRON;
if (halSPCSetRunMode(SPC5_RUNMODE_DRUN) == OSAL_FAILED) {
SPC5_CLOCK_FAILURE_HOOK();
}
/* PLLs initialization, the changes will have effect on mode switch.*/
PLLDIG.PLL0CR.R = 0;
PLLDIG.PLL0DV.R = SPC5_PLL0_DV_RFDPHI1(SPC5_PLL0_RFDPHI1_VALUE) |
SPC5_PLL0_DV_RFDPHI(SPC5_PLL0_RFDPHI_VALUE) |
SPC5_PLL0_DV_PREDIV(SPC5_PLL0_PREDIV_VALUE) |
SPC5_PLL0_DV_MFD(SPC5_PLL0_MFD_VALUE);
PLLDIG.PLL1CR.R = 0;
PLLDIG.PLL1DV.R = SPC5_PLL1_DV_RFDPHI(SPC5_PLL1_RFDPHI_VALUE) |
SPC5_PLL1_DV_MFD(SPC5_PLL1_MFD_VALUE);
/* Run modes initialization, note writes to the MC registers are verified
by a protection mechanism, the operation success is verified at the
end of the sequence.*/
MC_ME.IS.R = 8; /* Resetting I_ICONF status.*/
MC_ME.ME.R = SPC5_ME_ME_BITS;
MC_ME.SAFE_MC.R = SPC5_ME_SAFE_MC_BITS;
MC_ME.DRUN_MC.R = SPC5_ME_DRUN_MC_BITS;
MC_ME.RUN0_MC.R = SPC5_ME_RUN0_MC_BITS;
MC_ME.RUN1_MC.R = SPC5_ME_RUN1_MC_BITS;
MC_ME.RUN2_MC.R = SPC5_ME_RUN2_MC_BITS;
MC_ME.RUN3_MC.R = SPC5_ME_RUN3_MC_BITS;
MC_ME.HALT0_MC.R = SPC5_ME_HALT0_MC_BITS;
MC_ME.STOP0_MC.R = SPC5_ME_STOP0_MC_BITS;
if (MC_ME.IS.B.I_ICONF) {
/* Configuration rejected.*/
SPC5_CLOCK_FAILURE_HOOK();
}
/* Peripherals run and low power modes initialization.*/
MC_ME.RUN_PC[0].R = SPC5_ME_RUN_PC0_BITS;
MC_ME.RUN_PC[1].R = SPC5_ME_RUN_PC1_BITS;
MC_ME.RUN_PC[2].R = SPC5_ME_RUN_PC2_BITS;
MC_ME.RUN_PC[3].R = SPC5_ME_RUN_PC3_BITS;
MC_ME.RUN_PC[4].R = SPC5_ME_RUN_PC4_BITS;
MC_ME.RUN_PC[5].R = SPC5_ME_RUN_PC5_BITS;
MC_ME.RUN_PC[6].R = SPC5_ME_RUN_PC6_BITS;
MC_ME.RUN_PC[7].R = SPC5_ME_RUN_PC7_BITS;
MC_ME.LP_PC[0].R = SPC5_ME_LP_PC0_BITS;
MC_ME.LP_PC[1].R = SPC5_ME_LP_PC1_BITS;
MC_ME.LP_PC[2].R = SPC5_ME_LP_PC2_BITS;
MC_ME.LP_PC[3].R = SPC5_ME_LP_PC3_BITS;
MC_ME.LP_PC[4].R = SPC5_ME_LP_PC4_BITS;
MC_ME.LP_PC[5].R = SPC5_ME_LP_PC5_BITS;
MC_ME.LP_PC[6].R = SPC5_ME_LP_PC6_BITS;
MC_ME.LP_PC[7].R = SPC5_ME_LP_PC7_BITS;
/* TODO: PFLASH settings initialized for a maximum clock of 200MHz.*/
/* PFLASH.PFCR0.B.B02_APC = 3;
PFLASH.PFCR0.B.B02_WWSC = 3;
PFLASH.PFCR0.B.B02_RWSC = 3;*/
/* Switches again to DRUN mode (current mode) in order to update the
settings.*/
if (halSPCSetRunMode(SPC5_RUNMODE_DRUN) == OSAL_FAILED) {
SPC5_CLOCK_FAILURE_HOOK();
}
#endif /* !SPC5_NO_INIT */
}