示例#1
0
/*********************************************************
* Name: SPI_Init
* Desc: Initialize SPI2 Module
* Parameter: None
* Return: None             
**********************************************************/
void SPI_Init(void)
{
    /*Body*/
    /* set PORTE pin 1 to DSPI1.SOUT*/
#ifdef MCU_MK70F12
    PORTE_PCR1 =  PORT_PCR_MUX(7);
#else
    PORTE_PCR1 =  PORT_PCR_MUX(2);
#endif // MCU_MK70F12
    /* set PORTE pin 2 to DSPI1.SCK*/
    PORTE_PCR2 =  PORT_PCR_MUX(2);
    /* set PORTE pin 3 to DSPI1.SIN*/
#ifdef MCU_MK70F12
    PORTE_PCR3 =  PORT_PCR_MUX(7);
#else
    PORTE_PCR3 =  PORT_PCR_MUX(2);
#endif // MCU_MK70F12
    /* set PORTE pin 4 to DSPI1.CS0*/
    PORTE_PCR4 =  PORT_PCR_MUX(2);    
    
    SIM_SCGC5 |= SIM_SCGC5_PORTE_MASK;
    /* Enable clock gate to DSPI1 module */
#ifdef MCU_MK70F12
    SIM_SCGC6 |= SIM_SCGC6_DSPI1_MASK;
#else
    SIM_SCGC6 |= SIM_SCGC6_SPI1_MASK;
#endif // MCU_MK70F12
    
    /* Enable master mode, disable both transmit and receive FIFO buffers, 
    set the inactive state for PCS2 high, enable the module (MDIS = 0), 
   delay the sample point from the leading edge of the clock and halt 
   any transfer
    */
    SPI1_MCR = (SPI_MCR_MSTR_MASK   | 
                SPI_MCR_PCSIS(1)    | 
                SPI_MCR_SMPL_PT(2)  |
                SPI_MCR_HALT_MASK); 
  
    SPI1_MCR |= (SPI_MCR_CLR_RXF_MASK | SPI_MCR_CLR_TXF_MASK);
    // K60: bus clock: 48MHz, DSPI clock: ~107 KHz
    // K70: bus clock: 60MHz, DSPI clock: ~156 KHz
    /* Value to be passed in SPI_Send_byte() function to DPI_CTAR0 register */
#ifdef MCU_MK70F12
    gSPI_BaudRate = (SPI_CTAR_PBR(1) | SPI_CTAR_BR(0x07));
#else
    gSPI_BaudRate = (SPI_CTAR_PBR(3) | SPI_CTAR_BR(0x06));
#endif 
    /* Configure the rest of the delays */
    gSPI_BeforeTransfDelay = (SPI_CTAR_CSSCK(1) | SPI_CTAR_CSSCK(0x04));
    gSPI_AfterTransfDelay  = (SPI_CTAR_PASC(3) | SPI_CTAR_ASC(0x04));
    gSPI_InterTransfDelay  = (SPI_CTAR_PDT(3)  | SPI_CTAR_DT(0x05));  
}/*EndBody*/
示例#2
0
/*********************************************************
* Name: SPI_High_rate
* Desc: Change SPI baud rate to high speed
* Parameter: None
* Return: None
**********************************************************/
void SPI_High_rate(void)
{
    /*Body*/
    /* DSPI clock 6 MHz */
    /* The system clock fsys = 68 MHz */
    /* Value to be passed in SPI_Send_byte() function to DPI_CTAR0 register */
    gSPI_BaudRate = (SPI_CTAR_PBR(1) | SPI_CTAR_BR(0x01)); 
        
    /* Configure the rest of the delays */
    gSPI_BeforeTransfDelay = (SPI_CTAR_CSSCK(1)  | SPI_CTAR_CSSCK(0x02));
    gSPI_AfterTransfDelay  = (SPI_CTAR_PASC(1) | SPI_CTAR_ASC(0x02));
    gSPI_InterTransfDelay  = (SPI_CTAR_PDT(1)  | SPI_CTAR_DT(0x01));  
}/*EndBody*/   
示例#3
0
BOOL SPI_Init ( SPI_Type *SPIx, INT32U baud )
{
	SPIx->MCR	 = (SPI_MCR_CLR_RXF_MASK|
					SPI_MCR_CLR_TXF_MASK|
					SPI_MCR_PCSIS_MASK	|
					SPI_MCR_HALT_MASK	);	
	SPIx->MCR	|= 	SPI_MCR_MSTR_MASK;
	
	SPIx->CTAR[0] = (//SPI_CTAR_DBR_MASK	|
					SPI_CTAR_BR(7)		|
					SPI_CTAR_FMSZ(7)	|
					SPI_CTAR_CSSCK(4)	|
					SPI_CTAR_ASC(4)		|
					SPI_CTAR_DT(6)		|
					SPI_CTAR_PDT_MASK	//|
// 					SPI_CTAR_CPOL_MASK	|
// 					SPI_CTAR_CPHA_MASK	
					);
						
	SPIx->SR	    |= (SPI_SR_EOQF_MASK	|
					SPI_SR_TFFF_MASK	|
					SPI_SR_TFUF_MASK	|
					SPI_SR_RFDF_MASK	|
					SPI_SR_RFOF_MASK	);

	SPIx->MCR	&=  ~SPI_MCR_HALT_MASK;
	return (TRUE);
}
示例#4
0
/*FUNCTION****************************************************************
* 
* Function Name    : _dspi_find_baudrate
* Returned Value   : uint_8 divider register setting
* Comments         :
*    Find closest setting of divider register for given baudrate.
*
*END*********************************************************************/
static uint_32 _dspi_find_baudrate 
    (
        /* [IN] Module input clock in Hz */
        uint_32 clock, 
        
        /* [IN] Desired baudrate in Hz */
        uint_32 baudrate
    ) 
{
    uint_32 pres, scaler, min, minpres, minscaler;
    int_32  val;
    
    min = (uint_32)-1;
    for (pres = 0; pres < 4; pres++) 
    {
        for (scaler = 0; scaler < 16; scaler++) 
        {
            val = BAUDRATE_PRESCALER[pres] * BAUDRATE_SCALER[scaler] * baudrate - clock;
            if (val < 0) val = -val;
            if (min > val) 
            {
                min = val;
                minpres = pres;
                minscaler = scaler;
            }
        }
    }
    return SPI_CTAR_PBR(minpres) | SPI_CTAR_BR(minscaler) | SPI_CTAR_CSSCK(1) | SPI_CTAR_PCSSCK(1);
}
示例#5
0
inline void SPI_setup()
{
	// Enable SPI internal clock
	SIM_SCGC6 |= SIM_SCGC6_SPI0;

	// Setup MOSI (SOUT) and SCLK (SCK)
	PORTC_PCR6 = PORT_PCR_DSE | PORT_PCR_MUX(2);
	PORTC_PCR5 = PORT_PCR_DSE | PORT_PCR_MUX(2);

	// Setup SS (PCS)
	PORTC_PCR4 = PORT_PCR_DSE | PORT_PCR_MUX(2);

	// Master Mode, CS0
	SPI0_MCR = SPI_MCR_MSTR | SPI_MCR_PCSIS(1);

	// DSPI Clock and Transfer Attributes
	// Frame Size: 8 bits
	// MSB First
	// CLK Low by default
	SPI0_CTAR0 = SPI_CTAR_FMSZ(7)
		| SPI_CTAR_ASC(7)
		| SPI_CTAR_DT(7)
		| SPI_CTAR_CSSCK(7)
		| SPI_CTAR_PBR(0) | SPI_CTAR_BR(7);
}
示例#6
0
//------------------------------------------------------------------------------
// initialize SPI pins
void SpiFlash::begin(uint8_t _SS, uint8_t sckDivisor) {
	SS = _SS;
	pinMode(SS, OUTPUT);
	digitalWriteFast(SS, HIGH);
	
	SIM_SCGC6 |= SIM_SCGC6_SPI0;

	uint32_t ctar, ctar0, ctar1;

	if (sckDivisor <= 2) {
		// 1/2 speed
		ctar = SPI_CTAR_DBR | SPI_CTAR_BR(0) | SPI_CTAR_CSSCK(0);
	} else if (sckDivisor <= 4) {
		// 1/4 speed
		ctar = SPI_CTAR_BR(0) | SPI_CTAR_CSSCK(0);
	} else if (sckDivisor <= 8) {
		// 1/8 speed
		ctar = SPI_CTAR_BR(1) | SPI_CTAR_CSSCK(1);
	} else if (sckDivisor <= 12) {
		// 1/12 speed
		ctar = SPI_CTAR_BR(2) | SPI_CTAR_CSSCK(2);
	} else if (sckDivisor <= 16) {
		// 1/16 speed
		ctar = SPI_CTAR_BR(3) | SPI_CTAR_CSSCK(3);
	} else if (sckDivisor <= 32) {
		// 1/32 speed
		ctar = SPI_CTAR_PBR(1) | SPI_CTAR_BR(4) | SPI_CTAR_CSSCK(4);
	} else if (sckDivisor <= 64) {
		// 1/64 speed
		ctar = SPI_CTAR_PBR(1) | SPI_CTAR_BR(5) | SPI_CTAR_CSSCK(5);
	} else {
		// 1/128 speed
		ctar = SPI_CTAR_PBR(1) | SPI_CTAR_BR(6) | SPI_CTAR_CSSCK(6);
	}
	// CTAR0 - 8 bit transfer
	ctar0 = ctar | SPI_CTAR_FMSZ(7);

	// CTAR1 - 16 bit transfer
	ctar1 = ctar | SPI_CTAR_FMSZ(15);

	if (SPI0_CTAR0 != ctar0 || SPI0_CTAR1 != ctar1) {
		SPI0_MCR = SPI_MCR_MSTR | SPI_MCR_MDIS | SPI_MCR_HALT;
		SPI0_CTAR0 = ctar0;
		SPI0_CTAR1 = ctar1;
	}
	SPI0_MCR = SPI_MCR_MSTR;
	CORE_PIN11_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(2);
	CORE_PIN12_CONFIG = PORT_PCR_MUX(2);
	CORE_PIN13_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(2);
	
	readID();
	
	writeEnable();
}
示例#7
0
/**
 * @brief  SPI 波特率及传输控制寄存器配置
 * @param[in]  instance      芯片SPI端口
 *              @arg HW_SPI0 芯片的SPI0端口
 *              @arg HW_SPI1 芯片的SPI1端口
 *              @arg HW_SPI2 芯片的SPI2端口
 * @param[in]  ctar SPI通信通道选择
 *          		@arg HW_CTAR0  0配置寄存器
 *          		@arg HW_CTAR1  1配置寄存器
 * @param[in]  frameFormat SPI通信时的相位和极性的关系
 *         			@arg kSPI_CPOL0_CPHA0
 *         			@arg kSPI_CPOL1_CPHA0
 *         			@arg kSPI_CPOL0_CPHA1
 *         			@arg kSPI_CPOL1_CPHA1
 * \param[in]  dataSize 数据大小
 * \param[in]  bitOrder LSB First
 *  						\arg 0 Data is transferred MSB first
 * 							\arg 1 Data is transferred LSB first
 * @param[in]  baudrate SPI通信速度设置
 * @return None
 */
void SPI_CTARConfig(uint32_t instance, uint32_t ctar, SPI_FrameFormat_Type frameFormat, uint8_t dataSize, uint8_t bitOrder, uint32_t baudrate)
{
    SPI_Type *SPIx;
    uint32_t clock;
    
    SPIx = SPI_InstanceTable[instance];
    
    
    /* data size */
    SPIx->CTAR[ctar] &= ~SPI_CTAR_FMSZ_MASK;
    SPIx->CTAR[ctar] |= SPI_CTAR_FMSZ(dataSize-1);
    
    /* bit order */
    switch(bitOrder)
    {
        case kSPI_MSB:
            SPIx->CTAR[ctar] &= ~SPI_CTAR_LSBFE_MASK;
            break;
        case kSPI_LSB:
            SPIx->CTAR[ctar] |= SPI_CTAR_LSBFE_MASK;
            break;
        default:
            break;
    }
    
    /* frame format */
    switch(frameFormat)
    {
        case kSPI_CPOL0_CPHA0:
            SPIx->CTAR[ctar] &= ~SPI_CTAR_CPOL_MASK;
            SPIx->CTAR[ctar] &= ~SPI_CTAR_CPHA_MASK;
            break;
        case kSPI_CPOL0_CPHA1:
            SPIx->CTAR[ctar] &= ~SPI_CTAR_CPOL_MASK;
            SPIx->CTAR[ctar] |= SPI_CTAR_CPHA_MASK;
            break;   
        case kSPI_CPOL1_CPHA0:
            SPIx->CTAR[ctar] |= SPI_CTAR_CPOL_MASK;
            SPIx->CTAR[ctar] &= ~SPI_CTAR_CPHA_MASK;
            break;  
        case kSPI_CPOL1_CPHA1:
            SPIx->CTAR[ctar] |= SPI_CTAR_CPOL_MASK;
            SPIx->CTAR[ctar] |= SPI_CTAR_CPHA_MASK;  
            break;  
        default:
            break;
    }
    
    /* set SPI clock, SPI use Busclock */
    clock = GetClock(kBusClock);
    dspi_hal_set_baud(instance, ctar, baudrate, clock);
    
    /* add more CS time */
    SPIx->CTAR[ctar] |= SPI_CTAR_ASC(1)|SPI_CTAR_CSSCK(1)|SPI_CTAR_PASC(1)|SPI_CTAR_PCSSCK(1);  
}
示例#8
0
/**
  * @brief  .
  * @param  None
  * @retval None
  */
void SPI_Configuration (void)
{
	/* note:ILI初始化需在AT25芯片初始化之�?*/
	/* 开启对应时��?*/
	SIM->SCGC6 |= SIM_SCGC6_SPI1_MASK;
	SIM->SCGC5 |= SIM_SCGC5_PORTE_MASK;
	ILI_SIN_PORT->PCR[ILI_SIN_Pin] = (PORT_PCR_MUX(2) 
			|PORT_PCR_PE_MASK
			|PORT_PCR_PS_MASK);
	ILI_SOUT_PORT->PCR[ILI_SOUT_Pin] = (PORT_PCR_MUX(2)
			|PORT_PCR_PE_MASK
			|PORT_PCR_PS_MASK);
	ILI_SCK_PORT->PCR[ILI_SCK_Pin] = (PORT_PCR_MUX(2)
			|PORT_PCR_PE_MASK
			|PORT_PCR_PS_MASK);
	ILI_CS_PORT->PCR[ILI_CS_Pin] = (PORT_PCR_MUX(2)
			|PORT_PCR_PE_MASK
			|PORT_PCR_PS_MASK);
	/* 主模�?*/
	ILI_SPI->MCR  = 0 & (~SPI_MCR_MDIS_MASK) 
				|SPI_MCR_HALT_MASK
				|SPI_MCR_MSTR_MASK
				|SPI_MCR_PCSIS_MASK
				|SPI_MCR_CLR_TXF_MASK
				|SPI_MCR_CLR_RXF_MASK  
				|SPI_MCR_DIS_TXF_MASK
				|SPI_MCR_DIS_RXF_MASK
				|SPI_MCR_SMPL_PT(2);
	//�᫽�分频及波特率
	ILI_SPI->CTAR[0] = 0| SPI_CTAR_DBR_MASK	 //设置���⿡��?
						| SPI_CTAR_PCSSCK(0)
						| SPI_CTAR_PASC(0)
						| SPI_CTAR_PBR(0)
						| SPI_CTAR_CSSCK(0)
						| SPI_CTAR_ASC (0)
					| SPI_CTAR_FMSZ(8)
					| SPI_CTAR_PDT(0);
	//分频设置
	ILI_SPI->CTAR[0] |=SPI_CTAR_BR(0xc);
	//�߶钟相位、极��?
	//ILI_SPI->CTAR[0] |= SPI_CTAR_CPHA_MASK;
	//ILI_SPI->CTAR[0] |= SPI_CTAR_CPOL_MASK;
	//ILI_SPI->CTAR[0] |= SPI_CTAR_LSBFE_MASK;
	ILI_SPI->SR = SPI_SR_EOQF_MASK
		| SPI_SR_TFUF_MASK
		| SPI_SR_TFFF_MASK
		| SPI_SR_RFOF_MASK
		| SPI_SR_RFDF_MASK
		| SPI_SR_TCF_MASK;
	ILI_SPI->MCR &= ~SPI_MCR_HALT_MASK;
}
/**
 * Initialize hardware SPI
 *
 */
void SdSpi::init(uint8_t sckDivisor) {
  uint32_t ctar, ctar0, ctar1;

  if (sckDivisor <= 2) {
    // 1/2 speed
    ctar = SPI_CTAR_DBR | SPI_CTAR_BR(0) | SPI_CTAR_CSSCK(0);
  } else if (sckDivisor <= 4) {
    // 1/4 speed
    ctar = SPI_CTAR_BR(0) | SPI_CTAR_CSSCK(0);
  } else if (sckDivisor <= 8) {
    // 1/8 speed
    ctar = SPI_CTAR_BR(1) | SPI_CTAR_CSSCK(1);
  } else if (sckDivisor <= 12) {
    // 1/12 speed
    ctar = SPI_CTAR_BR(2) | SPI_CTAR_CSSCK(2);
  } else if (sckDivisor <= 16) {
    // 1/16 speed
    ctar = SPI_CTAR_BR(3) | SPI_CTAR_CSSCK(3);
  } else if (sckDivisor <= 32) {
    // 1/32 speed
    ctar = SPI_CTAR_PBR(1) | SPI_CTAR_BR(4) | SPI_CTAR_CSSCK(4);
  } else if (sckDivisor <= 64) {
    // 1/64 speed
    ctar = SPI_CTAR_PBR(1) | SPI_CTAR_BR(5) | SPI_CTAR_CSSCK(5);
  } else {
    // 1/128 speed
    ctar = SPI_CTAR_PBR(1) | SPI_CTAR_BR(6) | SPI_CTAR_CSSCK(6);
  }
  // CTAR0 - 8 bit transfer
  ctar0 = ctar | SPI_CTAR_FMSZ(7);

  // CTAR1 - 16 bit transfer
  ctar1 = ctar | SPI_CTAR_FMSZ(15);

  if (SPI0_CTAR0 != ctar0 || SPI0_CTAR1 != ctar1) {
    SPI0_MCR = SPI_MCR_MSTR | SPI_MCR_MDIS | SPI_MCR_HALT | SPI_MCR_PCSIS(0x1F);
    SPI0_CTAR0 = ctar0;
    SPI0_CTAR1 = ctar1;
  }
  SPI0_MCR = SPI_MCR_MSTR | SPI_MCR_PCSIS(0x1F);
  CORE_PIN11_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(2);
  CORE_PIN12_CONFIG = PORT_PCR_MUX(2);
  CORE_PIN13_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(2);
}
示例#10
0
/* ===================================================================*/
LDD_TDeviceData* SPI_SD_Init(LDD_TUserData *UserDataPtr)
{
  /* Allocate LDD device structure */
  SPI_SD_TDeviceDataPtr DeviceDataPrv;

  /* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
  DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC;
  DeviceDataPrv->UserData = UserDataPtr; /* Store the RTOS device structure */
  /* Interrupt vector(s) allocation */
  /* {Default RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */
  INT_SPI1__DEFAULT_RTOS_ISRPARAM = DeviceDataPrv;
  DeviceDataPrv->TxCommand = 0x80000000U; /* Initialization of current Tx command */
  DeviceDataPrv->ErrFlag = 0x00U;      /* Clear error flags */
  /* Clear the receive counters and pointer */
  DeviceDataPrv->InpRecvDataNum = 0x00U; /* Clear the counter of received characters */
  DeviceDataPrv->InpDataNumReq = 0x00U; /* Clear the counter of characters to receive by ReceiveBlock() */
  DeviceDataPrv->InpDataPtr = NULL;    /* Clear the buffer pointer for received characters */
  /* Clear the transmit counters and pointer */
  DeviceDataPrv->OutSentDataNum = 0x00U; /* Clear the counter of sent characters */
  DeviceDataPrv->OutDataNumReq = 0x00U; /* Clear the counter of characters to be send by SendBlock() */
  DeviceDataPrv->OutDataPtr = NULL;    /* Clear the buffer pointer for data to be transmitted */
  DeviceDataPrv->CurrentAttributeSet = 0U; /* Init current attribute set */
  DeviceDataPrv->SerFlag = 0x00U;      /* Reset flags */
  /* SIM_SCGC6: SPI1=1 */
  SIM_SCGC6 |= SIM_SCGC6_SPI1_MASK;
  /* Interrupt vector(s) priority setting */
  /* NVICIP27: PRI27=0x70 */
  NVICIP27 = NVIC_IP_PRI27(0x70);
  /* NVICISER0: SETENA|=0x08000000 */
  NVICISER0 |= NVIC_ISER_SETENA(0x08000000);
  /* SIM_SCGC5: PORTD=1 */
  SIM_SCGC5 |= SIM_SCGC5_PORTD_MASK;
  /* PORTD_PCR7: ISF=0,MUX=7 */
  PORTD_PCR7 = (uint32_t)((PORTD_PCR7 & (uint32_t)~(uint32_t)(
                PORT_PCR_ISF_MASK
               )) | (uint32_t)(
                PORT_PCR_MUX(0x07)
               ));
  /* PORTD_PCR6: ISF=0,MUX=7 */
  PORTD_PCR6 = (uint32_t)((PORTD_PCR6 & (uint32_t)~(uint32_t)(
                PORT_PCR_ISF_MASK
               )) | (uint32_t)(
                PORT_PCR_MUX(0x07)
               ));
  /* PORTD_PCR5: ISF=0,MUX=7 */
  PORTD_PCR5 = (uint32_t)((PORTD_PCR5 & (uint32_t)~(uint32_t)(
                PORT_PCR_ISF_MASK
               )) | (uint32_t)(
                PORT_PCR_MUX(0x07)
               ));
  /* SPI1_MCR: MSTR=0,CONT_SCKE=0,DCONF=0,FRZ=0,MTFE=0,PCSSE=0,ROOE=1,??=0,??=0,PCSIS=0,DOZE=0,MDIS=0,DIS_TXF=0,DIS_RXF=0,CLR_TXF=0,CLR_RXF=0,SMPL_PT=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,HALT=1 */
  SPI1_MCR = SPI_MCR_DCONF(0x00) |
             SPI_MCR_ROOE_MASK |
             SPI_MCR_PCSIS(0x00) |
             SPI_MCR_SMPL_PT(0x00) |
             SPI_MCR_HALT_MASK;        /* Set Configuration register */
  /* SPI1_MCR: MSTR=1,CONT_SCKE=0,DCONF=0,FRZ=0,MTFE=0,PCSSE=0,ROOE=1,??=0,??=0,PCSIS=0,DOZE=0,MDIS=0,DIS_TXF=1,DIS_RXF=1,CLR_TXF=1,CLR_RXF=1,SMPL_PT=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,HALT=1 */
  SPI1_MCR = SPI_MCR_MSTR_MASK |
             SPI_MCR_DCONF(0x00) |
             SPI_MCR_ROOE_MASK |
             SPI_MCR_PCSIS(0x00) |
             SPI_MCR_DIS_TXF_MASK |
             SPI_MCR_DIS_RXF_MASK |
             SPI_MCR_CLR_TXF_MASK |
             SPI_MCR_CLR_RXF_MASK |
             SPI_MCR_SMPL_PT(0x00) |
             SPI_MCR_HALT_MASK;        /* Set Configuration register */
  /* SPI1_CTAR0: DBR=1,FMSZ=7,CPOL=0,CPHA=0,LSBFE=0,PCSSCK=0,PASC=0,PDT=0,PBR=0,CSSCK=0,ASC=0,DT=0,BR=0 */
  SPI1_CTAR0 = SPI_CTAR_DBR_MASK |
               SPI_CTAR_FMSZ(0x07) |
               SPI_CTAR_PCSSCK(0x00) |
               SPI_CTAR_PASC(0x00) |
               SPI_CTAR_PDT(0x00) |
               SPI_CTAR_PBR(0x00) |
               SPI_CTAR_CSSCK(0x00) |
               SPI_CTAR_ASC(0x00) |
               SPI_CTAR_DT(0x00) |
               SPI_CTAR_BR(0x00);      /* Set Clock and Transfer Attributes register */
  /* SPI1_SR: TCF=1,TXRXS=0,??=0,EOQF=1,TFUF=1,??=0,TFFF=1,??=0,??=0,??=0,??=1,??=0,RFOF=1,??=0,RFDF=1,??=0,TXCTR=0,TXNXTPTR=0,RXCTR=0,POPNXTPTR=0 */
  SPI1_SR = SPI_SR_TCF_MASK |
            SPI_SR_EOQF_MASK |
            SPI_SR_TFUF_MASK |
            SPI_SR_TFFF_MASK |
            SPI_SR_RFOF_MASK |
            SPI_SR_RFDF_MASK |
            SPI_SR_TXCTR(0x00) |
            SPI_SR_TXNXTPTR(0x00) |
            SPI_SR_RXCTR(0x00) |
            SPI_SR_POPNXTPTR(0x00) |
            0x00200000U;               /* Clear flags */
  /* SPI1_RSER: TCF_RE=0,??=0,??=0,EOQF_RE=0,TFUF_RE=0,??=0,TFFF_RE=0,TFFF_DIRS=0,??=0,??=0,??=0,??=0,RFOF_RE=0,??=0,RFDF_RE=1,RFDF_DIRS=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
  SPI1_RSER = SPI_RSER_RFDF_RE_MASK;   /* Set DMA Interrupt Request Select and Enable register */
  SPI_SD_SetClockConfiguration(DeviceDataPrv, Cpu_GetClockConfiguration()); /* Set Initial according speed CPU mode */
  /* Registration of the device structure */
  PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_SPI_SD_ID,DeviceDataPrv);
  return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the data data structure */
}
示例#11
0
// initialize LCD SPI pins or hardware
void lcd_spi_init(void)
{
    INIT_OUTPUT(LCD_RESET);

    //INIT SPI
    SIM->SCGC6 |= SIM_SCGC6_SPI0_MASK;
	SPI0_MCR = SPI_MCR_MDIS_MASK | SPI_MCR_HALT_MASK | SPI_MCR_PCSIS(0x1F);
	SPI0_CTAR0 = SPI_CTAR_FMSZ(7) | SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR_MASK | SPI_CTAR_CSSCK(0);
	SPI0_CTAR1 = SPI_CTAR_FMSZ(15) | SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR_MASK | SPI_CTAR_CSSCK(0);
	SPI0_MCR = SPI_MCR_MSTR_MASK | SPI_MCR_PCSIS(0x1F);
	//SPCR.enable_pins();
     //SIM_SCGC4 |= SIM_SCGC4_SPI1_MASK;       //Enable SPI1 clock

    PORTD_PCR0 = PORT_PCR_MUX(0x2);    //Set PTD0 to mux 2 [SPI0_PCS0]
    PORTD_PCR1 = PORT_PCR_MUX(0x2);    //Set PTD1 to mux 2 [SPI0_SCK]
    PORTD_PCR2 = PORT_PCR_MUX(0x2);    //Set PTD2 to mux 2 [SPI0_MOSI]
    PORTD_PCR3 = PORT_PCR_MUX(0x2);    //Set PTD3 to mux 2 [SPI0_MISO]
    PORTD_PCR4 = PORT_PCR_MUX(0x2);    //Set PTD4 to mux 2 [SPI0_PCS1]

    //PORTC_PCR11 = PORT_PCR_MUX(0x1);   //Set PTC11 to mux 1 [GPIO]


//    while ( !(SPI0->S & SPI_S_SPTEF_MASK) )__asm__ __volatile__("nop");
}
示例#12
0
OSStatus spi_init( spi_driver_t* spi_driver, SPI_MemMapPtr spi_peripheral, uint32_t baud_rate_bps, uint8_t chip_select, bool polarity, bool phase, bool use_dma )
{
    uint8_t br = get_baud_rate_scaler_register_value( baud_rate_bps );

    spi_driver->spi_peripheral = spi_peripheral;
    spi_driver->baud_rate_bps  = baud_rate_bps;
    spi_driver->chip_select    = chip_select;
    spi_driver->polarity       = polarity;
    spi_driver->phase          = phase;
    spi_driver->use_dma        = use_dma;

    /* Enable SPI peripheral clock */
    set_spi_peripheral_clock( spi_peripheral, true );

    /* Enable SPI peripheral and clean up (stop) any previous transfer
     * MDIS     = 0 to enable
     * HALT     = 1 to stop transfer
     * MSTR     = 1 for master mode
     * DCONF    = 0 for SPI
     * PCSIS[x] = 1 for CS active low
     */
    SPI_MCR_REG( spi_peripheral ) &= ~(uint32_t) ( SPI_MCR_MDIS_MASK | SPI_MCR_DCONF(0) );
    SPI_MCR_REG( spi_peripheral ) |=  (uint32_t) ( (0x1<<24)|SPI_MCR_HALT_MASK | SPI_MCR_MSTR_MASK | SPI_MCR_PCSIS( 1 << chip_select ) );

    /* Select Clock and Transfer Attributes Register (CTAR). Always use CTAR0 */
    SPI_PUSHR_REG( spi_peripheral ) &= ~(uint32_t) SPI_PUSHR_CTAS(CTAR_REG_USED);

    /* Reset Clock and Transfer Attributes (CTAR) register */
    SPI_CTAR_REG( spi_peripheral, CTAR_REG_USED ) = 0;

    /* Set SPI configuration
     * FMSZ   = 7. Set frame size to 8-bit. frame size = FMSZ + 1
     * CPOL   = phase
     * CPHA   = polarity
     * DBR    = 00
     * PBR    = 2
     * BR     = calculate based on baud_rate_Mbps
     * PCSSCK = 0
     * PASC   = 0
     * PDT    = 0
     * CSSCK  = BR - 1
     * ASC    = BR - 1
     * DT     = 0
     */
    SPI_CTAR_REG( spi_peripheral, CTAR_REG_USED ) |= (uint32_t) ( SPI_CTAR_CPOL_MASK & (uint32_t)( polarity << SPI_CTAR_CPOL_SHIFT ) ) |
                                                     (uint32_t) ( SPI_CTAR_CPHA_MASK & (uint32_t)( phase    << SPI_CTAR_CPHA_SHIFT ) ) |
                                                     (uint32_t) ( SPI_CTAR_FMSZ( 8 - 1 ) ) |
                                                     (uint32_t) ( SPI_CTAR_DBR_MASK & ( DOUBLE_BAUD_RATE << SPI_CTAR_DBR_SHIFT ) ) |
                                                     (uint32_t) ( SPI_CTAR_PBR( CTAR_PBR ) ) |
                                                     (uint32_t) ( SPI_CTAR_BR( br ) ) |
                                                     (uint32_t) ( SPI_CTAR_CSSCK( br - 1 ) ) |
                                                     (uint32_t) ( SPI_CTAR_ASC( br - 1 ) );

    clear_spi_fifos( spi_peripheral );
        
    /* Enable the start transfer bit */
    SPI_MCR_REG( spi_peripheral ) &= ~(uint32_t) ( SPI_MCR_HALT_MASK );

	if(use_dma)
	{
		SPI_RSER_REG( spi_peripheral ) |= (0x3<<24)|(0x3<<16);
		DMA_init();
	}

    spi_status_print(spi_peripheral);
    return kNoErr;
}
示例#13
0
/* ===================================================================*/
LDD_TDeviceData* SM1_Init(LDD_TUserData *UserDataPtr)
{
    /* Allocate LDD device structure */
    SM1_TDeviceDataPtr DeviceDataPrv;

    /* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
    DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC;
    DeviceDataPrv->UserData = UserDataPtr; /* Store the RTOS device structure */
    /* Interrupt vector(s) allocation */
    /* {Default RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */
    INT_SPI0__DEFAULT_RTOS_ISRPARAM = DeviceDataPrv;
    DeviceDataPrv->TxCommand = 0x80040000U; /* Initialization of current Tx command */
    DeviceDataPrv->ErrFlag = 0x00U;      /* Clear error flags */
    /* Clear the receive counters and pointer */
    DeviceDataPrv->InpRecvDataNum = 0x00U; /* Clear the counter of received characters */
    DeviceDataPrv->InpDataNumReq = 0x00U; /* Clear the counter of characters to receive by ReceiveBlock() */
    DeviceDataPrv->InpDataPtr = NULL;    /* Clear the buffer pointer for received characters */
    /* Clear the transmit counters and pointer */
    DeviceDataPrv->OutSentDataNum = 0x00U; /* Clear the counter of sent characters */
    DeviceDataPrv->OutDataNumReq = 0x00U; /* Clear the counter of characters to be send by SendBlock() */
    DeviceDataPrv->OutDataPtr = NULL;    /* Clear the buffer pointer for data to be transmitted */
    /* SIM_SCGC6: SPI0=1 */
    SIM_SCGC6 |= SIM_SCGC6_SPI0_MASK;
    /* Interrupt vector(s) priority setting */
    /* NVIC_IPR2: PRI_10=1 */
    NVIC_IPR2 = (uint32_t)((NVIC_IPR2 & (uint32_t)~(uint32_t)(
                                NVIC_IP_PRI_10(0x02)
                            )) | (uint32_t)(
                               NVIC_IP_PRI_10(0x01)
                           ));
    /* NVIC_ISER: SETENA31=0,SETENA30=0,SETENA29=0,SETENA28=0,SETENA27=0,SETENA26=0,SETENA25=0,SETENA24=0,SETENA23=0,SETENA22=0,SETENA21=0,SETENA20=0,SETENA19=0,SETENA18=0,SETENA17=0,SETENA16=0,SETENA15=0,SETENA14=0,SETENA13=0,SETENA12=0,SETENA11=0,SETENA10=1,SETENA9=0,SETENA8=0,SETENA7=0,SETENA6=0,SETENA5=0,SETENA4=0,SETENA3=0,SETENA2=0,SETENA1=0,SETENA0=0 */
    NVIC_ISER = NVIC_ISER_SETENA10_MASK;
    /* NVIC_ICER: CLRENA31=0,CLRENA30=0,CLRENA29=0,CLRENA28=0,CLRENA27=0,CLRENA26=0,CLRENA25=0,CLRENA24=0,CLRENA23=0,CLRENA22=0,CLRENA21=0,CLRENA20=0,CLRENA19=0,CLRENA18=0,CLRENA17=0,CLRENA16=0,CLRENA15=0,CLRENA14=0,CLRENA13=0,CLRENA12=0,CLRENA11=0,CLRENA10=0,CLRENA9=0,CLRENA8=0,CLRENA7=0,CLRENA6=0,CLRENA5=0,CLRENA4=0,CLRENA3=0,CLRENA2=0,CLRENA1=0,CLRENA0=0 */
    NVIC_ICER = 0x00U;
    /* SIM_SCGC5: PORTE=1,PORTC=1 */
    SIM_SCGC5 |= (SIM_SCGC5_PORTE_MASK | SIM_SCGC5_PORTC_MASK);
    /* PORTE_PCR18: ISF=0,MUX=6 */
    PORTE_PCR18 = (uint32_t)((PORTE_PCR18 & (uint32_t)~(uint32_t)(
                                  PORT_PCR_ISF_MASK |
                                  PORT_PCR_MUX(0x01)
                              )) | (uint32_t)(
                                 PORT_PCR_MUX(0x06)
                             ));
    /* PORTE_PCR19: ISF=0,MUX=6 */
    PORTE_PCR19 = (uint32_t)((PORTE_PCR19 & (uint32_t)~(uint32_t)(
                                  PORT_PCR_ISF_MASK |
                                  PORT_PCR_MUX(0x01)
                              )) | (uint32_t)(
                                 PORT_PCR_MUX(0x06)
                             ));
    /* PORTC_PCR5: ISF=0,MUX=2 */
    PORTC_PCR5 = (uint32_t)((PORTC_PCR5 & (uint32_t)~(uint32_t)(
                                 PORT_PCR_ISF_MASK |
                                 PORT_PCR_MUX(0x05)
                             )) | (uint32_t)(
                                PORT_PCR_MUX(0x02)
                            ));
    /* PORTC_PCR2: ISF=0,MUX=2 */
    PORTC_PCR2 = (uint32_t)((PORTC_PCR2 & (uint32_t)~(uint32_t)(
                                 PORT_PCR_ISF_MASK |
                                 PORT_PCR_MUX(0x05)
                             )) | (uint32_t)(
                                PORT_PCR_MUX(0x02)
                            ));
    /* SPI0_MCR: MSTR=0,CONT_SCKE=0,DCONF=0,FRZ=0,MTFE=0,??=0,ROOE=1,??=0,??=0,??=0,PCSIS=4,DOZE=0,MDIS=0,DIS_TXF=0,DIS_RXF=0,CLR_TXF=0,CLR_RXF=0,SMPL_PT=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,HALT=1 */
    SPI0_MCR = SPI_MCR_DCONF(0x00) |
               SPI_MCR_ROOE_MASK |
               SPI_MCR_PCSIS(0x04) |
               SPI_MCR_SMPL_PT(0x00) |
               SPI_MCR_HALT_MASK;        /* Set Configuration register */
    /* SPI0_MCR: MSTR=1,CONT_SCKE=0,DCONF=0,FRZ=0,MTFE=0,??=0,ROOE=1,??=0,??=0,??=0,PCSIS=4,DOZE=0,MDIS=0,DIS_TXF=1,DIS_RXF=1,CLR_TXF=1,CLR_RXF=1,SMPL_PT=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,HALT=1 */
    SPI0_MCR = SPI_MCR_MSTR_MASK |
               SPI_MCR_DCONF(0x00) |
               SPI_MCR_ROOE_MASK |
               SPI_MCR_PCSIS(0x04) |
               SPI_MCR_DIS_TXF_MASK |
               SPI_MCR_DIS_RXF_MASK |
               SPI_MCR_CLR_TXF_MASK |
               SPI_MCR_CLR_RXF_MASK |
               SPI_MCR_SMPL_PT(0x00) |
               SPI_MCR_HALT_MASK;        /* Set Configuration register */
    /* SPI0_CTAR0: DBR=1,FMSZ=7,CPOL=0,CPHA=0,LSBFE=0,PCSSCK=0,PASC=0,PDT=0,PBR=2,CSSCK=0,ASC=0,DT=0,BR=1 */
    SPI0_CTAR0 = SPI_CTAR_DBR_MASK |
                 SPI_CTAR_FMSZ(0x07) |
                 SPI_CTAR_PCSSCK(0x00) |
                 SPI_CTAR_PASC(0x00) |
                 SPI_CTAR_PDT(0x00) |
                 SPI_CTAR_PBR(0x02) |
                 SPI_CTAR_CSSCK(0x00) |
                 SPI_CTAR_ASC(0x00) |
                 SPI_CTAR_DT(0x00) |
                 SPI_CTAR_BR(0x01);      /* Set Clock and Transfer Attributes register */
    /* SPI0_SR: TCF=1,TXRXS=0,??=0,EOQF=1,TFUF=1,??=0,TFFF=1,??=0,??=0,??=0,??=1,??=0,RFOF=1,??=0,RFDF=1,??=0,TXCTR=0,TXNXTPTR=0,RXCTR=0,POPNXTPTR=0 */
    SPI0_SR = SPI_SR_TCF_MASK |
              SPI_SR_EOQF_MASK |
              SPI_SR_TFUF_MASK |
              SPI_SR_TFFF_MASK |
              SPI_SR_RFOF_MASK |
              SPI_SR_RFDF_MASK |
              SPI_SR_TXCTR(0x00) |
              SPI_SR_TXNXTPTR(0x00) |
              SPI_SR_RXCTR(0x00) |
              SPI_SR_POPNXTPTR(0x00) |
              0x00200000U;               /* Clear flags */
    /* SPI0_RSER: TCF_RE=0,??=0,??=0,EOQF_RE=0,TFUF_RE=0,??=0,TFFF_RE=0,TFFF_DIRS=0,??=0,??=0,??=0,??=0,RFOF_RE=0,??=0,RFDF_RE=1,RFDF_DIRS=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
    SPI0_RSER = SPI_RSER_RFDF_RE_MASK;   /* Set DMA Interrupt Request Select and Enable register */
    /* SPI0_MCR: HALT=0 */
    SPI0_MCR &= (uint32_t)~(uint32_t)(SPI_MCR_HALT_MASK);
    /* Registration of the device structure */
    PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_SM1_ID,DeviceDataPrv);
    return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the data data structure */
}
示例#14
0
/*
*******************************************************************************
* void SpiSetDelayAfterCS( SPI_MemMapPtr base , uint8_t delay)
*******************************************************************************
* Input         : base : Pointer to SPI0/ SPI1 /SPI2 Register Base 	
* 				  delay : Selects the scaler value for the Delay after CS.
* Output        : void
* Description   : Set After CS Delay for SPI
*******************************************************************************
*/
void SpiSetDelayAfterCS( SPI_MemMapPtr base , uint8_t delay)
{
	SPI_CTAR_REG(base,0) |= SPI_CTAR_CSSCK(delay);

}//End of SpiSetDelayAfterPCS
示例#15
0
/*********************************************************
* Name: SPI_Init
* Desc: Initialize SPI2 Module
* Parameter: None
* Return: None             
**********************************************************/
void SPI_Init(void)
{
    /*Body*/
    /* set PORTE pin 1 to DSPI1.SOUT*/
#ifdef MCU_MK70F12
	/* set PORTE pin 1 to DSPI1.SOUT*/
	PORTE_PCR1 =  PORT_PCR_MUX(7);
	/* set PORTE pin 2 to DSPI1.SCK*/
	PORTE_PCR2 =  PORT_PCR_MUX(2);
	/* set PORTE pin 3 to DSPI1.SIN*/
	PORTE_PCR3 =  PORT_PCR_MUX(7);
	/* set PORTE pin 4 to DSPI1.CS0*/
	PORTE_PCR4 =  PORT_PCR_MUX(2);    

	SIM_SCGC5 |= SIM_SCGC5_PORTE_MASK;
	/* Enable clock gate to DSPI1 module */
	SIM_SCGC6 |= SIM_SCGC6_DSPI1_MASK;
#elif defined MCU_MK20D5
	/* set PORTD pin 1 to SPI0.SOUT*/
	PORTD_PCR2 =  PORT_PCR_MUX(2);
	/* set PORTD pin 1 to SPI0.SCK*/
	PORTD_PCR1 =  PORT_PCR_MUX(2);
	/* set PORTD pin 3 to SPI0.SIN*/
	PORTD_PCR3 =  PORT_PCR_MUX(2);
	/* set PORTD pin 0 to SPI0.CS0*/
	PORTD_PCR0 =  PORT_PCR_MUX(2);    

	SIM_SCGC5 |= SIM_SCGC5_PORTE_MASK;
	/* Enable clock gate to DSPI1 module */
	SIM_SCGC6 |= SIM_SCGC6_SPI0_MASK;
#elif defined MCU_MK20D7
	/* set PORTE pin 1 to DSPI1.SOUT*/
	PORTE_PCR1 =  PORT_PCR_MUX(2);
	/* set PORTE pin 2 to DSPI1.SCK*/
	PORTE_PCR2 =  PORT_PCR_MUX(2);
	/* set PORTE pin 3 to DSPI1.SIN*/
	PORTE_PCR3 =  PORT_PCR_MUX(2);
	/* set PORTE pin 4 to DSPI1.CS0*/
	PORTE_PCR4 =  PORT_PCR_MUX(2);

	SIM_SCGC5 |= SIM_SCGC5_PORTE_MASK;
	/* Enable clock gate to DSPI1 module */
	SIM_SCGC6 |= SIM_SCGC6_SPI1_MASK;
#elif defined MCU_MK40D7
	/* set PORTE pin 1 to DSPI1.SOUT*/
	PORTE_PCR1 =  PORT_PCR_MUX(2);
	/* set PORTE pin 2 to DSPI1.SCK*/
	PORTE_PCR2 =  PORT_PCR_MUX(2);
	/* set PORTE pin 3 to DSPI1.SIN*/
	PORTE_PCR3 =  PORT_PCR_MUX(2);
	/* set PORTE pin 4 to DSPI1.CS0*/
	PORTE_PCR4 =  PORT_PCR_MUX(2);

	SIM_SCGC5 |= SIM_SCGC5_PORTE_MASK;
	/* Enable clock gate to DSPI1 module */
	SIM_SCGC6 |= SIM_SCGC6_SPI1_MASK;
#elif defined MCU_MK40N512VMD100
	/* set PORTE pin 1 to DSPI1.SOUT*/
	PORTE_PCR1 =  PORT_PCR_MUX(2);
	/* set PORTE pin 2 to DSPI1.SCK*/
	PORTE_PCR2 =  PORT_PCR_MUX(2);
	/* set PORTE pin 3 to DSPI1.SIN*/
	PORTE_PCR3 =  PORT_PCR_MUX(2);
	/* set PORTE pin 4 to DSPI1.CS0*/
	PORTE_PCR4 =  PORT_PCR_MUX(2);

	SIM_SCGC5 |= SIM_SCGC5_PORTE_MASK;
	/* Enable clock gate to DSPI1 module */
	SIM_SCGC6 |= SIM_SCGC6_SPI1_MASK;
#elif defined MCU_MK53N512CMD100
	/* set PORTE pin 1 to DSPI1.SOUT*/
	PORTE_PCR1 =  PORT_PCR_MUX(2);
	/* set PORTE pin 2 to DSPI1.SCK*/
	PORTE_PCR2 =  PORT_PCR_MUX(2);
	/* set PORTE pin 3 to DSPI1.SIN*/
	PORTE_PCR3 =  PORT_PCR_MUX(2);
	/* set PORTE pin 4 to DSPI1.CS0*/
	PORTE_PCR4 =  PORT_PCR_MUX(2);

	SIM_SCGC5 |= SIM_SCGC5_PORTE_MASK;
	/* Enable clock gate to DSPI1 module */
	SIM_SCGC6 |= SIM_SCGC6_SPI1_MASK;
#elif defined MCU_MK60N512VMD100
	/* set PORTE pin 1 to DSPI1.SOUT*/
	PORTE_PCR1 =  PORT_PCR_MUX(2);
	/* set PORTE pin 2 to DSPI1.SCK*/
	PORTE_PCR2 =  PORT_PCR_MUX(2);
	/* set PORTE pin 3 to DSPI1.SIN*/
	PORTE_PCR3 =  PORT_PCR_MUX(2);
	/* set PORTE pin 4 to DSPI1.CS0*/
	PORTE_PCR4 =  PORT_PCR_MUX(2);

	SIM_SCGC5 |= SIM_SCGC5_PORTE_MASK;
	/* Enable clock gate to DSPI1 module */
	SIM_SCGC6 |= SIM_SCGC6_SPI1_MASK;
#elif defined MCU_MK21D5
        SIM_SCGC5 |= SIM_SCGC5_PORTB_MASK;
	/* set PORTB pin 16 to DSPI1.SOUT*/
	PORTB_PCR16 =  PORT_PCR_MUX(2);
	/* set PORTB pin 11 to DSPI1.SCK*/
	PORTB_PCR11 =  PORT_PCR_MUX(2);
	/* set PORTB pin 17 to DSPI1.SIN*/
	PORTB_PCR17 =  PORT_PCR_MUX(2);
	/* set PORTB pin 10 to DSPI1.CS0*/
	PORTB_PCR10 =  PORT_PCR_MUX(2);

	SIM_SCGC5 |= SIM_SCGC5_PORTB_MASK;
	/* Enable clock gate to DSPI1 module */
	SIM_SCGC6 |= SIM_SCGC6_SPI1_MASK | SIM_SCGC6_DMAMUX_MASK;
#elif defined MCU_MKL25Z4
	/* set PORTE pin 1 to DSPI1.SOUT*/
	PORTE_PCR1 =  PORT_PCR_MUX(2);
	/* set PORTE pin 2 to DSPI1.SCK*/
	PORTE_PCR2 =  PORT_PCR_MUX(2);
	/* set PORTE pin 3 to DSPI1.SIN*/
	PORTE_PCR3 =  PORT_PCR_MUX(2);
	/* set PORTE pin 4 to DSPI1.CS0*/
	PORTE_PCR4 =  PORT_PCR_MUX(2);
	SIM_SCGC5 |= SIM_SCGC5_PORTE_MASK;
	/* Enable clock gate to DSPI1 module */
	SIM_SCGC4 |= SIM_SCGC4_SPI1_MASK;
	SIM_SCGC6 |= SIM_SCGC6_DMAMUX_MASK;
#else
	/* set PORTE pin 1 to DSPI1.SOUT*/
	PORTE_PCR1 =  PORT_PCR_MUX(2);
	/* set PORTE pin 2 to DSPI1.SCK*/
	PORTE_PCR2 =  PORT_PCR_MUX(2);
	/* set PORTE pin 3 to DSPI1.SIN*/
	PORTE_PCR3 =  PORT_PCR_MUX(2);
	/* set PORTE pin 4 to DSPI1.CS0*/
	PORTE_PCR4 =  PORT_PCR_MUX(2);

	SIM_SCGC5 |= SIM_SCGC5_PORTE_MASK;
	/* Enable clock gate to DSPI1 module */
	SIM_SCGC6 |= SIM_SCGC6_DMAMUX_SPI1_MASK;
#endif

	/* Enable master mode, disable both transmit and receive FIFO buffers,
   set the inactive state for PCS2 high, enable the module (MDIS = 0),
   delay the sample point from the leading edge of the clock and halt
   any transfer
	 */
#ifdef MCU_MK20D5
	SPI0_MCR = (SPI_MCR_MSTR_MASK   |
			SPI_MCR_PCSIS(1)    |
			SPI_MCR_SMPL_PT(2)  |
			SPI_MCR_HALT_MASK);

	SPI0_MCR |= (SPI_MCR_CLR_RXF_MASK | SPI_MCR_CLR_TXF_MASK);
#elif defined MCU_MKL25Z4
  
	PORTE_PCR4 =  PORT_PCR_MUX(1);
	GPIOE_PDDR |= (1<<4);
	SPI_clr_SS();
	

	SPI1_C2 = SPI_C2_SPISWAI_MASK;     
	SPI1_C1 = SPI_C1_SPE_MASK | SPI_C1_MSTR_MASK | SPI_C1_SSOE_MASK;
	
#else
	SPI1_MCR = (SPI_MCR_MSTR_MASK   |
			SPI_MCR_PCSIS(1)    |
			SPI_MCR_SMPL_PT(2)  |
			SPI_MCR_HALT_MASK);

	SPI1_MCR |= (SPI_MCR_CLR_RXF_MASK | SPI_MCR_CLR_TXF_MASK);
#endif
	/* DSPI clock 375 KHz */
	/* The system clock fsys = 68 MHz */
	// K60: bus clock: 48MHz, DSPI clock: ~107 KHz
	// K70: bus clock: 60MHz, DSPI clock: ~156 KHz
	/* Value to be passed in SPI_Send_byte() function to DPI_CTAR0 register */
#ifdef MCU_MKL25Z4
	/* 375KHz SPI clock */
	SPI1_BR = SPI_BR_SPPR(7) | SPI_BR_SPR(5);             /*  SCK = 10us */
#else
#ifdef MCU_MK70F12
    gSPI_BaudRate = (SPI_CTAR_PBR(1) | SPI_CTAR_BR(0x07));
#else
    gSPI_BaudRate = (SPI_CTAR_PBR(3) | SPI_CTAR_BR(0x06));
#endif
    /* Configure the rest of the delays */
    gSPI_BeforeTransfDelay = (SPI_CTAR_CSSCK(1) | SPI_CTAR_CSSCK(0x04));
    gSPI_AfterTransfDelay  = (SPI_CTAR_PASC(3) | SPI_CTAR_ASC(0x04));
    gSPI_InterTransfDelay  = (SPI_CTAR_PDT(3)  | SPI_CTAR_DT(0x05));  
#endif
}/*EndBody*/
示例#16
0
文件: SPI.c 项目: lkxlaz/uni-projects
BOOL SPI_Init(const TSPIModule* const aSPIModule, const uint32_t moduleClock)
{
  // Enables SPI clock
  SIM_SCGC3 |= SIM_SCGC3_DSPI2_MASK;       
  
  // Enable clock gate to PORTD and PORTE
  SIM_SCGC5 |= SIM_SCGC5_PORTD_MASK;                         
  SIM_SCGC5 |= SIM_SCGC5_PORTE_MASK;                         

  // set PORTD 11-15 as SPI2
  PORTD_PCR11 = PORT_PCR_MUX(2);                             
  PORTD_PCR12 = PORT_PCR_MUX(2);                            
  PORTD_PCR13 = PORT_PCR_MUX(2);                            
  PORTD_PCR14 = PORT_PCR_MUX(2);                             
  PORTD_PCR15 = PORT_PCR_MUX(2);                        

  // Configure GPIO7 and GPIO8
  PORTE_PCR27 = PORT_PCR_MUX(1);                           
  PORTE_PCR5  = PORT_PCR_MUX(1);           
  
  // Initially clear output  
  GPIOE_PCOR  = (GPIO8 | GPIO7);  
  // set pin direction as output  
  GPIOE_PDDR |= (GPIO8 | GPIO7);                             

  SPI_SetBaudRateDivisors(moduleClock, aSPIModule->baudRate);

  // Enable module clocks
  SPI2_MCR &= ~SPI_MCR_MDIS_MASK;          
  // Halt serial transfers in debug mode  
  SPI2_MCR |= SPI_MCR_FRZ_MASK;      
  // Set Chip select to inactive high  
  SPI2_MCR |= SPI_MCR_PCSIS(1);    
  // Disable transmit FIFO and receive FIFO  
  SPI2_MCR |= SPI_MCR_DIS_TXF_MASK;                          
  SPI2_MCR |= SPI_MCR_DIS_RXF_MASK;                          

  // Set 16 bit frame size
  SPI2_CTAR0 |= SPI_CTAR_FMSZ(15);                           

  // Sets the SPI to Master Mode
  if (aSPIModule->isMaster)
    SPI2_MCR |= SPI_MCR_MSTR_MASK;                           

  // Sets the SPI to Master Mode
  if (aSPIModule->continuousClock)
    SPI2_MCR |= SPI_MCR_CONT_SCKE_MASK;                      

  // Enables the SPI clock
  if (aSPIModule->inactiveHighClock)
    SPI2_CTAR0 |= SPI_CTAR_CPOL_MASK;                        

  if (aSPIModule->changedOnLeadingClockEdge)                 
    SPI2_CTAR0 |= SPI_CTAR_CPHA_MASK;

  // Sets the LSB first
  if (aSPIModule->LSBFirst)
    SPI2_CTAR0 |= SPI_CTAR_LSBFE_MASK;                       

  // Delay to allow capacitors to charge before transfer
  SPI2_CTAR0 |= SPI_CTAR_CSSCK(3); 
  SPI2_CTAR0 |= SPI_CTAR_PCSSCK(3);

  SpiTransmitData.s.Hi = 1;

  return bTRUE;

}
示例#17
0
void SPI_Configuration (void)
{
	SPI_Type *SPIx = NULL;
	PORT_Type *SPI_PORT = NULL;
	SPI_InitTypeDef SPI_InitStruct;
	SPI_DataMapTypeDef *pSPI_DataMap;
	SPI_CSMapTypeDef *pSPI_CSMap;
	SPI_InitStruct.SPIxDataMap = SPILCD_PORT_DATA;
	SPI_InitStruct.SPIxPCSMap = SPILCD_PORT_CS;
	SPI_InitStruct.SPI_DataSize = 16;
	SPI_InitStruct.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_4;
	SPI_InitStruct.SPI_Mode = SPI_Mode_Master;
	SPI_InitStruct.SPI_CPHA = SPI_CPHA_1Edge;
	SPI_InitStruct.SPI_CPOL = SPI_CPOL_High;
	SPI_InitStruct.SPI_FirstBit = SPI_FirstBit_MSB;
	//SPI_Init(&SPI_InitStruct);
	pSPI_CSMap = (SPI_CSMapTypeDef*)&(SPI_InitStruct.SPIxPCSMap);
	pSPI_DataMap = (SPI_DataMapTypeDef*)&(SPI_InitStruct.SPIxDataMap);
	SIM->SCGC6 |= SIM_SCGC6_SPI0_MASK;
	SPIx = SPI0;
	SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK;
	SPI_PORT = PORTA;	
	SPI_PORT->PCR[pSPI_DataMap->SPI_SCK_Pin_Index] &= ~PORT_PCR_MUX_MASK;
	SPI_PORT->PCR[pSPI_DataMap->SPI_SIN_Pin_Index] &= ~PORT_PCR_MUX_MASK;
	SPI_PORT->PCR[pSPI_DataMap->SPI_SOUT_Pin_Index] &= ~PORT_PCR_MUX_MASK;
	SPI_PORT->PCR[pSPI_DataMap->SPI_SCK_Pin_Index] |= PORT_PCR_MUX(pSPI_DataMap->SPI_Alt_Index);
	SPI_PORT->PCR[pSPI_DataMap->SPI_SIN_Pin_Index] |= PORT_PCR_MUX(pSPI_DataMap->SPI_Alt_Index);
	SPI_PORT->PCR[pSPI_DataMap->SPI_SOUT_Pin_Index] |= PORT_PCR_MUX(pSPI_DataMap->SPI_Alt_Index);
	/*SCK配置开漏*/
	SPI_PORT->PCR[pSPI_DataMap->SPI_SCK_Pin_Index]|= PORT_PCR_ODE_MASK;
	SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK;
/*	SPI_PORT = PORTA;
	SPI_PORT->PCR[pSPI_CSMap->SPI_PCS_Pin_Index] &= ~PORT_PCR_MUX_MASK;
	SPI_PORT->PCR[pSPI_CSMap->SPI_PCS_Pin_Index] |= PORT_PCR_MUX(pSPI_CSMap->SPI_Alt_Index);*/
	//设置主从模式
	(SPI_InitStruct.SPI_Mode == SPI_Mode_Master)?(SPIx->MCR  |= SPI_MCR_MSTR_MASK):(SPIx->MCR  &= ~SPI_MCR_MSTR_MASK);
	SPIx->MCR  = 0 & (~SPI_MCR_MDIS_MASK) 
					|SPI_MCR_HALT_MASK        //让SPI进入停止模式
					|SPI_MCR_MSTR_MASK        //配置SPI为主机模式
					|SPI_MCR_PCSIS_MASK       //PCS为高电平当在SPI不工作的时候
					|SPI_MCR_CLR_TXF_MASK     //首先要清除MDIS,清除TXF_MASK和RXF_MASK
					|SPI_MCR_CLR_RXF_MASK  
					|SPI_MCR_DIS_TXF_MASK     //然后再禁止TXD和RXD FIFO 模式 ,将SPI配置成正常模式
					|SPI_MCR_DIS_RXF_MASK
					|SPI_MCR_SMPL_PT(2);
	SPIx->CTAR[1] = 0| SPI_CTAR_DBR_MASK	 //设置通信的
					| SPI_CTAR_PCSSCK(0)
					| SPI_CTAR_PASC(0)
					| SPI_CTAR_ASC(0)
					| SPI_CTAR_PBR(0)
					| SPI_CTAR_CSSCK(0)
					| SPI_CTAR_FMSZ(SPI_InitStruct.SPI_DataSize -1)//设置数据传输的位数
					| SPI_CTAR_PDT(0);//设置片选信号在数据完成后的延时值 
	//分频设置
	SPIx->CTAR[1] |=SPI_CTAR_BR(SPI_InitStruct.SPI_BaudRatePrescaler);							 
	//时钟相位设置
	(SPI_InitStruct.SPI_CPHA == SPI_CPHA_1Edge)?(SPIx->CTAR[1] &= ~SPI_CTAR_CPHA_MASK):(SPIx->CTAR[1] |= SPI_CTAR_CPHA_MASK);
	//时钟极性
	(SPI_InitStruct.SPI_CPOL == SPI_CPOL_Low)?(SPIx->CTAR[1] &= ~SPI_CTAR_CPOL_MASK):(SPIx->CTAR[1] |= SPI_CTAR_CPOL_MASK);
	//配置MSB或者LSD
	(SPI_InitStruct.SPI_FirstBit == SPI_FirstBit_MSB)?(SPIx->CTAR[1] &= ~SPI_CTAR_LSBFE_MASK):(SPIx->CTAR[1] |= SPI_CTAR_LSBFE_MASK);
	//清空状态
	SPIx->SR = SPI_SR_EOQF_MASK   //队列结束标志 w1c  (write 1 to clear)     
			| SPI_SR_TFUF_MASK    //TX FIFO underflow flag  w1c
			| SPI_SR_TFFF_MASK    //TX FIFO fill      flag  w1c
			| SPI_SR_RFOF_MASK    //RX FIFO overflow  flag  w1c
			| SPI_SR_RFDF_MASK    //RX FIFO fill      flasg w1c (0时为空)
			| SPI_SR_TCF_MASK;
	//开始传输
	SPIx->MCR &= ~SPI_MCR_HALT_MASK;    //开始传输,见参考手册1129页					
	
	AD7687_ReceiveWord ();
	NVIC_DisableIRQ (AD7687_SIN_IRQ);
 	AD7687_SIN_PORT->PCR[AD7687_SIN_Pin]&=~PORT_PCR_IRQC_MASK;
 	AD7687_SIN_PORT->PCR[AD7687_SIN_Pin]|=PORT_PCR_IRQC(GPIO_IT_RISING);
}
示例#18
0
	*((volatile unsigned *)(ITM_BASE + 0x01000)) = 0x400003FE; // DWT_CTRL
	*((volatile unsigned *)(ITM_BASE + 0x40304)) = 0x00000100; // Formatter and Flush Control Register
}

static SPI_slave volatile	test_slave = SPI_slave(
	Platform::spi0,
	{PTD, 0}, GPIOPin::MUX_ALT2,
	(
		SPI_CTAR_FMSZ(7)   |   // 8-bit frames
		SPI_CTAR_CPOL_MASK |   // Clock idle high
		SPI_CTAR_CPHA_MASK |   // Sample following edge
		SPI_CTAR_PCSSCK(2) |   // PCS to SCK prescaler = 5
		SPI_CTAR_PASC(2)   |   // Same delay before end of PCS
		SPI_CTAR_PDT(3)    |   // Same delay after end of PCS
		SPI_CTAR_PBR(0)    |   // Use sysclk / 2
		SPI_CTAR_CSSCK(6)  |   // Base delay is 128*Tsys
		SPI_CTAR_ASC(3)    |   // Unit delay before end of PCS
		SPI_CTAR_DT(3)     |   // Same after end of PCS
		SPI_CTAR_BR(8)         // Scale by 256
	),
    0
);

/*!
 * @brief Application entry point
 */
int main(){
	struct pt pt_dsp, pt_controller, pt_wavegen;

	PT_INIT(&pt_dsp);
	PT_INIT(&pt_controller);
示例#19
0
/***********************************************************************************************
 功能:SPI 初始化
 形参:SPI_InitStruct SPI 初始化结构
 返回:0
 详解:0
************************************************************************************************/
void SPI_Init(SPI_InitTypeDef* SPI_InitStruct)
{
	SPI_Type *SPIx = NULL;
	PORT_Type *SPI_PORT = NULL;
	SPI_DataMapTypeDef *pSPI_DataMap = (SPI_DataMapTypeDef*)&(SPI_InitStruct->SPIxDataMap);
	SPI_CSMapTypeDef *pSPI_CSMap = (SPI_CSMapTypeDef*)&(SPI_InitStruct->SPIxPCSMap);
	
	//参数检测
	assert_param(IS_SPI_DATA_CHL(SPI_InitStruct->SPIxDataMap));
	assert_param(IS_SPI_PCS_CHL(SPI_InitStruct->SPIxPCSMap));
	assert_param(IS_SPI_BAUDRATE(SPI_InitStruct->SPI_BaudRatePrescaler));
	assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
	assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
	assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
	assert_param(IS_SPI_FIRSTBIT(SPI_InitStruct->SPI_FirstBit));
	
	//找出SPI模块 开SPI模块时钟
	switch(pSPI_DataMap->SPI_Index)
	{
		case 0:
			SIM->SCGC6 |= SIM_SCGC6_SPI0_MASK;
			SPIx = SPI0;
			break;
		case 1:
			SIM->SCGC6 |= SIM_SCGC6_SPI1_MASK;
			SPIx = SPI1;
			break;
		case 2:
			SIM->SCGC3 |= SIM_SCGC3_SPI2_MASK;
		  SPIx = SPI2;
			break;
		default:break;     
	}
	//找出对应的PORT
	switch(pSPI_DataMap->SPI_GPIO_Index)
	{
		case 0:
			SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK;
			SPI_PORT = PORTA;
			break;
		case 1:
			SIM->SCGC5 |= SIM_SCGC5_PORTB_MASK;
			SPI_PORT = PORTB;
			break;
		case 2:
			SIM->SCGC5 |= SIM_SCGC5_PORTC_MASK;
			SPI_PORT = PORTC;
			break;
		case 3:
			SIM->SCGC5 |= SIM_SCGC5_PORTD_MASK;
			SPI_PORT = PORTD;
			break;
		case 4:
			SIM->SCGC5 |= SIM_SCGC5_PORTE_MASK;
			SPI_PORT = PORTE;
			break;
		default:break;
	}
	//开启对应的引脚 SCK SOUT SIN
	SPI_PORT->PCR[pSPI_DataMap->SPI_SCK_Pin_Index] &= ~PORT_PCR_MUX_MASK;
	SPI_PORT->PCR[pSPI_DataMap->SPI_SIN_Pin_Index] &= ~PORT_PCR_MUX_MASK;
	SPI_PORT->PCR[pSPI_DataMap->SPI_SOUT_Pin_Index] &= ~PORT_PCR_MUX_MASK;
	SPI_PORT->PCR[pSPI_DataMap->SPI_SCK_Pin_Index] |= PORT_PCR_MUX(pSPI_DataMap->SPI_Alt_Index);
	SPI_PORT->PCR[pSPI_DataMap->SPI_SIN_Pin_Index] |= PORT_PCR_MUX(pSPI_DataMap->SPI_Alt_Index);
	SPI_PORT->PCR[pSPI_DataMap->SPI_SOUT_Pin_Index] |= PORT_PCR_MUX(pSPI_DataMap->SPI_Alt_Index);
	/*SCK配置开漏*/
	SPI_PORT->PCR[pSPI_DataMap->SPI_SCK_Pin_Index]|= PORT_PCR_ODE_MASK;
	//配置PCS
	//找出对应的PORT
	switch(pSPI_CSMap->SPI_GPIO_Index)
	{
		case 0:
			SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK;
			SPI_PORT = PORTA;
			break;
		case 1:
			SIM->SCGC5 |= SIM_SCGC5_PORTB_MASK;
			SPI_PORT = PORTB;
			break;
		case 2:
			SIM->SCGC5 |= SIM_SCGC5_PORTC_MASK;
			SPI_PORT = PORTC;
			break;
		case 3:
			SIM->SCGC5 |= SIM_SCGC5_PORTD_MASK;
			SPI_PORT = PORTD;
			break;
		case 4:
			SIM->SCGC5 |= SIM_SCGC5_PORTE_MASK;
			SPI_PORT = PORTE;
			break;
		default:break;
	}
	SPI_PORT->PCR[pSPI_CSMap->SPI_PCS_Pin_Index] &= ~PORT_PCR_MUX_MASK;
	SPI_PORT->PCR[pSPI_CSMap->SPI_PCS_Pin_Index] |= PORT_PCR_MUX(pSPI_CSMap->SPI_Alt_Index);
	//设置主从模式
	(SPI_InitStruct->SPI_Mode == SPI_Mode_Master)?(SPIx->MCR  |= SPI_MCR_MSTR_MASK):(SPIx->MCR  &= ~SPI_MCR_MSTR_MASK);
	//配置SPI主模式寄存器
	SPIx->MCR  = 0 & (~SPI_MCR_MDIS_MASK) 
									|SPI_MCR_HALT_MASK        //让SPI进入停止模式
									|SPI_MCR_MSTR_MASK        //配置SPI为主机模式
									|SPI_MCR_PCSIS_MASK       //PCS为高电平当在SPI不工作的时候
									|SPI_MCR_CLR_TXF_MASK     //首先要清除MDIS,清除TXF_MASK和RXF_MASK
									|SPI_MCR_CLR_RXF_MASK  
									|SPI_MCR_DIS_TXF_MASK     //然后再禁止TXD和RXD FIFO 模式 ,将SPI配置成正常模式
									|SPI_MCR_DIS_RXF_MASK
									|SPI_MCR_SMPL_PT(2);
	//配置分频及波特率
	SPIx->CTAR[1] = 0| SPI_CTAR_DBR_MASK	 //设置通信的
									| SPI_CTAR_PCSSCK(0)
									| SPI_CTAR_PASC(0)
									| SPI_CTAR_PBR(0)
									| SPI_CTAR_CSSCK(0)
									| SPI_CTAR_FMSZ(SPI_InitStruct->SPI_DataSize -1) //设置数据传输的位数
									| SPI_CTAR_PDT(0);                                //设置片选信号在数据完成后的延时值 
	//分频设置
	SPIx->CTAR[1] |=SPI_CTAR_BR(SPI_InitStruct->SPI_BaudRatePrescaler);							 
	//时钟相位设置
	(SPI_InitStruct->SPI_CPHA == SPI_CPHA_1Edge)?(SPIx->CTAR[1] &= ~SPI_CTAR_CPHA_MASK):(SPIx->CTAR[1] |= SPI_CTAR_CPHA_MASK);
	//时钟极性
	(SPI_InitStruct->SPI_CPOL == SPI_CPOL_Low)?(SPIx->CTAR[1] &= ~SPI_CTAR_CPOL_MASK):(SPIx->CTAR[1] |= SPI_CTAR_CPOL_MASK);
	//配置MSB或者LSD
	(SPI_InitStruct->SPI_FirstBit == SPI_FirstBit_MSB)?(SPIx->CTAR[1] &= ~SPI_CTAR_LSBFE_MASK):(SPIx->CTAR[1] |= SPI_CTAR_LSBFE_MASK);
	//清空状态
  SPIx->SR = SPI_SR_EOQF_MASK   //队列结束标志 w1c  (write 1 to clear)     
            | SPI_SR_TFUF_MASK    //TX FIFO underflow flag  w1c
            | SPI_SR_TFFF_MASK    //TX FIFO fill      flag  w1c
            | SPI_SR_RFOF_MASK    //RX FIFO overflow  flag  w1c
            | SPI_SR_RFDF_MASK    //RX FIFO fill      flasg w1c (0时为空)
					  | SPI_SR_TCF_MASK;
	//开始传输
	 SPIx->MCR &= ~SPI_MCR_HALT_MASK;    //开始传输,见参考手册1129页
}
示例#20
0
   ctar0Value = ctar0;
   ctar1Value = ctar1;   
   // Configure SPI
   (void)spi_setSpeed(0);
   SPI0->MCR   = SPI_MCR_CLR_RXF_MASK|SPI_MCR_ROOE_MASK|SPI_MCR_CLR_TXF_MASK|SPI_MCR_PCSIS((1<<0)|(1<<1))|
                SPI_MCR_MSTR_MASK|SPI_MCR_FRZ_MASK|SPI_MCR_DCONF(0)|SPI_MCR_SMPL_PT(0);
}

typedef struct {
   uint32_t freq; 
   uint32_t ctarBaud; 
} Scidata;

static const Scidata spiBaudTable[] = {
     //  freq(kHz)                        ctarBaud
 /*  0 */ {12000, SPI_CTAR_PBR(0)|SPI_CTAR_BR(0)|SPI_CTAR_PCSSCK(0)|SPI_CTAR_CSSCK(0)},
 /*  1 */ { 8000, SPI_CTAR_PBR(1)|SPI_CTAR_BR(0)|SPI_CTAR_PCSSCK(0)|SPI_CTAR_CSSCK(1)},
 /*  2 */ { 6000, SPI_CTAR_PBR(0)|SPI_CTAR_BR(1)|SPI_CTAR_PCSSCK(0)|SPI_CTAR_CSSCK(1)},
 /*  3 */ { 4800, SPI_CTAR_PBR(2)|SPI_CTAR_BR(0)|SPI_CTAR_PCSSCK(1)|SPI_CTAR_CSSCK(0)},
 /*  4 */ { 4000, SPI_CTAR_PBR(1)|SPI_CTAR_BR(1)|SPI_CTAR_PCSSCK(1)|SPI_CTAR_CSSCK(0)},
 /*  5 */ { 3000, SPI_CTAR_PBR(0)|SPI_CTAR_BR(3)|SPI_CTAR_PCSSCK(0)|SPI_CTAR_CSSCK(2)},
 /*  6 */ { 2667, SPI_CTAR_PBR(1)|SPI_CTAR_BR(2)|SPI_CTAR_PCSSCK(2)|SPI_CTAR_CSSCK(0)},
 /*  7 */ { 2400, SPI_CTAR_PBR(2)|SPI_CTAR_BR(1)|SPI_CTAR_PCSSCK(2)|SPI_CTAR_CSSCK(0)},
 /*  8 */ { 2000, SPI_CTAR_PBR(1)|SPI_CTAR_BR(3)|SPI_CTAR_PCSSCK(1)|SPI_CTAR_CSSCK(1)},
 /*  9 */ { 1500, SPI_CTAR_PBR(0)|SPI_CTAR_BR(4)|SPI_CTAR_PCSSCK(0)|SPI_CTAR_CSSCK(3)},
 /* 10 */ { 1200, SPI_CTAR_PBR(2)|SPI_CTAR_BR(3)|SPI_CTAR_PCSSCK(2)|SPI_CTAR_CSSCK(1)},
 /* 11 */ { 1000, SPI_CTAR_PBR(1)|SPI_CTAR_BR(4)|SPI_CTAR_PCSSCK(1)|SPI_CTAR_CSSCK(2)},
 /* 12 */ {  857, SPI_CTAR_PBR(3)|SPI_CTAR_BR(3)|SPI_CTAR_PCSSCK(1)|SPI_CTAR_CSSCK(2)},
 /* 13 */ {  750, SPI_CTAR_PBR(0)|SPI_CTAR_BR(5)|SPI_CTAR_PCSSCK(2)|SPI_CTAR_CSSCK(2)},
 /* 14 */ {  600, SPI_CTAR_PBR(2)|SPI_CTAR_BR(4)|SPI_CTAR_PCSSCK(2)|SPI_CTAR_CSSCK(2)},
 /* 15 */ {  500, SPI_CTAR_PBR(1)|SPI_CTAR_BR(5)|SPI_CTAR_PCSSCK(1)|SPI_CTAR_CSSCK(3)},
示例#21
0
文件: spi.c 项目: LucaZulberti/RIOT
int spi_init_master(spi_t dev, spi_conf_t conf, spi_speed_t speed)
{
    SPI_Type *spi_dev;
    uint8_t br_prescaler = 0xff;
    uint8_t br_scaler = 0xff;
    uint8_t prescaler_tmp = 0xff;
    uint8_t scaler_tmp = 0xff;
    uint32_t ctas = 0;
    uint32_t ctar = 0;
    uint32_t br_desired;
    uint32_t module_clock;
    uint32_t tcsc_freq;
    uint32_t tasc_freq;
    uint32_t tdt_freq;

    switch (speed) {
        case SPI_SPEED_100KHZ:
            br_desired = 100000;
            break;

        case SPI_SPEED_400KHZ:
            br_desired = 400000;
            break;

        case SPI_SPEED_1MHZ:
            br_desired = 1000000;
            break;

        case SPI_SPEED_5MHZ:
            br_desired = 5000000;
            break;

        case SPI_SPEED_10MHZ:
            br_desired = 10000000;
            break;

        default:
            return -2;
    }

    switch (dev) {
#if SPI_0_EN

        case SPI_0:
            KINETIS_CFG_SPI_IO(0);
            break;
#endif /* SPI_0_EN */

#if SPI_1_EN

        case SPI_1:
            KINETIS_CFG_SPI_IO(1);
            break;
#endif /* SPI_1_EN */

#if SPI_2_EN

        case SPI_2:
            KINETIS_CFG_SPI_IO(2);
            break;
#endif /* SPI_2_EN */

#if SPI_3_EN

        case SPI_3:
            KINETIS_CFG_SPI_IO(3);
            break;
#endif /* SPI_3_EN */

#if SPI_4_EN

        case SPI_4:
            KINETIS_CFG_SPI_IO(4);
            break;
#endif /* SPI_4_EN */

#if SPI_5_EN

        case SPI_5:
            KINETIS_CFG_SPI_IO(5);
            break;
#endif /* SPI_5_EN */

#if SPI_6_EN

        case SPI_6:
            KINETIS_CFG_SPI_IO(6);
            break;
#endif /* SPI_6_EN */

#if SPI_7_EN

        case SPI_7:
            KINETIS_CFG_SPI_IO(7);
            break;
#endif /* SPI_7_EN */

        default:
            return -1;
    }

    /* Find baud rate scaler and prescaler settings */
    if (find_closest_baudrate_scalers(module_clock, br_desired,
                                      &br_prescaler, &br_scaler) < 0) {
        /* Desired baud rate is too low to be reachable at current module clock frequency. */
        return -2;
    }

    ctar |= SPI_CTAR_PBR(br_prescaler) | SPI_CTAR_BR(br_scaler);

    /* Find the other delay divisors */
    /* tCSC */
    if (tcsc_freq == 0) {
        /* Default to same as baud rate if set to zero. */
        tcsc_freq = br_desired;
    }

    if (find_closest_delay_scalers(module_clock, tcsc_freq,
                                   &prescaler_tmp, &scaler_tmp) < 0) {
        /* failed to find a solution */
        return -2;
    }

    ctar |= SPI_CTAR_PCSSCK(prescaler_tmp) | SPI_CTAR_CSSCK(scaler_tmp);

    /* tASC */
    if (tasc_freq == 0) {
        /* Default to same as baud rate if set to zero. */
        tasc_freq = br_desired;
    }

    if (find_closest_delay_scalers(module_clock, tasc_freq,
                                   &prescaler_tmp, &scaler_tmp) < 0) {
        /* failed to find a solution */
        return -2;
    }

    ctar |= SPI_CTAR_PASC(prescaler_tmp) | SPI_CTAR_ASC(scaler_tmp);

    /* tDT */
    if (tdt_freq == 0) {
        /* Default to same as baud rate if set to zero. */
        tdt_freq = br_desired;
    }

    if (find_closest_delay_scalers(module_clock, tdt_freq,
                                   &prescaler_tmp, &scaler_tmp) < 0) {
        /* failed to find a solution */
        return -2;
    }

    ctar |= SPI_CTAR_PDT(prescaler_tmp) | SPI_CTAR_DT(scaler_tmp);


    /* Set clock polarity and phase. */
    switch (conf) {
        case SPI_CONF_FIRST_RISING:
            break;

        case SPI_CONF_SECOND_RISING:
            ctar |= SPI_CTAR_CPHA_MASK;
            break;

        case SPI_CONF_FIRST_FALLING:
            ctar |= SPI_CTAR_CPOL_MASK;
            break;

        case SPI_CONF_SECOND_FALLING:
            ctar |= SPI_CTAR_CPHA_MASK | SPI_CTAR_CPOL_MASK;
            break;

        default:
            return -2;
    }

    /* Update CTAR register with new timing settings, 8-bit frame size. */
    spi_dev->CTAR[ctas] = SPI_CTAR_FMSZ(7) | ctar;

    /* enable SPI */
    spi_dev->MCR = SPI_MCR_MSTR_MASK
                   | SPI_MCR_DOZE_MASK
                   | SPI_MCR_CLR_TXF_MASK
                   | SPI_MCR_CLR_RXF_MASK;

    if (KINETIS_SPI_USE_HW_CS) {
        spi_dev->MCR |= SPI_MCR_PCSIS(1);
    }

    spi_dev->RSER = (uint32_t)0;

    return 0;
}
示例#22
0
void spi_set_params(const spi_bus_t spi_num, const uint8_t ctas, const spi_config_t* config) {
  uint32_t ctar = 0;
  uint8_t br_prescaler = 0xff;
  uint8_t br_scaler = 0xff;
  uint8_t prescaler_tmp = 0xff;
  uint8_t scaler_tmp = 0xff;

  /* All of the SPI modules run on the Bus clock, see K60 Ref Manual. 3.9.4.2 SPI clocking */
  /* Find the baud rate divisors */
  find_closest_baudrate_scalers(SystemBusClock, config->sck_freq, &br_prescaler, &br_scaler);
  ctar |= SPI_CTAR_PBR(br_prescaler) | SPI_CTAR_BR(br_scaler);

  /* Find the other delay divisors */
  /* tCSC */
  if (config->tcsc_freq > 0) {
    if (find_closest_delay_scalers(SystemBusClock, config->tcsc_freq,
          &prescaler_tmp, &scaler_tmp) == 0) {
      ctar |= SPI_CTAR_PCSSCK(prescaler_tmp) | SPI_CTAR_CSSCK(scaler_tmp);
    } else {
      /* failed to find a solution */
      DEBUGGER_BREAK(BREAK_INVALID_PARAM);
    }
  } else {
    /* default: copy BR scaler */
    ctar |= SPI_CTAR_PCSSCK(br_prescaler) | SPI_CTAR_CSSCK(br_scaler);
  }

  /* tASC */
  if (config->tasc_freq > 0) {
    if (find_closest_delay_scalers(SystemBusClock, config->tasc_freq,
          &prescaler_tmp, &scaler_tmp) == 0) {
      ctar |= SPI_CTAR_PASC(prescaler_tmp) | SPI_CTAR_ASC(scaler_tmp);
    } else {
      /* failed to find a solution */
      DEBUGGER_BREAK(BREAK_INVALID_PARAM);
    }
  } else {
    /* default: copy BR scaler */
    ctar |= SPI_CTAR_PASC(br_prescaler) | SPI_CTAR_ASC(br_scaler);
  }

  /* tDT */
  if (config->tdt_freq > 0) {
    if (find_closest_delay_scalers(SystemBusClock, config->tdt_freq,
          &prescaler_tmp, &scaler_tmp) == 0) {
      ctar |= SPI_CTAR_PDT(prescaler_tmp) | SPI_CTAR_DT(scaler_tmp);
    } else {
      /* failed to find a solution */
      DEBUGGER_BREAK(BREAK_INVALID_PARAM);
    }
  } else {
    /* default: copy BR scaler */
    ctar |= SPI_CTAR_PDT(br_prescaler) | SPI_CTAR_DT(br_scaler);
  }

  /* FMSZ+1 equals the frame size */
  ctar |= SPI_CTAR_FMSZ(config->frame_size - 1);

  if (config->cpol != 0) {
    ctar |= SPI_CTAR_CPOL_MASK;
  }
  if (config->cpha != 0) {
    ctar |= SPI_CTAR_CPHA_MASK;
  }

  SPI[spi_num]->CTAR[ctas] = ctar;
  spi_conf[spi_num][ctas] = config;
}