示例#1
0
/*!
    \brief      diable SPI DMA send or receive
    \param[in]  spi_periph: SPIx(x=0,1,2,3,4,5)
    \param[in]  spi_dma: SPI DMA mode
                only one parameter can be selected which is shown as below:
      \arg        SPI_DMA_TRANSMIT: SPI transmit data use DMA
      \arg        SPI_DMA_RECEIVE: SPI receive data use DMA
    \param[out] none
    \retval     none
*/
void spi_dma_disable(uint32_t spi_periph, uint8_t spi_dma)
{
    if (SPI_DMA_TRANSMIT == spi_dma) {
        SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMATEN);
    } else {
        SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMAREN);
    }
}
示例#2
0
/*!
    \brief      enable SPI DMA send or receive
    \param[in]  spi_periph: SPIx(x=0,1,2,3,4,5)
    \param[in]  spi_dma: SPI DMA mode
                only one parameter can be selected which is shown as below:
      \arg        SPI_DMA_TRANSMIT: SPI transmit data use DMA
      \arg        SPI_DMA_RECEIVE: SPI receive data use DMA
    \param[out] none
    \retval     none
*/
void spi_dma_enable(uint32_t spi_periph, uint8_t spi_dma)
{
    if (SPI_DMA_TRANSMIT == spi_dma) {
        SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMATEN;
    } else {
        SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMAREN;
    }
}
示例#3
0
/*!
    \brief      SPI and I2S interrupt disable
    \param[in]  spi_periph: SPIx(x=0,1,2,3,4,5)
    \param[in]  spi_i2s_int:
      \arg        SPI_I2S_INT_TBE: transmit buffer empty interrupt
      \arg        SPI_I2S_INT_RBNE: receive buffer not empty interrupt
      \arg        SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error,
                                   transmission underrun error and format error interrupt
    \param[out] none
    \retval     none
*/
void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t spi_i2s_int)
{
    switch(spi_i2s_int){
    case SPI_I2S_INT_TBE :
        SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TBEIE);
        break;
    case SPI_I2S_INT_RBNE :
        SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_RBNEIE);
        break;
    case SPI_I2S_INT_ERR :
        SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_ERRIE);
        break;
    default :
        break;
    }
}
示例#4
0
/*!
    \brief      disable SPI and I2S interrupt
    \param[in]  spi_periph: SPIx(x=0,1,2,3,4,5)
    \param[in]  spi_i2s_int: SPI/I2S interrupt
                only one parameter can be selected which is shown as below:
      \arg        SPI_I2S_INT_TBE: transmit buffer empty interrupt
      \arg        SPI_I2S_INT_RBNE: receive buffer not empty interrupt
      \arg        SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error,
                                   transmission underrun error and format error interrupt
    \param[out] none
    \retval     none
*/
void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t spi_i2s_int)
{
    switch (spi_i2s_int) {
        /* SPI/I2S transmit buffer empty interrupt */
        case SPI_I2S_INT_TBE :
            SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TBEIE);
            break;
        /* SPI/I2S receive buffer not empty interrupt */
        case SPI_I2S_INT_RBNE :
            SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_RBNEIE);
            break;
        /* SPI/I2S error */
        case SPI_I2S_INT_ERR :
            SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_ERRIE);
            break;
        default :
            break;
    }
}
示例#5
0
/*!
    \brief      get SPI and I2S interrupt flag status
    \param[in]  spi_periph: SPIx(x=0,1,2,3,4,5)
    \param[in]  spi_i2s_int: SPI/I2S interrupt flag status
      \arg        SPI_I2S_INT_FLAG_TBE: transmit buffer empty interrupt flag
      \arg        SPI_I2S_INT_FLAG_RBNE: receive buffer not empty interrupt flag
      \arg        SPI_I2S_INT_FLAG_RXORERR: overrun interrupt flag
      \arg        SPI_INT_FLAG_CONFERR: config error interrupt flag
      \arg        SPI_INT_FLAG_CRCERR: CRC error interrupt flag
      \arg        I2S_INT_FLAG_TXURERR: underrun error interrupt flag
      \arg        SPI_I2S_INT_FLAG_FERR: format error interrupt flag
    \param[out] none
    \retval     FlagStatus: SET or RESET
*/
FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t spi_i2s_int)
{
    uint32_t reg1 = SPI_STAT(spi_periph);
    uint32_t reg2 = SPI_CTL1(spi_periph);

    switch (spi_i2s_int) {
        /* SPI/I2S transmit buffer empty interrupt */
        case SPI_I2S_INT_FLAG_TBE :
            reg1 = reg1 & SPI_STAT_TBE;
            reg2 = reg2 & SPI_CTL1_TBEIE;
            break;
        /* SPI/I2S receive buffer not empty interrupt */
        case SPI_I2S_INT_FLAG_RBNE :
            reg1 = reg1 & SPI_STAT_RBNE;
            reg2 = reg2 & SPI_CTL1_RBNEIE;
            break;
        /* SPI/I2S overrun interrupt */
        case SPI_I2S_INT_FLAG_RXORERR :
            reg1 = reg1 & SPI_STAT_RXORERR;
            reg2 = reg2 & SPI_CTL1_ERRIE;
            break;
        /* SPI config error interrupt */
        case SPI_INT_FLAG_CONFERR :
            reg1 = reg1 & SPI_STAT_CONFERR;
            reg2 = reg2 & SPI_CTL1_ERRIE;
            break;
        /* SPI CRC error interrupt */
        case SPI_INT_FLAG_CRCERR :
            reg1 = reg1 & SPI_STAT_CRCERR;
            reg2 = reg2 & SPI_CTL1_ERRIE;
            break;
        /* I2S underrun error interrupt */
        case I2S_INT_FLAG_TXURERR :
            reg1 = reg1 & SPI_STAT_TXURERR;
            reg2 = reg2 & SPI_CTL1_ERRIE;
            break;
        /* SPI/I2S format error interrupt */
        case SPI_I2S_INT_FLAG_FERR :
            reg1 = reg1 & SPI_STAT_FERR;
            reg2 = reg2 & SPI_CTL1_ERRIE;
            break;
        default :
            break;
    }
    /*get SPI/I2S interrupt flag status */
    if (reg1 && reg2) {
        return SET;
    } else {
        return RESET;
    }
}
示例#6
0
/*!
    \brief      get interrupt flag status
    \param[in]  spi_periph: SPIx(x=0,1,2,3,4,5)
    \param[in]  spi_i2s_int:
      \arg        SPI_I2S_INT_TBE: transmit buffer empty interrupt
      \arg        SPI_I2S_INT_RBNE: receive buffer not empty interrupt
      \arg        SPI_I2S_INT_RXORERR: overrun interrupt
      \arg        SPI_INT_CONFERR: config error interrupt
      \arg        SPI_INT_CRCERR: CRC error interrupt
      \arg        I2S_INT_TXURERR: underrun error interrupt
      \arg        SPI_I2S_INT_FERR: format error interrupt
    \param[out] none
    \retval     FlagStatus: SET or RESET
*/
FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t spi_i2s_int)
{
    uint32_t reg1 = SPI_STAT(spi_periph);
    uint32_t reg2 = SPI_CTL1(spi_periph);
    
    uint32_t temp1 = 0U;
    uint32_t temp2 = 0U;

    switch(spi_i2s_int){
    case SPI_I2S_INT_TBE :
        temp1 = reg1 & SPI_STAT_TBE;
        temp2 = reg2 & SPI_CTL1_TBEIE;
        break;
    case SPI_I2S_INT_RBNE :
        temp1 = reg1 & SPI_STAT_RBNE;
        temp2 = reg2 & SPI_CTL1_RBNEIE;
        break;
    case SPI_I2S_INT_RXORERR :
        temp1 = reg1 & SPI_STAT_RXORERR;
        temp2 = reg2 & SPI_CTL1_ERRIE;
        break;
    case SPI_INT_CONFERR :
        temp1 = reg1 & SPI_STAT_CONFERR;
        temp2 = reg2 & SPI_CTL1_ERRIE;
        break;
    case SPI_INT_CRCERR :
        temp1 = reg1 & SPI_STAT_CRCERR;
        temp2 = reg2 & SPI_CTL1_ERRIE;
        break;
    case I2S_INT_TXURERR :
        temp1 = reg1 & SPI_STAT_TXURERR;
        temp2 = reg2 & SPI_CTL1_ERRIE;
        break;
    case SPI_I2S_INT_FERR :
        temp1 = reg1 & SPI_STAT_FERR;
        temp2 = reg2 & SPI_CTL1_ERRIE;
        break;
    default :
        break;
    }

    if(temp1 && temp2){
        return SET;
    }else{
        return RESET;
    }
}
示例#7
0
/*!
    \brief      disable SPI TI mode
    \param[in]  spi_periph: SPIx(x=0,1,2,3,4,5)
    \param[out] none
    \retval     none
*/
void spi_ti_mode_disable(uint32_t spi_periph)
{
    SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TMOD);
}
示例#8
0
/*!
    \brief      enable SPI TI mode
    \param[in]  spi_periph: SPIx(x=0,1,2,3,4,5)
    \param[out] none
    \retval     none
*/
void spi_ti_mode_enable(uint32_t spi_periph)
{
    SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TMOD;
}
示例#9
0
/*!
    \brief      disable SPI nss output
    \param[in]  spi_periph: SPIx(x=0,1,2,3,4,5)
    \param[out] none
    \retval     none
*/
void spi_nss_output_disable(uint32_t spi_periph)
{
    SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSDRV);
}
示例#10
0
/*!
    \brief      enable SPI nss output
    \param[in]  spi_periph: SPIx(x=0,1,2,3,4,5)
    \param[out] none
    \retval     none
*/
void spi_nss_output_enable(uint32_t spi_periph)
{
    SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSDRV;
}