void SpiFormat(Spi_t *obj, int8_t bits, int8_t cpol, int8_t cpha, int8_t slave) { spi_clock_polarity_t clockPolarity; spi_clock_phase_t clockPhase; spi_data_bitcount_mode_t bitCount; /* Disable Spi module */ SPI_HAL_Disable(obj->Spi); clockPolarity = ((cpol != 1) ? kSpiClockPolarity_ActiveHigh : kSpiClockPolarity_ActiveLow); clockPhase = ((cpha != 1) ? kSpiClockPhase_FirstEdge : kSpiClockPhase_SecondEdge); bitCount = ((bits != 8) ? kSpi16BitMode : kSpi8BitMode); if (obj->isSlave) { /* Set SPI to master mode */ SPI_HAL_SetMasterSlave(obj->Spi, kSpiSlave); } else { /* Set SPI to master mode */ SPI_HAL_SetMasterSlave(obj->Spi, kSpiMaster); // Set slave select to automatic output mode SPI_HAL_SetSlaveSelectOutputMode(obj->Spi, kSpiSlaveSelect_AutomaticOutput); } SPI_HAL_SetDataFormat(obj->Spi, clockPolarity, clockPhase, kSpiMsbFirst); SPI_HAL_Set8or16BitMode(obj->Spi, bitCount); /* Enable Spi module */ SPI_HAL_Enable(obj->Spi); }
/*FUNCTION********************************************************************** * * Function Name : SPI_DRV_MasterInit * Description : Initialize a SPI instance for master mode operation. * This function uses a CPU interrupt driven method for transferring data. * This function initializes the run-time state structure to track the ongoing * transfers, ungates the clock to the SPI module, resets and initializes the module * to default settings, configures the IRQ state structure, enables * the module-level interrupt to the core, and enables the SPI module. * *END**************************************************************************/ spi_status_t SPI_DRV_MasterInit(uint32_t instance, spi_master_state_t * spiState) { SPI_Type *base = g_spiBase[instance]; /* Clear the state for this instance.*/ memset(spiState, 0, sizeof(* spiState)); /* Enable clock for SPI*/ CLOCK_SYS_EnableSpiClock(instance); /* configure the run-time state struct with the source clock value */ spiState->spiSourceClock = CLOCK_SYS_GetSpiFreq(instance); /* Reset the SPI module to it's default state, which includes SPI disabled */ SPI_HAL_Init(base); /* Init the interrupt sync object.*/ OSA_SemaCreate(&spiState->irqSync, 0); /* Set SPI to master mode */ SPI_HAL_SetMasterSlave(base, kSpiMaster); /* Set slave select to automatic output mode */ SPI_HAL_SetSlaveSelectOutputMode(base, kSpiSlaveSelect_AutomaticOutput); /* Set the SPI pin mode to normal mode */ SPI_HAL_SetPinMode(base, kSpiPinMode_Normal); #if FSL_FEATURE_SPI_FIFO_SIZE if (g_spiFifoSize[instance] != 0) { /* If SPI module contains a FIFO, enable it and set watermarks to half full/empty */ SPI_HAL_SetFifoMode(base, true, kSpiTxFifoOneHalfEmpty, kSpiRxFifoOneHalfFull); } #endif /* Save runtime structure pointers to irq handler can point to the correct state structure*/ g_spiStatePtr[instance] = spiState; /* Enable SPI interrupt.*/ INT_SYS_EnableIRQ(g_spiIrqId[instance]); /* SPI system Enable*/ SPI_HAL_Enable(base); return kStatus_SPI_Success; }
/*FUNCTION********************************************************************** * * Function Name : SPI_DRV_DmaMasterInit * Description : Initializes a SPI instance for master mode operation to work with DMA. * This function uses a dma driven method for transferring data. * this function initializes the run-time state structure to track the ongoing * transfers, ungates the clock to the SPI module, resets the SPI module, initializes the module * to user defined settings and default settings, configures the IRQ state structure, enables * the module-level interrupt to the core, and enables the SPI module. * * This initialization function also configures the DMA module by requesting channels for DMA * operation. * *END**************************************************************************/ spi_status_t SPI_DRV_DmaMasterInit(uint32_t instance, spi_dma_master_state_t * spiDmaState) { SPI_Type *base = g_spiBase[instance]; /* Clear the state for this instance.*/ memset(spiDmaState, 0, sizeof(* spiDmaState)); /* Enable clock for SPI*/ CLOCK_SYS_EnableSpiClock(instance); /* configure the run-time state struct with the source clock value */ spiDmaState->spiSourceClock = CLOCK_SYS_GetSpiFreq(instance); /* Reset the SPI module to it's default state, which includes SPI disabled */ SPI_HAL_Init(base); /* Init the interrupt sync object.*/ if (OSA_SemaCreate(&spiDmaState->irqSync, 0) != kStatus_OSA_Success) { return kStatus_SPI_Error; } /* Set SPI to master mode */ SPI_HAL_SetMasterSlave(base, kSpiMaster); /* Set slave select to automatic output mode */ SPI_HAL_SetSlaveSelectOutputMode(base, kSpiSlaveSelect_AutomaticOutput); /* Set the SPI pin mode to normal mode */ SPI_HAL_SetPinMode(base, kSpiPinMode_Normal); #if FSL_FEATURE_SPI_FIFO_SIZE if (g_spiFifoSize[instance] != 0) { /* If SPI module contains a FIFO, enable it and set watermarks to half full/empty */ SPI_HAL_SetFifoMode(base, true, kSpiTxFifoOneHalfEmpty, kSpiRxFifoOneHalfFull); /* Set the interrupt clearing mechansim select for later use in driver to clear * status flags */ SPI_HAL_SetIntClearCmd(base, true); } #endif /* Save runtime structure pointers to irq handler can point to the correct state structure*/ g_spiStatePtr[instance] = spiDmaState; /***************************************** * Request DMA channel for RX and TX FIFO *****************************************/ /* This channel transfers data from RX FIFO to receiveBuffer */ if (instance == 0) { /* Request DMA channel for RX FIFO */ DMA_DRV_RequestChannel(kDmaAnyChannel, kDmaRequestMux0SPI0Rx, &spiDmaState->dmaReceive); /* Request DMA channel for TX FIFO */ DMA_DRV_RequestChannel(kDmaAnyChannel, kDmaRequestMux0SPI0Tx, &spiDmaState->dmaTransmit); } #if (SPI_INSTANCE_COUNT > 1) else { /* Request DMA channel for RX FIFO */ DMA_DRV_RequestChannel(kDmaAnyChannel, kDmaRequestMux0SPI1Rx, &spiDmaState->dmaReceive); /* Request DMA channel for TX FIFO */ DMA_DRV_RequestChannel(kDmaAnyChannel, kDmaRequestMux0SPI1Tx, &spiDmaState->dmaTransmit); } #endif /* Enable SPI interrupt.*/ INT_SYS_EnableIRQ(g_spiIrqId[instance]); /* SPI system Enable */ SPI_HAL_Enable(base); return kStatus_SPI_Success; }