__EXPORT int nsh_archinitialize(void) { /* the interruption subsystem is not initialized when stm32_boardinitialize() is called */ stm32_gpiosetevent(GPIO_FORCE_BOOTLOADER, true, false, false, _bootloader_force_pin_callback); /* configure power supply control/sense pins */ stm32_configgpio(GPIO_VDD_5V_SENSORS_EN); /* configure the high-resolution time/callout interface */ hrt_init(); /* configure the DMA allocator */ dma_alloc_init(); /* configure CPU load estimation */ #ifdef CONFIG_SCHED_INSTRUMENTATION cpuload_initialize_once(); #endif /* set up the serial DMA polling */ static struct hrt_call serial_dma_call; struct timespec ts; /* * Poll at 1ms intervals for received bytes that have not triggered * a DMA event. */ ts.tv_sec = 0; ts.tv_nsec = 1000000; hrt_call_every(&serial_dma_call, ts_to_abstime(&ts), ts_to_abstime(&ts), (hrt_callout)stm32_serial_dma_poll, NULL); /* initial LED state */ drv_led_start(); led_off(LED_AMBER); led_off(LED_BLUE); /* Configure SPI-based devices */ spi1 = up_spiinitialize(1); if (!spi1) { message("[boot] FAILED to initialize SPI port 1\n"); up_ledon(LED_AMBER); return -ENODEV; } /* Default SPI1 to 1MHz and de-assert the known chip selects. */ SPI_SETFREQUENCY(spi1, 10000000); SPI_SETBITS(spi1, 8); SPI_SETMODE(spi1, SPIDEV_MODE3); SPI_SELECT(spi1, PX4_SPIDEV_MPU, false); up_udelay(20); return OK; }
static void ramtron_attach(void) { /* find the right spi */ struct spi_dev_s *spi = up_spiinitialize(2); /* this resets the spi bus, set correct bus speed again */ // xxx set in ramtron driver, leave this out // SPI_SETFREQUENCY(spi, 4000000); SPI_SETFREQUENCY(spi, 375000000); SPI_SETBITS(spi, 8); SPI_SETMODE(spi, SPIDEV_MODE3); SPI_SELECT(spi, SPIDEV_FLASH, false); if (spi == NULL) errx(1, "failed to locate spi bus"); /* start the MTD driver, attempt 5 times */ for (int i = 0; i < 5; i++) { ramtron_mtd = ramtron_initialize(spi); if (ramtron_mtd) { /* abort on first valid result */ if (i > 0) { warnx("warning: ramtron needed %d attempts to attach", i+1); } break; } } /* if last attempt is still unsuccessful, abort */ if (ramtron_mtd == NULL) errx(1, "failed to initialize ramtron driver"); attached = true; }
static inline void adxl345_configspi(FAR struct spi_dev_s *spi) { /* Configure SPI for the ADXL345 */ SPI_SETMODE(spi, SPIDEV_MODE3); SPI_SETBITS(spi, 8); SPI_SETFREQUENCY(spi, ADXL345_SPI_MAXFREQUENCY); }
static void max6675_lock(FAR struct spi_dev_s *spi) { (void)SPI_LOCK(spi, true); SPI_SETMODE(spi, SPIDEV_MODE0); SPI_SETBITS(spi, 8); (void)SPI_HWFEATURES(spi, 0); SPI_SETFREQUENCY(spi, 4000000); }
int cc1101_access(struct cc1101_dev_s * dev, uint8_t addr, uint8_t *buf, int length) { int stabyte; /* Address cannot explicitly define READ command while length WRITE. * Also access to these cells is only permitted as one byte, eventhough * transfer is marked as BURST! */ if ((addr & CC1101_READ_SINGLE) && length != 1) return ERROR; /* Prepare SPI */ cc1101_access_begin(dev); if (length>1 || length < -1) SPI_SETFREQUENCY(dev->spi, CC1101_SPIFREQ_BURST); else SPI_SETFREQUENCY(dev->spi, CC1101_SPIFREQ_SINGLE); /* Transfer */ if (length <= 0) { /* 0 length are command strobes */ if (length < -1) addr |= CC1101_WRITE_BURST; stabyte = SPI_SEND(dev->spi, addr); if (length) { SPI_SNDBLOCK(dev->spi, buf, -length); } } else { addr |= CC1101_READ_SINGLE; if (length > 1) addr |= CC1101_READ_BURST; stabyte = SPI_SEND(dev->spi, addr); SPI_RECVBLOCK(dev->spi, buf, length); } cc1101_access_end(dev); return stabyte; }
static inline void max11802_configspi(FAR struct spi_dev_s *spi) { /* Configure SPI for the MAX11802. But only if we own the SPI bus. * Otherwise, don't bother because it might change. */ SPI_SETMODE(spi, CONFIG_MAX11802_SPIMODE); SPI_SETBITS(spi, 8); SPI_SETFREQUENCY(spi, CONFIG_MAX11802_FREQUENCY); }
static inline void nrf24l01_configspi(FAR struct spi_dev_s *spi) { /* Configure SPI for the NRF24L01 module. */ SPI_SELECT(spi, SPIDEV_WIRELESS, true); /* Useful ? */ SPI_SETMODE(spi, SPIDEV_MODE0); SPI_SETBITS(spi, 8); (void)SPI_HWFEATURES(spi, 0); (void)SPI_SETFREQUENCY(spi, NRF24L01_SPIFREQ); SPI_SELECT(spi, SPIDEV_WIRELESS, false); }
static inline void ads7843e_configspi(FAR struct spi_dev_s *spi) { /* Configure SPI for the ADS7843. But only if we own the SPI bus. Otherwise, don't * bother because it might change. */ SPI_SELECT(spi, SPIDEV_TOUCHSCREEN, true); SPI_SETMODE(spi, CONFIG_ADS7843E_SPIMODE); SPI_SETBITS(spi, 8); SPI_SETFREQUENCY(spi, CONFIG_ADS7843E_FREQUENCY); SPI_SELECT(spi, SPIDEV_TOUCHSCREEN, false); }
static inline void nrf24l01_configspi(FAR struct spi_dev_s *spi) { /* Configure SPI for the NRF24L01 module. * As we own the SPI bus this method is called just once. */ SPI_SELECT(spi, SPIDEV_WIRELESS, true); // Useful ? SPI_SETMODE(spi, SPIDEV_MODE0); SPI_SETBITS(spi, 8); SPI_SETFREQUENCY(spi, NRF24L01_SPIFREQ); SPI_SELECT(spi, SPIDEV_WIRELESS, false); }
static int max11802_ioctl(FAR struct file *filep, int cmd, unsigned long arg) { FAR struct inode *inode; FAR struct max11802_dev_s *priv; int ret; iinfo("cmd: %d arg: %ld\n", cmd, arg); DEBUGASSERT(filep); inode = filep->f_inode; DEBUGASSERT(inode && inode->i_private); priv = (FAR struct max11802_dev_s *)inode->i_private; /* Get exclusive access to the driver data structure */ ret = sem_wait(&priv->devsem); if (ret < 0) { /* This should only happen if the wait was canceled by an signal */ DEBUGASSERT(errno == EINTR); return -EINTR; } /* Process the IOCTL by command */ switch (cmd) { case TSIOC_SETFREQUENCY: /* arg: Pointer to uint32_t frequency value */ { FAR uint32_t *ptr = (FAR uint32_t *)((uintptr_t)arg); DEBUGASSERT(priv->config != NULL && ptr != NULL); priv->config->frequency = SPI_SETFREQUENCY(priv->spi, *ptr); } break; case TSIOC_GETFREQUENCY: /* arg: Pointer to uint32_t frequency value */ { FAR uint32_t *ptr = (FAR uint32_t *)((uintptr_t)arg); DEBUGASSERT(priv->config != NULL && ptr != NULL); *ptr = priv->config->frequency; } break; default: ret = -ENOTTY; break; } sem_post(&priv->devsem); return ret; }
/** Strobes command and returns chip status byte * * By default commands are send as Write. To a command, * CC1101_READ_SINGLE may be OR'ed to obtain the number of RX bytes * pending in RX FIFO. */ inline uint8_t cc1101_strobe(struct cc1101_dev_s * dev, uint8_t command) { uint8_t status; cc1101_access_begin(dev); SPI_SETFREQUENCY(dev->spi, CC1101_SPIFREQ_SINGLE); status = SPI_SEND(dev->spi, command); cc1101_access_end(dev); return status; }
static void pga11x_configure(FAR struct spi_dev_s *spi) { spivdbg("MODE: %d BITS: 8 Frequency: %d\n", CONFIG_PGA11X_SPIMODE, CONFIG_PGA11X_SPIFREQUENCY); /* Call the setfrequency, setbits, and setmode methods to make sure that * the SPI is properly configured for the device. */ SPI_SETMODE(spi, CONFIG_PGA11X_SPIMODE); SPI_SETBITS(spi, 8); (void)SPI_HWFEATURES(spi, 0); (void)SPI_SETFREQUENCY(spi, CONFIG_PGA11X_SPIFREQUENCY); }
FAR struct lcd_dev_s *ssd1351_initialize(FAR struct spi_dev_s *spi, unsigned int devno) #endif { FAR struct ssd1351_dev_s *priv = &g_lcddev; /* Sanity check */ #ifdef CONFIG_SSD1351_PARALLEL8BIT DEBUGASSERT(lcd != NULL); #elif defined(CONFIG_SSD1351_SPI3WIRE) || defined(CONFIG_SSD1351_SPI4WIRE) DEBUGASSERT(spi != NULL); #endif DEBUGASSERT(devno == 0); /* Initialize the driver data structure */ priv->dev.getvideoinfo = ssd1351_getvideoinfo; priv->dev.getplaneinfo = ssd1351_getplaneinfo; priv->dev.getpower = ssd1351_getpower; priv->dev.setpower = ssd1351_setpower; priv->dev.getcontrast = ssd1351_getcontrast; priv->dev.setcontrast = ssd1351_setcontrast; #ifdef CONFIG_SSD1351_PARALLEL8BIT priv->lcd = lcd; #elif defined(CONFIG_SSD1351_SPI3WIRE) || defined(CONFIG_SSD1351_SPI4WIRE) priv->spi = spi; #endif priv->power = LCD_FULL_OFF; /* Configure the SPI bus if we own it. Otherwise, don't bother because * it might change. */ #if defined(CONFIG_SSD1351_SPI3WIRE) || defined(CONFIG_SSD1351_SPI4WIRE) #ifdef CONFIG_SPI_OWNBUS SPI_SETMODE(spi, CONFIG_SSD1351_SPIMODE); SPI_SETBITS(spi, SSD1351_SPIBITS); SPI_SETFREQUENCY(spi, CONFIG_SSD1351_SPIFREQ); #endif #endif /* Configure the device */ ssd1351_hwinitialize(priv); return &priv->dev; }
int SPI::_transfer(uint8_t *send, uint8_t *recv, unsigned len) { SPI_SETFREQUENCY(_dev, _frequency); SPI_SETMODE(_dev, _mode); SPI_SETBITS(_dev, 8); SPI_SELECT(_dev, _device, true); /* do the transfer */ SPI_EXCHANGE(_dev, send, recv, len); /* and clean up */ SPI_SELECT(_dev, _device, false); return OK; }
static inline void pn532_configspi(FAR struct spi_dev_s *spi) { int ret; /* Configure SPI for the PN532 module. */ SPI_SETMODE(spi, SPIDEV_MODE0); SPI_SETBITS(spi, 8); ret = SPI_HWFEATURES(spi, HWFEAT_LSBFIRST); if (ret < 0) { pn532err("ERROR: SPI_HWFEATURES failed to set bit order: %d\n", ret); } (void)SPI_SETFREQUENCY(spi, CONFIG_PN532_SPI_FREQ); }
static void max11802_lock(FAR struct spi_dev_s *spi) { /* Lock the SPI bus because there are multiple devices competing for the * SPI bus */ (void)SPI_LOCK(spi, true); /* We have the lock. Now make sure that the SPI bus is configured for the * MAX11802 (it might have gotten configured for a different device while * unlocked) */ SPI_SETMODE(spi, CONFIG_MAX11802_SPIMODE); SPI_SETBITS(spi, 8); SPI_SETFREQUENCY(spi, CONFIG_MAX11802_FREQUENCY); }
static void ramtron_attach(void) { /* find the right spi */ #ifdef CONFIG_ARCH_BOARD_AEROCORE struct spi_dev_s *spi = up_spiinitialize(4); #else struct spi_dev_s *spi = up_spiinitialize(2); #endif /* this resets the spi bus, set correct bus speed again */ SPI_SETFREQUENCY(spi, 10 * 1000 * 1000); SPI_SETBITS(spi, 8); SPI_SETMODE(spi, SPIDEV_MODE3); SPI_SELECT(spi, SPIDEV_FLASH, false); if (spi == NULL) errx(1, "failed to locate spi bus"); /* start the RAMTRON driver, attempt 5 times */ for (int i = 0; i < 5; i++) { mtd_dev = ramtron_initialize(spi); if (mtd_dev) { /* abort on first valid result */ if (i > 0) { warnx("warning: mtd needed %d attempts to attach", i + 1); } break; } } /* if last attempt is still unsuccessful, abort */ if (mtd_dev == NULL) errx(1, "failed to initialize mtd driver"); int ret = mtd_dev->ioctl(mtd_dev, MTDIOC_SETSPEED, (unsigned long)10*1000*1000); if (ret != OK) { // FIXME: From the previous warnx call, it looked like this should have been an errx instead. Tried // that but setting the bug speed does fail all the time. Which was then exiting and the board would // not run correctly. So changed to warnx. warnx("failed to set bus speed"); } attached = true; }
static void pn532_lock(FAR struct spi_dev_s *spi) { int ret; (void)SPI_LOCK(spi, true); SPI_SETMODE(spi, SPIDEV_MODE0); SPI_SETBITS(spi, 8); ret = SPI_HWFEATURES(spi, HWFEAT_LSBFIRST); if (ret < 0) { pn532err("ERROR: SPI_HWFEATURES failed to set bit order: %d\n", ret); } (void)SPI_SETFREQUENCY(spi, CONFIG_PN532_SPI_FREQ); }
static void spi_write(int port, int addr, int frequency, int bits, int conf, char value) { unsigned char buf[2]; buf[0] = addr; buf[1] = value; SPI_LOCK(spi_dev, true); SPI_SETFREQUENCY(spi_dev, frequency); SPI_SETBITS(spi_dev, bits); SPI_SETMODE(spi_dev, conf); SPI_SELECT(spi_dev, port, true); SPI_SNDBLOCK(spi_dev, buf, 2); SPI_SELECT(spi_dev, port, false); SPI_LOCK(spi_dev, false); }
static char spi_read(int port, int addr, int frequency, int bits, int conf) { unsigned char buf[2]; buf[0] = addr | 0x80; SPI_LOCK(spi_dev, true); SPI_SETFREQUENCY(spi_dev, frequency); SPI_SETBITS(spi_dev, bits); SPI_SETMODE(spi_dev, conf); SPI_SELECT(spi_dev, port, true); SPI_RECVBLOCK(spi_dev, buf, 2); SPI_SELECT(spi_dev, port, false); SPI_LOCK(spi_dev, false); return buf[1]; }
static void ads7843e_lock(FAR struct spi_dev_s *spi) { /* Lock the SPI bus because there are multiple devices competing for the * SPI bus */ (void)SPI_LOCK(spi, true); /* We have the lock. Now make sure that the SPI bus is configured for the * ADS7843 (it might have gotten configured for a different device while * unlocked) */ SPI_SELECT(spi, SPIDEV_TOUCHSCREEN, true); SPI_SETMODE(spi, CONFIG_ADS7843E_SPIMODE); SPI_SETBITS(spi, 8); SPI_SETFREQUENCY(spi, CONFIG_ADS7843E_FREQUENCY); SPI_SELECT(spi, SPIDEV_TOUCHSCREEN, false); }
static void nrf24l01_lock(FAR struct spi_dev_s *spi) { /* Lock the SPI bus because there are multiple devices competing for the * SPI bus */ (void)SPI_LOCK(spi, true); /* We have the lock. Now make sure that the SPI bus is configured for the * NRF24L01 (it might have gotten configured for a different device while * unlocked) */ SPI_SELECT(spi, SPIDEV_WIRELESS, true); SPI_SETMODE(spi, SPIDEV_MODE0); SPI_SETBITS(spi, 8); SPI_SETFREQUENCY(spi, NRF24L01_SPIFREQ); SPI_SELECT(spi, SPIDEV_WIRELESS, false); }
int SPI::_transferword(uint16_t *send, uint16_t *recv, unsigned len) { SPI_SETFREQUENCY(_dev, _frequency); SPI_SETMODE(_dev, _mode); SPI_SETBITS(_dev, 16); /* 16 bit transfer */ SPI_SELECT(_dev, _device, true); /* do the transfer */ //SPI_EXCHANGE(_dev, send, recv, len); /* Try to be compatible with the t_stall of the ADIS16448 which is 9usec (by applying 5usec delay ) */ SPI_EXCHANGE(_dev, send, nullptr, 1); up_udelay(5); /* Reduced to 5 usec (from 10 use) */ SPI_EXCHANGE(_dev, nullptr, recv+1, len-1); //// /* and clean up */ SPI_SELECT(_dev, _device, false); return OK; }
static void ssd1351_select(FAR struct ssd1351_dev_s *priv) { FAR struct spi_dev_s *spi = priv->spi; /* Select the chip, locking the SPI bus in case there are multiple devices * competing for the SPI bus */ gdbg("SELECTED\n"); SPI_LOCK(spi, true); SPI_SELECT(spi, SPIDEV_DISPLAY, true); /* Now make sure that the SPI bus is configured for this device (it might * have gotten configured for a different device while unlocked) */ SPI_SETMODE(spi, CONFIG_SSD1351_SPIMODE); SPI_SETBITS(spi, SSD1351_SPIBITS); (void)SPI_HWFEATURES(spi, 0); (void)SPI_SETFREQUENCY(spi, CONFIG_SSD1351_SPIFREQ); }
static void spansion_attach(void) { /* find the right spi */ struct spi_dev_s *spi = up_spiinitialize(1); /* this resets the spi bus, set correct bus speed again */ SPI_SETFREQUENCY(spi, 10 * 1000 * 1000); SPI_SETBITS(spi, 8); SPI_SETMODE(spi, SPIDEV_MODE0); SPI_SELECT(spi, SPIDEV_FLASH, false); /* set 0 dummy cycles */ //SPI_SEND(spi, if (spi == NULL) errx(1, "failed to locate spi bus"); /* start the RAMTRON driver, attempt 5 times */ for (int i = 0; i < 10; i++) { mtd_dev = m25p_initialize(spi); if (mtd_dev) { /* abort on first valid result */ if (i > 0) { warnx("warning: mtd needed %d attempts to attach", i + 1); } break; } } /* if last attempt is still unsuccessful, abort */ if (mtd_dev == NULL) errx(1, "failed to initialize mtd driver"); int ret = mtd_dev->ioctl(mtd_dev, MTDIOC_SETSPEED, (unsigned long)10*1000*1000); if (ret != OK) warnx(1, "failed to set bus speed"); attached = true; }
static void ramtron_lock(FAR struct ramtron_dev_s *priv) { /* On SPI busses where there are multiple devices, it will be necessary to * lock SPI to have exclusive access to the busses for a sequence of * transfers. The bus should be locked before the chip is selected. * * This is a blocking call and will not return until we have exclusiv access to * the SPI buss. We will retain that exclusive access until the bus is unlocked. */ (void)SPI_LOCK(priv->dev, true); /* After locking the SPI bus, the we also need call the setfrequency, setbits, and * setmode methods to make sure that the SPI is properly configured for the device. * If the SPI buss is being shared, then it may have been left in an incompatible * state. */ SPI_SETMODE(priv->dev, SPIDEV_MODE3); SPI_SETBITS(priv->dev, 8); (void)SPI_SETFREQUENCY(priv->dev, priv->speed); }
static void ee25xx_lock(FAR struct spi_dev_s *dev) { /* On SPI buses where there are multiple devices, it will be necessary to * lock SPI to have exclusive access to the buses for a sequence of * transfers. The bus should be locked before the chip is selected. * * This is a blocking call and will not return until we have exclusive * access to the SPI bus. We will retain that exclusive access until the * bus is unlocked. */ (void)SPI_LOCK(dev, true); /* After locking the SPI bus, the we also need call the setfrequency, * setbits, and setmode methods to make sure that the SPI is properly * configured for the device. If the SPI bus is being shared, then it may * have been left in an incompatible state. */ SPI_SETMODE(dev, CONFIG_EE25XX_SPIMODE); SPI_SETBITS(dev, 8); (void)SPI_HWFEATURES(dev, 0); (void)SPI_SETFREQUENCY(dev, 10000000); /* This is the default speed */ }
bool iotjs_spi_transfer(iotjs_spi_t* spi) { iotjs_spi_platform_data_t* platform_data = spi->platform_data; struct spi_dev_s* spi_dev = platform_data->spi_dev; SPI_LOCK(spi_dev, true); SPI_SETFREQUENCY(spi_dev, spi->max_speed); SPI_SETMODE(spi_dev, spi->mode); SPI_SETBITS(spi_dev, spi->bits_per_word); // Select the SPI iotjs_gpio_write_nuttx(platform_data->cs_chip, false); SPI_EXCHANGE(spi_dev, spi->tx_buf_data, spi->rx_buf_data, spi->buf_len); // Unselect the SPI device iotjs_gpio_write_nuttx(platform_data->cs_chip, true); SPI_LOCK(spi_dev, false); return true; }
__EXPORT int board_app_initialize(uintptr_t arg) { #if defined(CONFIG_HAVE_CXX) && defined(CONFIG_HAVE_CXXINITIALIZE) /* run C++ ctors before we go any further */ up_cxxinitialize(); # if defined(CONFIG_EXAMPLES_NSH_CXXINITIALIZE) # error CONFIG_EXAMPLES_NSH_CXXINITIALIZE Must not be defined! Use CONFIG_HAVE_CXX and CONFIG_HAVE_CXXINITIALIZE. # endif #else # error platform is dependent on c++ both CONFIG_HAVE_CXX and CONFIG_HAVE_CXXINITIALIZE must be defined. #endif /* configure the high-resolution time/callout interface */ hrt_init(); /* configure the DMA allocator */ if (board_dma_alloc_init() < 0) { message("DMA alloc FAILED"); } /* configure CPU load estimation */ #ifdef CONFIG_SCHED_INSTRUMENTATION cpuload_initialize_once(); #endif /* set up the serial DMA polling */ static struct hrt_call serial_dma_call; struct timespec ts; /* * Poll at 1ms intervals for received bytes that have not triggered * a DMA event. */ ts.tv_sec = 0; ts.tv_nsec = 1000000; hrt_call_every(&serial_dma_call, ts_to_abstime(&ts), ts_to_abstime(&ts), (hrt_callout)stm32_serial_dma_poll, NULL); #if defined(CONFIG_STM32_BBSRAM) /* NB. the use of the console requires the hrt running * to poll the DMA */ /* Using Battery Backed Up SRAM */ int filesizes[CONFIG_STM32_BBSRAM_FILES + 1] = BSRAM_FILE_SIZES; stm32_bbsraminitialize(BBSRAM_PATH, filesizes); #if defined(CONFIG_STM32_SAVE_CRASHDUMP) /* Panic Logging in Battery Backed Up Files */ /* * In an ideal world, if a fault happens in flight the * system save it to BBSRAM will then reboot. Upon * rebooting, the system will log the fault to disk, recover * the flight state and continue to fly. But if there is * a fault on the bench or in the air that prohibit the recovery * or committing the log to disk, the things are too broken to * fly. So the question is: * * Did we have a hard fault and not make it far enough * through the boot sequence to commit the fault data to * the SD card? */ /* Do we have an uncommitted hard fault in BBSRAM? * - this will be reset after a successful commit to SD */ int hadCrash = hardfault_check_status("boot"); if (hadCrash == OK) { message("[boot] There is a hard fault logged. Hold down the SPACE BAR," \ " while booting to halt the system!\n"); /* Yes. So add one to the boot count - this will be reset after a successful * commit to SD */ int reboots = hardfault_increment_reboot("boot", false); /* Also end the misery for a user that holds for a key down on the console */ int bytesWaiting; ioctl(fileno(stdin), FIONREAD, (unsigned long)((uintptr_t) &bytesWaiting)); if (reboots > 2 || bytesWaiting != 0) { /* Since we can not commit the fault dump to disk. Display it * to the console. */ hardfault_write("boot", fileno(stdout), HARDFAULT_DISPLAY_FORMAT, false); message("[boot] There were %d reboots with Hard fault that were not committed to disk - System halted %s\n", reboots, (bytesWaiting == 0 ? "" : " Due to Key Press\n")); /* For those of you with a debugger set a break point on up_assert and * then set dbgContinue = 1 and go. */ /* Clear any key press that got us here */ static volatile bool dbgContinue = false; int c = '>'; while (!dbgContinue) { switch (c) { case EOF: case '\n': case '\r': case ' ': continue; default: putchar(c); putchar('\n'); switch (c) { case 'D': case 'd': hardfault_write("boot", fileno(stdout), HARDFAULT_DISPLAY_FORMAT, false); break; case 'C': case 'c': hardfault_rearm("boot"); hardfault_increment_reboot("boot", true); break; case 'B': case 'b': dbgContinue = true; break; default: break; } // Inner Switch message("\nEnter B - Continue booting\n" \ "Enter C - Clear the fault log\n" \ "Enter D - Dump fault log\n\n?>"); fflush(stdout); if (!dbgContinue) { c = getchar(); } break; } // outer switch } // for } // inner if } // outer if #endif // CONFIG_STM32_SAVE_CRASHDUMP #endif // CONFIG_STM32_BBSRAM /* initial LED state */ drv_led_start(); led_off(LED_RED); led_off(LED_GREEN); led_off(LED_BLUE); /* Configure SPI-based devices */ spi1 = stm32_spibus_initialize(1); if (!spi1) { message("[boot] FAILED to initialize SPI port 1\n"); board_autoled_on(LED_RED); return -ENODEV; } /* Default SPI1 to 1MHz and de-assert the known chip selects. */ SPI_SETFREQUENCY(spi1, 10000000); SPI_SETBITS(spi1, 8); SPI_SETMODE(spi1, SPIDEV_MODE3); SPI_SELECT(spi1, PX4_SPIDEV_GYRO, false); SPI_SELECT(spi1, PX4_SPIDEV_HMC, false); SPI_SELECT(spi1, PX4_SPIDEV_MPU, false); up_udelay(20); /* Get the SPI port for the FRAM */ spi2 = stm32_spibus_initialize(2); if (!spi2) { message("[boot] FAILED to initialize SPI port 2\n"); board_autoled_on(LED_RED); return -ENODEV; } /* Default SPI2 to 12MHz and de-assert the known chip selects. * MS5611 has max SPI clock speed of 20MHz */ // XXX start with 10.4 MHz and go up to 20 once validated SPI_SETFREQUENCY(spi2, 20 * 1000 * 1000); SPI_SETBITS(spi2, 8); SPI_SETMODE(spi2, SPIDEV_MODE3); SPI_SELECT(spi2, SPIDEV_FLASH, false); SPI_SELECT(spi2, PX4_SPIDEV_BARO, false); #ifdef CONFIG_MMCSD /* First, get an instance of the SDIO interface */ sdio = sdio_initialize(CONFIG_NSH_MMCSDSLOTNO); if (!sdio) { message("[boot] Failed to initialize SDIO slot %d\n", CONFIG_NSH_MMCSDSLOTNO); return -ENODEV; } /* Now bind the SDIO interface to the MMC/SD driver */ int ret = mmcsd_slotinitialize(CONFIG_NSH_MMCSDMINOR, sdio); if (ret != OK) { message("[boot] Failed to bind SDIO to the MMC/SD driver: %d\n", ret); return ret; } /* Then let's guess and say that there is a card in the slot. There is no card detect GPIO. */ sdio_mediachange(sdio, true); #endif return OK; }
__EXPORT int nsh_archinitialize(void) { int result; message("\n"); /* configure always-on ADC pins */ stm32_configgpio(GPIO_ADC1_IN0); stm32_configgpio(GPIO_ADC1_IN10); stm32_configgpio(GPIO_ADC1_IN11); stm32_configgpio(GPIO_UART_SBUS_INVERTER); #ifdef CONFIG_RC_INPUTS_TYPE(RC_INPUT_SBUS) stm32_gpiowrite(GPIO_UART_SBUS_INVERTER, 1); #else stm32_gpiowrite(GPIO_UART_SBUS_INVERTER, 0); #endif /* configure the high-resolution time/callout interface */ hrt_init(); /* configure CPU load estimation */ #ifdef CONFIG_SCHED_INSTRUMENTATION cpuload_initialize_once(); #endif /* initial BUZZER state */ drv_buzzer_start(); buzzer_off(BUZZER_EXT); /* initial LED state */ drv_led_start(); led_off(LED_AMBER); led_off(LED_BLUE); led_off(LED_GREEN); led_off(LED_EXT1); led_off(LED_EXT2); /* Configure SPI-based devices */ message("[boot] Initializing SPI port 1\n"); spi1 = up_spiinitialize(1); if (!spi1) { message("[boot] FAILED to initialize SPI port 1\r\n"); led_on(LED_AMBER); return -ENODEV; } /* Default SPI1 to 1MHz and de-assert the known chip selects. */ SPI_SETFREQUENCY(spi1, 10000000); SPI_SETBITS(spi1, 8); SPI_SETMODE(spi1, SPIDEV_MODE3); SPI_SELECT(spi1, GPIO_SPI_CS_MS5611, false); SPI_SELECT(spi1, GPIO_SPI_CS_EXP_MS5611, false); SPI_SELECT(spi1, GPIO_SPI_CS_EXP_MPU6000, false); SPI_SELECT(spi1, GPIO_SPI_CS_EXP_HMC5983, false); SPI_SELECT(spi1, GPIO_SPI_CS_EXP_WIFI_EEPROM, false); up_udelay(20); message("[boot] Successfully initialized SPI port 1\r\n"); // message("[boot] Initializing Wireless Module\n"); // wireless_archinitialize(); message("[boot] Initializing SPI port 2\n"); spi2 = up_spiinitialize(2); if (!spi2) { message("[boot] FAILED to initialize SPI port 2\r\n"); led_on(LED_AMBER); return -ENODEV; } /* Default SPI2 to 1MHz and de-assert the known chip selects. */ SPI_SETFREQUENCY(spi2, 10000000); SPI_SETBITS(spi2, 8); SPI_SETMODE(spi2, SPIDEV_MODE3); SPI_SELECT(spi2, GPIO_SPI_CS_MPU6000, false); SPI_SELECT(spi2, GPIO_SPI_CS_IMU_MS5611, false); SPI_SELECT(spi2, GPIO_SPI_CS_IMU_MPU6000, false); SPI_SELECT(spi2, GPIO_SPI_CS_IMU_HMC5983, false); SPI_SELECT(spi2, GPIO_SPI_CS_IMU_EEPROM, false); message("[boot] Successfully initialized SPI port 2\n"); /* Get the SPI port for the microSD slot */ message("[boot] Initializing SPI port 3\n"); spi3 = up_spiinitialize(3); if (!spi3) { message("[boot] FAILED to initialize SPI port 3\n"); led_on(LED_AMBER); return -ENODEV; } /* Default SPI3 to 1MHz and de-assert the known chip selects. */ SPI_SETFREQUENCY(spi3, 10000000); SPI_SETBITS(spi3, 8); SPI_SETMODE(spi3, SPIDEV_MODE3); SPI_SELECT(spi3, GPIO_SPI_CS_DATAFLASH, false); SPI_SELECT(spi3, GPIO_SPI_CS_EEPROM, false); SPI_SELECT(spi3, GPIO_SPI_CS_SDCARD, false); message("[boot] Successfully initialized SPI port 3\n"); /* Now bind the SPI interface to the MMCSD driver */ result = mmcsd_spislotinitialize(CONFIG_NSH_MMCSDMINOR, CONFIG_NSH_MMCSDSLOTNO, spi3); if (result != OK) { message("[boot] FAILED to bind SPI port 3 to the MMCSD driver\n"); led_on(LED_AMBER); return -ENODEV; } message("[boot] Successfully bound SPI port 3 to the MMCSD driver\n"); return OK; }