//*****************************************************************************
//
// Executes a Reset direct command on the TRF79x0.
//
// \param ucCommand is the command to be executed and must be a valid command
// code between 0 and 0x1f. Definitions for command codes are given in
// trf79x0.h.
//
// \note This function applies a special workaround as indicated in SLOA140.
//
// \return Returns void.
//
//*****************************************************************************
void
SSITRF79x0WriteResetFifoDirectCommand(unsigned char ucCommand)
{
unsigned char pucCommand[1];
//
// Assert the chip select for TRF79x0.
//
SSITRF79x0ChipSelectAssert();
//
// Add TRF79x0 direct command.
//
ucCommand = ucCommand | TRF79X0_CONTROL_CMD;
//
// Workaround as per SLOA140: When sending a command, add a dummy cycle.
//
pucCommand[0] = ucCommand;
SSITRF79x0GenericWrite(pucCommand, sizeof(pucCommand));
//
// Deassert the chip select for the TRF79x0.
//
SSITRF79x0ChipSelectDeAssert();
}
//*****************************************************************************
//
// Executes a direct command on the TRF79x0.
//
// \param ucCommand is the command to be executed and must be a valid command
// code between 0 and 0x1f. Definitions for command codes are given in
// trf79x0.h.
//
// \note This function applies a special workaround as indicated in SLOA140.
//
// \return Returns void.
//
//*****************************************************************************
void
SSITRF79x0WriteDirectCommand(unsigned char ucCommand)
{
unsigned char pucCommand[2];
//
// Assert the chip select for TRF79x0.
//
SSITRF79x0ChipSelectAssert();
//
// Add TRF79x0 direct command.
//
ucCommand = ucCommand | TRF79X0_CONTROL_CMD;
//
// Workaround as per SLOA140: When sending a command, add a dummy cycle.
//
pucCommand[0] = ucCommand;
pucCommand[1] = SSI_NO_DATA;
if(ucCommand == TRF79X0_RESET_FIFO_CMD)
{
SSITRF79x0GenericWrite(pucCommand, sizeof(pucCommand));
}
else
{
SSITRF79x0GenericWrite(pucCommand, 1);
}
//
// Deassert the chip select for the TRF79x0.
//
SSITRF79x0ChipSelectDeAssert();
}
//*****************************************************************************
//
// Stops a continuous write operation.
//
// This function deasserts the TRF79x0 chip select.
//
// \return None.
//
//*****************************************************************************
void
SSITRF79x0WriteContinuousStop(void)
{
//
// Deassert the chip select for the TRF79x0.
//
SSITRF79x0ChipSelectDeAssert();
}
//*****************************************************************************
//
// Reads a single value from TRF79x0 at the address provided.
//
// \param ucAddress is the register address to read and must be between 0
// and 0x1f, inclusive.
//
// This function asserts the TRF79x0 chip select, sends a read command,
// reads a single byte and then deasserts the chip select.
//
// \return This function returns the value that was stored in the given
// register.
//
//*****************************************************************************
unsigned char
SSITRF79x0ReadRegister(unsigned char ucAddress)
{
unsigned char ucData = 0;
//
// Assert the chip select for TRF79x0.
//
SSITRF79x0ChipSelectAssert();
//
// Isolate register address.
//
ucAddress = ucAddress & TRF79X0_ADDRESS_MASK;
//
// Add TRF79x0 read single command.
//
ucAddress |= TRF79X0_CONTROL_REG_READ | TRF79X0_REG_MODE_SINGLE;
SSITRF79x0GenericWrite(&ucAddress, 1);
if(RF_DAUGHTER_TRF7960)
{
//
// Switch from SPH=0 to SPH=1.
//
HWREG(TRF79X0_SSI_BASE + SSI_O_CR0) |= SSI_CR0_SPH;
}
//
// Get the data.
//
SSITRF79x0GenericRead(&ucData, 1);
if(RF_DAUGHTER_TRF7960)
{
//
// Switch from SPH=1 to SPH=0.
//
HWREG(TRF79X0_SSI_BASE + SSI_O_CR0) &= ~SSI_CR0_SPH;
}
//
// Deassert the chip select for the TRF79x0.
//
SSITRF79x0ChipSelectDeAssert();
return(ucData);
}
//*****************************************************************************
//
// Stop a continuous read operation.
//
// This function deasserts the TRF79x0 chip select.
//
// \return None.
//
//*****************************************************************************
void
SSITRF79x0ReadContinuousStop(void)
{
if(RF_DAUGHTER_TRF7960) {
//
// Switch from SPH=1 to SPH=0.
//
HWREG(TRF79X0_SSI_BASE + SSI_O_CR0) &= ~SSI_CR0_SPH;
}
//
// Deassert the chip select for the TRF79x0.
//
SSITRF79x0ChipSelectDeAssert();
}
//*****************************************************************************
//
// Writes a single value to TRF79x0 for address provided.
//
// \param ucAddress is the register address to write and must be between 0
// and 0x1f, inclusive.
// \param ucData is the data byte to write.
//
// This function asserts the TRF79x0 chip select, sends a write command,
// the single data value and then deasserts the chip select.
//
// \return None.
//
//*****************************************************************************
void
SSITRF79x0WriteRegister(unsigned char ucAddress, unsigned char ucData)
{
unsigned char pucCommand[2];
//
// Assert the chip select for TRF79x0.
//
SSITRF79x0ChipSelectAssert();
//
// Isolate register address.
//
ucAddress = ucAddress & TRF79X0_ADDRESS_MASK;
//
// Add TRF79x0 write single command.
//
ucAddress |= TRF79X0_CONTROL_REG_WRITE | TRF79X0_REG_MODE_SINGLE;
//
// Put the address and data into the buffer.
//
pucCommand[0] = ucAddress;
pucCommand[1] = ucData;
//
// Start the write.
//
SSITRF79x0GenericWrite(pucCommand, sizeof(pucCommand));
//
// Deassert the chip select for the TRF79x0.
//
SSITRF79x0ChipSelectDeAssert();
}
//*****************************************************************************
//
// Executes: writes a packet to the TRF79x0
//
// \param pui8Buffer
// \param ui8CRCBit
// \param ui8TotalLength
// \param ui8PayloadLength
// \param bHeaderEnable
//
// \note
//
// \return Returns void.
//
//*****************************************************************************
void SSITRF79x0WritePacket(uint8_t *pui8Buffer, uint8_t ui8CRCBit, \
uint8_t ui8TotalLength, uint8_t ui8PayloadLength, bool bHeaderEnable)
{
uint8_t ui8LengthLowerNibble = (ui8TotalLength & 0x0F) << 4;
uint8_t ui8LengthHigherNibble = (ui8TotalLength & 0xF0) >> 4;
uint8_t pui8HeaderData[2];
//
// Assert the chip select for TRF79x0.
//
SSITRF79x0ChipSelectAssert();
if(bHeaderEnable == true)
{
// RESET FIFO
//while (!(IFG2 & UCB0TXIFG)); // USCI_B0 TX buffer ready?
pui8HeaderData[0] = 0x8F; // Previous data to TX, RX
SSITRF79x0GenericWrite(pui8HeaderData,1);
//while(UCB0STAT & UCBUSY);
// CRC COMMAND
//while (!(IFG2 & UCB0TXIFG)); // USCI_B0 TX buffer ready?
pui8HeaderData[0] = 0x90 | (ui8CRCBit & 0x01); // Previous data to TX, RX
SSITRF79x0GenericWrite(pui8HeaderData,1);
//while(UCB0STAT & UCBUSY);
// WRITE TO LENGTH REG
//while (!(IFG2 & UCB0TXIFG)); // USCI_B0 TX buffer ready?
pui8HeaderData[0] = 0x3D;
SSITRF79x0GenericWrite(pui8HeaderData,1);
//while(UCB0STAT & UCBUSY);
// LENGTH HIGH Nibble
//while (!(IFG2 & UCB0TXIFG)); // USCI_B0 TX buffer ready?
pui8HeaderData[0] = ui8LengthHigherNibble; // Previous data to TX, RX
SSITRF79x0GenericWrite(pui8HeaderData,1);
//while(UCB0STAT & UCBUSY);
// LENGTH LOW Nibble
//while (!(IFG2 & UCB0TXIFG)); // USCI_B0 TX buffer ready?
pui8HeaderData[0] = ui8LengthLowerNibble; // Previous data to TX, RX
SSITRF79x0GenericWrite(pui8HeaderData,1);
//while(UCB0STAT & UCBUSY);
}
else
{
//while (!(IFG2 & UCB0TXIFG)); // USCI_B0 TX buffer ready?
pui8HeaderData[0] = 0x3F;
SSITRF79x0GenericWrite(pui8HeaderData,1);
//while(UCB0STAT & UCBUSY);
}
SSITRF79x0GenericWrite(pui8Buffer,ui8PayloadLength);
//while(ui8PayloadLength > 0)
//{
// while (!(IFG2 & UCB0TXIFG)); // USCI_B0 TX buffer ready?
// UCB0TXBUF = *pui8Buffer; // Previous data to TX, RX
// while(UCB0STAT & UCBUSY);
// pui8Buffer++;
// ui8PayloadLength--;
//}
//
// Deassert the chip select for the TRF79x0.
//
SSITRF79x0ChipSelectDeAssert();
}