int sc_main(int argc, char* argv[]) { sc_clock clk("clk",10,SC_NS); sc_signal<bool> enable, rw, clr, ci, co, zflag, oflag; sc_signal<sc_uint<16> > din0, din1, dout2; sc_signal<sc_uint<4> > op; sc_trace(fp,clk,"clk"); // Add signals to trace file sc_trace(fp,enable,"enable"); sc_trace(fp,rw,"rw"); sc_trace(fp,clr,"clr"); sc_trace(fp,ci,"ci"); sc_trace(fp,co,"co"); sc_trace(fp,zflag,"zflag"); sc_trace(fp,oflag,"oflag"); sc_trace(fp,din0,"din0"); sc_trace(fp,din1,"din1"); sc_trace(fp,dout2,"dout2"); sc_trace(fp,op,"op"); //datapath datapath DATAPATH("datapath"); DATAPATH.enable(enable); DATAPATH.rw(rw); DATAPATH.clk(clk); DATAPATH.clr(clr); DATAPATH.din0(din0); DATAPATH.din1(din1); DATAPATH.dout2(dout2); DATAPATH.ci(ci); DATAPATH.co(co); DATAPATH.zflag(zflag); DATAPATH.oflag(oflag); DATAPATH.op(op); //stim stim STIM("stim"); STIM.clk(clk); STIM.enable(enable); STIM.rw(rw); STIM.clr(clr); STIM.din0(din0); STIM.din1(din1); STIM.ci(ci); STIM.op(op); sc_start(1000, SC_NS); //start simulation sc_close_vcd_trace_file(fp); // close wave.vcd return 0; // Return OK, no errors. }
int sc_main(int argc, char* argv[]) { sc_signal<sc_int<4> > ain, bin, sum; sc_signal<bool> ci,co,zflag,oflag; sc_clock clk("clk",10,SC_NS,0.5); adder4 DUT("addsub4"); DUT.ain(ain); DUT.bin(bin); DUT.ci(ci); DUT.sum(sum); DUT.co(co); DUT.zf(zflag); DUT.of(oflag); stim STIM("stimulus"); STIM.clk(clk); STIM.ain(ain); STIM.bin(bin); STIM.ci(ci); check CHECK("checker"); CHECK.clk(clk); CHECK.ain(ain); CHECK.bin(bin); CHECK.ci(ci); CHECK.sum(sum); CHECK.co(co); CHECK.zflag(zflag); CHECK.oflag(oflag); sc_initialize(); sc_trace_file *tf = sc_create_vcd_trace_file("trace"); sc_trace(tf, ain, "ain"); sc_trace(tf, bin, "bin"); sc_trace(tf, ci, "add/sub"); sc_trace(tf, sum, "sum"); sc_trace(tf, co, "co"); sc_trace(tf, clk, "clk"); sc_trace(tf, zflag, "zero_flag"); sc_trace(tf, oflag, "overflow_flag"); sc_start(200, SC_NS); sc_close_vcd_trace_file(tf); return 0; // Return OK, no errors. }
int sc_main(int argc, char* argv[]) { sc_signal<sc_uint<8> > ain, bin, ra, rb; sc_signal<sc_uint<16> > result ,rc; sc_signal<bool> ready, start; sc_clock clk("clk",10,SC_NS,0.5); // Create a clock signal sc_trace(fp, clk, "clk"); sc_trace(fp, ain, "A"); sc_trace(fp, bin, "B"); sc_trace(fp, result, "C"); sc_trace(fp, ra, "RA"); sc_trace(fp, rb, "RB"); sc_trace(fp, rc, "RC"); sc_trace(fp, ready, "Ready"); sc_trace(fp, start, "Start"); multiplier DUT("multiplier"); // Instantiate Device Under Test DUT.ain(ain); DUT.bin(bin); DUT.ra(ra); DUT.rb(rb); DUT.rc(rc); DUT.ready(ready); DUT.start(start); DUT.result(result); DUT.clk(clk); stim STIM("stimulus"); // Instantiate stimulus generator STIM.clk(clk); STIM.ain(ain); STIM.bin(bin); STIM.ready(ready); STIM.start(start); check CHECK("check"); CHECK.clk(clk); CHECK.ain(ain); CHECK.bin(bin); CHECK.ready(ready); CHECK.result(result); sc_start(150, SC_NS); // Run simulation sc_close_vcd_trace_file(fp); return 0; // Return OK, no errors. }
int sc_main(int argc, char* argv[]) { sc_signal<sc_uint<4> > ain, bin, sum; sc_signal<bool> ci,co; sc_signal<bool> zflag,oflag ; sc_clock clk("clk",10,SC_NS,0.5); // Create a clock signal sc_trace_file *fp; fp=sc_create_vcd_trace_file("adder_wave"); fp->set_time_unit(1, SC_PS); sc_trace(fp,ain,"ain"); sc_trace(fp,bin,"bin"); sc_trace(fp,sum,"sum"); sc_trace(fp,ci,"ci"); sc_trace(fp,co,"co"); sc_trace(fp,zflag,"zflag"); sc_trace(fp,oflag,"oflag"); sc_trace(fp,clk,"clk"); adder DUT("adder"); // Instantiate Device Under Test DUT.ain(ain); // Connect ports DUT.bin(bin); DUT.ci(ci); DUT.sum(sum); DUT.oflag(oflag); DUT.zflag(zflag); DUT.co(co); stim STIM("stimulus"); // Instantiate stimulus generator STIM.clk(clk); STIM.ain(ain); STIM.bin(bin); STIM.ci(ci); check CHECK("checker"); // Instantiate checker CHECK.clk(clk); CHECK.ain(ain); CHECK.bin(bin); CHECK.ci(ci); CHECK.sum(sum); CHECK.oflag(oflag); CHECK.zflag(zflag); CHECK.co(co); sc_start(100, SC_NS); // Run simulation return 0; // Return OK, no errors. }
int sc_main(int argc, char* argv[]) { sc_signal<sc_int<4> > ain, bin, sum; sc_signal<bool> ci,co; sc_signal<bool> oflag, zflag; sc_clock clk("clk",10,SC_NS,0.5); // Create a clock signal adder DUT("adder"); // Instantiate Device Under Test DUT.ain(ain); // Connect ports DUT.bin(bin); DUT.ci(ci); DUT.sum(sum); DUT.co(co); DUT.oflag(oflag); DUT.zflag(zflag); stim STIM("stimulus"); // Instantiate stimulus generator STIM.clk(clk); STIM.ain(ain); STIM.bin(bin); STIM.ci(ci); check CHECK("checker"); // Instantiate checker CHECK.clk(clk); CHECK.ain(ain); CHECK.bin(bin); CHECK.ci(ci); CHECK.sum(sum); CHECK.co(co); sc_start(SC_ZERO_TIME); sc_trace_file *tf = sc_create_vcd_trace_file("trace"); sc_trace(tf, ain, "A"); sc_trace(tf, bin, "B"); sc_trace(tf, sum, "SUM"); sc_trace(tf, ci, "CIN"); sc_trace(tf, co, "COUT"); sc_trace(tf, oflag, "OFlag"); sc_trace(tf, zflag, "ZFlag"); sc_trace(tf, clk, "CLOCK"); sc_start(10000, SC_NS); sc_close_vcd_trace_file(tf); return 0; // Return OK, no errors. }
int sc_main(int argc, char* argv[]) { sc_signal<sc_uint<8> > A0, A1, A2, A3; sc_signal<sc_uint<8> > outbuf; sc_signal<sc_uint<8> > avg; sc_clock clk("clk", 10, SC_NS, 0.5); reduction DUT("reduction"); DUT.clk(clk); DUT.A0(A0); DUT.A1(A1); DUT.A2(A2); DUT.A3(A3); DUT.avg(avg); stim STIM("stimulus"); STIM.clk(clk); STIM.A0(A0); STIM.A1(A1); STIM.A2(A2); STIM.A3(A3); outputcollect OUTCL("outputcollect"); OUTCL.clk(clk); OUTCL.avg(avg); check CHECK("checker"); CHECK.clk(clk); CHECK.avg(avg); sc_start(SC_ZERO_TIME); sc_trace_file *tf = sc_create_vcd_trace_file("trace"); sc_trace(tf, A0, "A0"); sc_trace(tf, A1, "A1"); sc_trace(tf, A2, "A2"); sc_trace(tf, A3, "A3"); sc_trace(tf, avg, "AVG"); sc_trace(tf, clk, "CLOCK"); sc_start(10000000, SC_NS); sc_close_vcd_trace_file(tf); return 0; }
int sc_main(int argc, char* argv[]) { sc_signal<bool> enable, rw, clr; sc_clock clk("clk",10,SC_NS); sc_signal<sc_uint<32> > din, dout; sc_trace_file *fp; // VCD filepointer fp=sc_create_vcd_trace_file("wave");// Create wave.vcd file sc_trace(fp,clk,"clk"); // Add signals to trace file sc_trace(fp,enable,"enable"); sc_trace(fp,rw,"rw"); sc_trace(fp,clr,"clr"); sc_trace(fp,din,"din"); sc_trace(fp,dout,"dout"); //register reg REG("reg"); REG.clk(clk); REG.enable(enable); REG.rw(rw); REG.clr(clr); REG.din(din); REG.dout(dout); //stim stim STIM("stim"); STIM.clk(clk); STIM.enable(enable); STIM.rw(rw); STIM.clr(clr); STIM.din(din); sc_start(1000, SC_NS); //start simulation sc_close_vcd_trace_file(fp); // close wave.vcd return 0; // Return OK, no errors. }
int sc_main(int argc, char* argv[]) { sc_signal<sc_uint<N_BIT_OPERATION> > QQ, DD, MM, AA; sc_clock clk("clk", 10, SC_NS, 0.5); devider DUT("devider"); DUT.QQ(QQ); DUT.DD(DD); DUT.MM(MM); DUT.AA(AA); stim STIM("stimulus"); STIM.DD(DD); STIM.MM(MM); STIM.clk(clk); print PRINT("print"); PRINT.clk(clk); PRINT.QQ(QQ); PRINT.DD(DD); PRINT.MM(MM); PRINT.AA(AA); sc_start(SC_ZERO_TIME); sc_trace_file *tf = sc_create_vcd_trace_file("trace"); sc_trace(tf, QQ, "Q"); sc_trace(tf, DD, "D"); sc_trace(tf, MM, "M"); sc_trace(tf, AA, "A"); sc_trace(tf, clk, "CLOCK"); sc_start(10000, SC_NS); sc_close_vcd_trace_file(tf); return 0; }
int sc_main(int argc, char *argv[]) { // signals sc_signal<sc_uint<NN_HALF_DIGIT_BITS> > multiplier, multiplicand, HI_mux_zero, carry_mux_zero, LO_LSB, HI_LSB; sc_signal<sc_uint<NN_DIGIT_BITS> > product; sc_signal<sc_logic> HI_mux_sel, LO_mux_sel, HI_mux2_sel, carry_mux_sel; sc_signal<sc_logic> HI_reg_load, LO_reg_load, rshift_load; sc_signal<sc_logic> DONE; sc_signal<sc_logic> reset; //sc_signal<sc_uint<input_length> > HI_OUT; //sc_signal<sc_uint<input_length> > LO_OUT; //sc_signal<sc_uint<product_length> > Z_OUT; //sc_signal<sc_logic> carry_IN; //sc_signal<sc_logic> carry_OUT; // clock //sc_signal<sc_logic> reset, load; sc_clock clock("clock", 10, SC_NS, 0.5, 0, SC_NS, true); // instancess datapath DP("DP"); ctrl CTRL("CTRL"); stim STIM("STIM"); mon MON("MON"); //interconnections DP.reset(reset); DP.clock(clock); DP.multiplier(multiplier); DP.multiplicand(multiplicand); DP.HI_mux_zero(HI_mux_zero); DP.carry_mux_zero(carry_mux_zero); DP.product(product); DP.LO_LSB(LO_LSB); DP.HI_LSB(HI_LSB); DP.HI_mux_sel(HI_mux_sel); DP.LO_mux_sel(LO_mux_sel); DP.HI_mux2_sel(HI_mux2_sel); DP.carry_mux_sel(carry_mux_sel); DP.HI_reg_load(HI_reg_load); DP.LO_reg_load(LO_reg_load); DP.rshift_load(rshift_load); CTRL.reset(reset); CTRL.clock(clock); CTRL.LO_LSB(LO_LSB); CTRL.HI_mux_sel(HI_mux_sel); CTRL.LO_mux_sel(LO_mux_sel); CTRL.HI_mux2_sel(HI_mux2_sel); CTRL.carry_mux_sel(carry_mux_sel); CTRL.HI_reg_load(HI_reg_load); CTRL.LO_reg_load(LO_reg_load); CTRL.rshift_load(rshift_load); CTRL.DONE(DONE); STIM.reset(reset); STIM.clock(clock); STIM.HI_mux_zero(HI_mux_zero); STIM.carry_mux_zero(carry_mux_zero); STIM.multiplier(multiplier); STIM.multiplicand(multiplicand); MON.clock(clock); MON.product(product); MON.DONE(DONE); // instances /* splitter SPLITTER("RSHIFT"); stim STIM("STIM"); mon MON("MON"); // interconnections SPLITTER.A_IN(A_IN); SPLITTER.HI_OUT(HI_OUT); SPLITTER.LO_OUT(LO_OUT); STIM.A_IN(A_IN); STIM.clock(clock); MON.HI_OUT(HI_OUT); MON.LO_OUT(LO_OUT); MON.clock(clock); */ // adder interconnections // ADD.A_IN(A_IN); // ADD.B_IN(B_IN); // ADD.Z_OUT(Z_OUT); // ADD.carry_OUT(carry_OUT); // STIM.A_IN(A_IN); // STIM.B_IN(B_IN); // STIM.clock(clock); // MON.Z_OUT(Z_OUT); // MON.carry_OUT(carry_OUT); // MON.clock(clock); // // REG interconnections // REG.A_IN(A_IN); // REG.B_OUT(B_OUT); // REG.reset(reset); // REG.load(load); // REG.clock(clock); // STIM.A_IN(A_IN); // STIM.reset(reset); // STIM.load(load); // STIM.clock(clock); // MON.B_OUT(B_OUT); // MON.clock(clock); //traces sc_trace_file *tf = sc_create_vcd_trace_file("gcd_trace"); tf->set_time_unit(1, SC_NS); //sc_trace(tf, X_IN, "X_IN"); //sc_trace(tf, Y_IN, "Y_IN"); sc_trace(tf, reset, "reset"); sc_trace(tf, clock, "clock"); //sc_trace(tf, Z_OUT, "Z_OUT"); sc_trace(tf, DP.LO_mux.A_IN, "LO_mux.A_IN"); sc_trace(tf, DP.LO_mux.B_IN, "LO_mux.B_IN"); sc_trace(tf, DP.LO_mux.Z_OUT, "LO_mux.Z_OUT"); sc_trace(tf, DP.LO_mux.sel, "LO_mux.sel"); sc_trace(tf, DP.LO_reg.A_IN, "LO_reg.A_IN"); sc_trace(tf, DP.LO_reg.load, "LO_reg.load"); sc_trace(tf, DP.LO_reg.Z_OUT, "LO_reg.Z_OUT"); sc_trace(tf, DP.LO_reg.LSB, "LO_reg.LSB"); sc_trace(tf, DP.HI_mux.A_IN, "HI_mux.A_IN"); sc_trace(tf, DP.HI_mux.B_IN, "HI_mux.B_IN"); sc_trace(tf, DP.HI_mux.Z_OUT, "HI_mux.Z_OUT"); sc_trace(tf, DP.HI_mux.sel, "HI_mux.sel"); sc_trace(tf, DP.rshifter.A_IN, "rshifter.A_IN"); sc_trace(tf, DP.rshifter.B_IN, "rshifter.B_IN"); sc_trace(tf, DP.rshifter.carry_IN, "rshifter.carry_IN"); sc_trace(tf, DP.rshifter.Z_OUT, "rshifter.Z_OUT"); sc_trace(tf, DP.rshifter.product_OUT, "rshifter.product_OUT"); sc_trace(tf, DP.rshifter.load, "rshifter.load"); //sc_trace(tf, DP.product, "DP.product"); sc_trace(tf, DP.adder.A_IN, "adder.A_IN"); sc_trace(tf, DP.adder.B_IN, "adder.B_IN"); sc_trace(tf, DP.adder.Z_OUT, "adder.Z_OUT"); sc_trace(tf, DP.adder.carry_OUT, "adder.carry_OUT"); // sc_trace(tf, GCD.ymux_sel, "ymux_sel"); // sc_trace(tf, GCD.amux_sel, "amux_sel"); // sc_trace(tf, GCD.bmux_sel, "bmux_sel"); // sc_trace(tf, GCD.xreg_load, "xreg_load"); // sc_trace(tf, GCD.yreg_load, "yreg_load"); // sc_trace(tf, GCD.zreg_load, "zreg_load"); // sc_trace(tf, GCD.EQ, "EQ"); // sc_trace(tf, GCD.GT, "GT"); // sc_trace(tf, GCD.LT, "LT"); // sc_trace(tf, GCD.DP.x_n, "x_n"); // sc_trace(tf, GCD.DP.y_n, "y_n"); // sc_trace(tf, GCD.DP.x, "x"); // sc_trace(tf, GCD.DP.y, "y"); // sc_trace(tf, GCD.DP.sub_A, "sub_A"); // sc_trace(tf, GCD.DP.sub_B, "sub_B"); // sc_trace(tf, GCD.DP.sub_out, "sub_out"); // sc_trace(tf, GCD.CL.state, "state"); // sc_trace(tf, GCD.CL.next_state, "next_state"); sc_start(3000, SC_NS); sc_close_vcd_trace_file(tf); return(0); }