void usb_spi_task(void)
{
/* Remap SPI2 to DMA channels 6 and 7 */
STM32_SYSCFG_CFGR1 |= (1 << 24);
gpio_config_module(MODULE_SPI_MASTER, 1);
/* Set all four SPI pins to high speed */
STM32_GPIO_OSPEEDR(GPIO_B) |= 0xff000000;
/* Enable clocks to SPI2 module */
STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;
/* Reset SPI2 */
STM32_RCC_APB1RSTR |= STM32_RCC_PB1_SPI2;
STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_SPI2;
spi_enable(1);
while (1) {
task_wait_event(-1);
while (usb_spi_service_request(&usb_spi))
;
}
}
/**
* Enable and disable SPI for case closed debugging. This forces the AP into
* reset while SPI is enabled, thus preventing contention on the SPI interface.
*/
void usb_spi_board_enable(struct usb_spi_config const *config)
{
/* Place AP into reset */
gpio_set_level(GPIO_PMIC_WARM_RESET_L, 0);
/* Configure SPI GPIOs */
gpio_config_module(MODULE_SPI_FLASH, 1);
gpio_set_flags(SPI_FLASH_DEVICE->gpio_cs, GPIO_OUT_HIGH);
/* Set all four SPI pins to high speed */
/* pins B10/B14/B15 and B9 */
STM32_GPIO_OSPEEDR(GPIO_B) |= 0xf03c0000;
/* Enable clocks to SPI2 module */
STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;
/* Reset SPI2 */
STM32_RCC_APB1RSTR |= STM32_RCC_PB1_SPI2;
STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_SPI2;
/* Enable SPI LDO to power the flash chip */
gpio_set_level(GPIO_VDDSPI_EN, 1);
spi_enable(CONFIG_SPI_FLASH_PORT, 1);
}
static void board_init_spi2(void)
{
/* Remap SPI2 to DMA channels 6 and 7 */
STM32_SYSCFG_CFGR1 |= (1 << 24);
/* Set pin NSS to general purpose output mode (01b). */
/* Set pins SCK, MISO, and MOSI to alternate function (10b). */
STM32_GPIO_MODER(GPIO_B) &= ~0xff000000;
STM32_GPIO_MODER(GPIO_B) |= 0xa9000000;
/* Set all four pins to alternate function 0 */
STM32_GPIO_AFRH(GPIO_B) &= ~(0xffff0000);
/* Set all four pins to output push-pull */
STM32_GPIO_OTYPER(GPIO_B) &= ~(0xf000);
/* Set pullup on NSS */
STM32_GPIO_PUPDR(GPIO_B) |= 0x1000000;
/* Set all four pins to high speed */
STM32_GPIO_OSPEEDR(GPIO_B) |= 0xff000000;
/* Reset SPI2 */
STM32_RCC_APB1RSTR |= (1 << 14);
STM32_RCC_APB1RSTR &= ~(1 << 14);
/* Enable clocks to SPI2 module */
STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;
}
static void spi_init(void)
{
stm32_spi_regs_t *spi = STM32_SPI1_REGS;
/* Reset the SPI Peripheral to clear any existing weird states. */
/* Fix for bug chrome-os-partner:31390 */
enabled = 0;
state = SPI_STATE_DISABLED;
STM32_RCC_APB2RSTR |= (1 << 12);
STM32_RCC_APB2RSTR &= ~(1 << 12);
/* 40 MHz pin speed */
STM32_GPIO_OSPEEDR(GPIO_A) |= 0xff00;
/* Enable clocks to SPI1 module */
STM32_RCC_APB2ENR |= STM32_RCC_PB2_SPI1;
/*
* Enable rx/tx DMA and get ready to receive our first transaction and
* "disable" FIFO by setting event to happen after only 1 byte
*/
spi->cr2 = STM32_SPI_CR2_RXDMAEN | STM32_SPI_CR2_TXDMAEN |
STM32_SPI_CR2_FRXTH;
/* Enable the SPI peripheral */
spi->cr1 |= STM32_SPI_CR1_SPE;
gpio_enable_interrupt(GPIO_SPI1_NSS);
/* If chipset is already on, prepare for transactions */
if (chipset_in_state(CHIPSET_STATE_ON))
spi_chipset_startup();
}
static void pins_init(void)
{
/* Pin usage:
* PA0 (OUT - OD GPIO) : Wakeup on Vnc / Threshold
* PA1 (ANALOG - ADC_IN1) : CC sense
* PA2 (ANALOG - ADC_IN2) : Current sense
* PA3 (ANALOG - ADC_IN3) : Voltage sense
* PA4 (OUT - OD GPIO) : PD TX enable
* PA5 (AF0 - SPI1_SCK) : TX clock in
* PA6 (AF0 - SPI1_MISO) : PD TX
* PA7 (AF5 - TIM3_CH2) : PD RX
* PA9 (AF1 - UART1_TX) : [DEBUG] UART TX
* PA10 (AF1 - UART1_RX) : [DEBUG] UART RX
* PA13 (OUT - GPIO) : voltage select[0]
* PA14 (OUT - GPIO) : voltage select[1]
* PB1 (AF0 - TIM14_CH1) : TX clock out
* PF0 (OUT - GPIO) : LM5050 FET driver off
* PF1 (OUT - GPIO) : discharge FET
*/
STM32_GPIO_ODR(GPIO_A) = /* HIGH(0) | */ HIGH(4);
STM32_GPIO_AFRL(GPIO_A) = AFx(7, 1);
STM32_GPIO_AFRH(GPIO_A) = AFx(9, 1) | AFx(10, 1);
STM32_GPIO_OTYPER(GPIO_A) = ODR(0) | ODR(4);
STM32_GPIO_OSPEEDR(GPIO_A) = HISPEED(5) | HISPEED(6) | HISPEED(7);
STM32_GPIO_MODER(GPIO_A) = OUT(0) | ANALOG(1) | ANALOG(2) | ANALOG(3)
| OUT(4) | AF(5) /*| AF(6)*/ | AF(7) | AF(9)
| AF(10) | OUT(13) | OUT(14);
/* set PF0 / PF1 as output */
STM32_GPIO_ODR(GPIO_F) = 0;
STM32_GPIO_MODER(GPIO_F) = OUT(0) | OUT(1);
STM32_GPIO_OTYPER(GPIO_F) = 0;
/* Set PB1 as AF0 (TIM14_CH1) */
STM32_GPIO_OSPEEDR(GPIO_B) = HISPEED(1);
STM32_GPIO_MODER(GPIO_B) = AF(1);
}
void usb_spi_board_enable(struct usb_spi_config const *config)
{
/* Remap SPI2 to DMA channels 6 and 7 */
STM32_SYSCFG_CFGR1 |= (1 << 24);
/* Configure SPI GPIOs */
gpio_config_module(MODULE_SPI_FLASH, 1);
/* Set all four SPI pins to high speed */
STM32_GPIO_OSPEEDR(GPIO_B) |= 0xff000000;
/* Enable clocks to SPI2 module */
STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;
/* Reset SPI2 */
STM32_RCC_APB1RSTR |= STM32_RCC_PB1_SPI2;
STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_SPI2;
spi_enable(CONFIG_SPI_FLASH_PORT, 1);
}
void usb_spi_board_enable(struct usb_spi_config const *config)
{
/* Remap SPI2 to DMA channels 6 and 7 */
/* STM32F072 SPI2 defaults to using DMA channels 4 and 5 */
/* but cros_ec hardcodes a 6/7 assumption in registers.h */
STM32_SYSCFG_CFGR1 |= (1 << 24);
/* Configure SPI GPIOs */
gpio_config_module(MODULE_SPI_FLASH, 1);
/* Set all four SPI pins to high speed */
STM32_GPIO_OSPEEDR(GPIO_B) |= 0xff000000;
/* Enable clocks to SPI2 module */
STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;
/* Reset SPI2 */
STM32_RCC_APB1RSTR |= STM32_RCC_PB1_SPI2;
STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_SPI2;
spi_enable(CONFIG_SPI_FLASH_PORT, 1);
}
/* Initialize board. */
static void board_init(void)
{
int i;
/* Enable pericom BC1.2 interrupts. */
gpio_enable_interrupt(GPIO_USBC_BC12_INT_L);
/*
* Initialize AP console forwarding USART and queues.
*/
queue_init(&ap_usart_to_usb);
queue_init(&ap_usb_to_usart);
usart_init(&ap_usart);
/* Disable UART input when the Write Protect is enabled */
if (system_is_locked())
ap_usb.state->rx_disabled = 1;
/*
* Enable CC lines after all GPIO have been initialized. Note, it is
* important that this is enabled after the CC_DEVICE_ODL lines are
* set low to specify device mode.
*/
gpio_set_level(GPIO_USBC_CC_EN, 1);
/* Enable interrupts on VBUS transitions. */
gpio_enable_interrupt(GPIO_CHGR_ACOK);
/* Enable interrupts from BMI160 sensor. */
gpio_enable_interrupt(GPIO_ACC_IRQ1);
/* Enable interrupts from SI1141 sensor. */
gpio_enable_interrupt(GPIO_ALS_PROXY_INT_L);
if (board_has_spi_sensors()) {
for (i = MOTIONSENSE_TYPE_ACCEL;
i <= MOTIONSENSE_TYPE_MAG; i++) {
motion_sensors[i].addr =
BMI160_SET_SPI_ADDRESS(CONFIG_SPI_ACCEL_PORT);
}
/* SPI sensors: put back the GPIO in its expected state */
gpio_set_level(GPIO_SPI3_NSS, 1);
/* Enable SPI for BMI160 */
gpio_config_module(MODULE_SPI_MASTER, 1);
/* Set all four SPI3 pins to high speed */
/* pins C10/C11/C12 */
STM32_GPIO_OSPEEDR(GPIO_C) |= 0x03f00000;
/* pin A4 */
STM32_GPIO_OSPEEDR(GPIO_A) |= 0x00000300;
/* Enable clocks to SPI3 module */
STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI3;
/* Reset SPI3 */
STM32_RCC_APB1RSTR |= STM32_RCC_PB1_SPI3;
STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_SPI3;
spi_enable(CONFIG_SPI_ACCEL_PORT, 1);
CPRINTS("Board using SPI sensors");
} else { /* I2C sensors on rev v6/7/8 */
CPRINTS("Board using I2C sensors");
/*
* On EVT2, when the sensors are on the same bus as other
* sensors, motion task would not leave enough time for
* processing as soon as its frequency is around ~200Hz.
*/
motion_min_interval = 8 * MSEC;
}
}
