void bsp_reset(void)
{
rtems_interrupt_level level;
rtems_interrupt_disable(level);
/* Enable the watchdog timer, then wait for the world to end. */
ST_REG(ST_WDMR) = ST_WDMR_RSTEN | 1;
while(1);
}
void Clock_driver_support_initialize_hardware(void)
{
uint32_t st_str;
int slck;
/* the system timer is driven from SLCK */
slck = at91rm9200_get_slck();
st_pimr_value =
(((rtems_configuration_get_microseconds_per_tick() * slck) + (1000000/2))/ 1000000);
st_pimr_reload = st_pimr_value;
/* read the status to clear the int */
st_str = ST_REG(ST_SR);
/* set priority */
AIC_SMR_REG(AIC_SMR_SYSIRQ) = AIC_SMR_PRIOR(0x7);
/* set the timer value */
ST_REG(ST_PIMR) = st_pimr_reload;
}
/**
* Tests to see if clock interrupt is enabled, and returns 1 if so.
* If interrupt is not enabled, returns 0.
*
* If the interrupt is always on, this always returns 1.
*/
static int clock_isr_is_on(const rtems_irq_connect_data *irq)
{
/* check timer interrupt */
return ST_REG(ST_IMR) & ST_SR_PITS;
}
/**
* Disables clock interrupts
*
* If the interrupt is always on, this can be a NOP.
*/
static void clock_isr_off(const rtems_irq_connect_data *unused)
{
/* disable timer interrupt */
ST_REG(ST_IDR) = ST_SR_PITS;
}
